JPH04142767A - Lead frame for semiconductor - Google Patents
Lead frame for semiconductorInfo
- Publication number
- JPH04142767A JPH04142767A JP26576490A JP26576490A JPH04142767A JP H04142767 A JPH04142767 A JP H04142767A JP 26576490 A JP26576490 A JP 26576490A JP 26576490 A JP26576490 A JP 26576490A JP H04142767 A JPH04142767 A JP H04142767A
- Authority
- JP
- Japan
- Prior art keywords
- island
- lead
- corner
- semiconductor chip
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 239000000853 adhesive Substances 0.000 abstract description 9
- 230000000694 effects Effects 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 2
- 230000001070 adhesive effect Effects 0.000 description 8
- 238000013459 approach Methods 0.000 description 1
- 238000001125 extrusion Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体用リードフレームに関し、特にアイラン
ドの角にアイランド支持リードを結続しアイランド周囲
にリードを配置した多ビン半導体用リードフレームに関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a lead frame for semiconductors, and more particularly to a lead frame for multi-bin semiconductors in which island support leads are connected to the corners of the islands and leads are arranged around the islands.
従来の半導体用リードフレーム（以下リードフレームと
記す）は、第４図に示すように、アイランド１１とアイ
ランド支持リード２が結続される部分の形状を互いに直
交する直線で構成することが常である。In conventional lead frames for semiconductors (hereinafter referred to as lead frames), as shown in FIG. 4, the shape of the portion where the island 11 and the island support lead 2 are connected is usually configured with straight lines orthogonal to each other. be.
この従来のリードフレームでは、アイランド１１にマウ
ントされた半導体チ・ノブ３のアイランド支持リード２
結続部付近にある外部配線用Ｒ・７ド４からアイランド
支持リード２に隣接するり−ド５へワイヤを配線する場
合に、ワイヤがアイランド支持リード２と同じ方向、即
ち、アイランド１１に対し４５度に近い角度で配線され
る為に他の配線に比ベワイヤの長さのアイランド１１領
域内に占める割合が多くなる。In this conventional lead frame, the island support lead 2 of the semiconductor chip knob 3 mounted on the island 11 is
When wiring a wire from the external wiring R-7 dome 4 near the connection part to the dome 5 adjacent to the island support lead 2, the wire should be routed in the same direction as the island support lead 2, that is, with respect to the island 11. Since the wire is wired at an angle close to 45 degrees, the wire occupies a larger proportion of the length of the island 11 than other wires.
ワイヤの形状は、第５図に示すように、半導体チップ３
上の外部配線用パッド４がら一旦は真上に伸びなワイヤ
６が滑らがなカーブを描きながら頂点を通過後、なだら
かな加工を伴ってリード５へ向かう為、パッド４とリー
ド５間のワイヤ６を横切るアイランド１１の外周がリー
ド５側に近い程アイランド１１の外縁にワイヤ６が接触
する恐れが大きくなるという問題点がある。The shape of the wire is as shown in FIG.
The wire 6, which extends directly above the external wiring pad 4 above, passes through the apex while drawing a smooth curve, and then goes to the lead 5 with a gentle process, so the wire between the pad 4 and the lead 5 There is a problem that the closer the outer periphery of the island 11 that crosses the wire 6 to the lead 5 side, the greater the possibility that the wire 6 will come into contact with the outer edge of the island 11.
ワイヤ６がアイランド支持リード２の上を通過する場合
にもワイヤ６とアイランド支持リード２の交点がリード
５側に近ずく為、接触の恐れは増大するという問題点が
ある。Even when the wire 6 passes over the island support lead 2, the intersection point between the wire 6 and the island support lead 2 approaches the lead 5 side, so there is a problem that the risk of contact increases.
本発明の目的は、ワイヤがアイランドまたはアイランド
支持リードに接触することのないリードフレームを提供
することにある。It is an object of the present invention to provide a lead frame in which the wires do not contact the islands or island support leads.
本発明は、
ｌ、半導体チップを搭載するアイランドと、該アイラン
ドの角に結続するアイランド支持リードと、前記アイラ
ンドの周囲に配置されたリードとを有する半導体用リー
ドフレームにおいて、前記アイランド支持リードと結続
する前記アイランドの角を丸め、かつ、前記アイランド
支持リードを厚さと同一の巾となっている。The present invention provides: (1) a semiconductor lead frame having an island on which a semiconductor chip is mounted, island support leads connected to corners of the island, and leads arranged around the island; The corners of the connected islands are rounded, and the width of the island support lead is the same as the thickness.
２、前記アイランド支持リードと結続するアイランドの
角が面取りの形状となっている。2. The corner of the island connected to the island support lead is chamfered.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例の平面図、第２図は第１図の
リードフレームに半導体チップを搭載した部分拡大平面
図、第３図は半導体チップがアイランドに許容限度まで
ずれて固着された状態を示す平面図である。Fig. 1 is a plan view of one embodiment of the present invention, Fig. 2 is a partially enlarged plan view of a semiconductor chip mounted on the lead frame of Fig. 1, and Fig. 3 is a semiconductor chip fixed to the island with deviation to the permissible limit. FIG.
第１図〜第３図に示すように、アイランド１は、半導体
チップ３の搭載すれと接着剤のはみ出し７を許容する大
きさとなるよう寸法が決められる。As shown in FIGS. 1 to 3, the dimensions of the island 1 are determined to allow the mounting of the semiconductor chip 3 and the extrusion 7 of the adhesive.
半導体チップ３は、アイランド１上に接着剤により固着
されるが、確実な固着が確認できるように、半導体チッ
プ３より接着剤がはみ出すよう接着剤が供給される６接
着剤のはみ出し７は、半導体チップ３の角部では見られ
ない。従って、アイランド１の大きさは、半導体チップ
３の大きさ。The semiconductor chip 3 is fixed onto the island 1 with an adhesive. In order to confirm that the semiconductor chip 3 is firmly fixed, the adhesive is supplied in such a way that the adhesive protrudes from the semiconductor chip 3. It is not seen at the corner of chip 3. Therefore, the size of the island 1 is the same as the size of the semiconductor chip 3.
半導体チップ３搭載時のずれ及び接着剤のはみ出し巾ａ
で決まり、アイランド１角部の形状は接着剤のはみ出し
７を考慮せずともよい、接着剤はみ出し７がアイランド
１内に収まる許容限度まで半導体チップ３がずれた場合
を想定し、その際に、半導体チップ３角部に接する円を
アイランド１角部の形状としてもさしつかえない。Misalignment and adhesive protrusion width a when semiconductor chip 3 is mounted
The shape of the corner of the island 1 does not need to take into account the adhesive protrusion 7. Assuming that the semiconductor chip 3 is shifted to the allowable limit where the adhesive protrusion 7 falls within the island 1, in that case, A circle touching three corners of the semiconductor chip may be used as the shape of one corner of the island.
半導体チップ３角部に接する円の半径、即ち、アイラン
ド角部丸み半径Ｒは、次式で示される。The radius of the circle touching the three corners of the semiconductor chip, ie, the island corner radius R, is expressed by the following equation.
Ｒ＝３． ４ａ Ｃ（Ｒ＋ｒΣ ａ）２ ＝２Ｒ２よ
リ〕上述のように、アイランド１角部の形状を決めた
後、アイランド支持リード２をアイランド１角部に結続
するが、バッド４とリード５間を結ぶワイヤ６がアイラ
ンド支持リード２を横切らぬようアイランド支持リード
２の巾を強度及び加工を考慮した上で少くとも厚さと同
じ巾まで狭くする。R=3. 4a C(R+rΣ a)2 = 2R2] As mentioned above, after determining the shape of the corner of the island 1, the island support lead 2 is connected to the corner of the island 1, but between the pad 4 and the lead 5. In order to prevent the connecting wire 6 from crossing the island support lead 2, the width of the island support lead 2 is narrowed to at least the same width as the thickness, taking into consideration strength and processing.
第３図の状態においてチップ各部に接する面取りをアイ
ランド１角部に施しても同様の効果が得られる。In the state shown in FIG. 3, a similar effect can be obtained by chamfering the corner of the island 1 in contact with each part of the chip.
以上説明したように本発明は、機能を損なわない範囲て
アイランドの角を丸め、あるいは、面取し、かつ、アイ
ランド支持リードの巾を狭くすることにより、アイラン
ド支持リードに隣接するリードへワイヤを配線する場合
に於て、ワイヤの長さのアイランド領域内に占める割合
を少くできる為、ワイヤのアイランド外縁あるいはアイ
ランド支持リードへの接触が低減できるという効果を有
する。As explained above, in the present invention, the corners of the island are rounded or chamfered to the extent that the function is not impaired, and the width of the island support lead is narrowed, so that the wire can be routed to the lead adjacent to the island support lead. When wiring, the ratio of the length of the wire to the island area can be reduced, which has the effect of reducing the contact of the wire with the outer edge of the island or the island support lead.
従来のリードフレームでは、アイランド領域内に占める
ワイヤの長さの割合が３６％であったものが本実施例に
よるリードフレームで２８％に改善されることが判明し
ている。It has been found that in the conventional lead frame, the proportion of the length of the wire in the island area was 36%, but in the lead frame according to the present embodiment, this was improved to 28%.
第１図は本発明の一実施例の平面図、第２図は第１図の
リードフレームに半導体チップを搭載した部分拡大平面
図、第３図は半導体チップがアイランドに許容限度まで
ずれて固着された状態を示す平面図、第４図は従来のリ
ードフレームに半導体チップが搭載され配線された状態
の一例の平面図、第５図は半導体チップとリードを結ぶ
ワイヤの形状の一例の側面図である。
１．１１・・・アイランド、２・・・アイランド支持リ
ード、３・・・半導体チップ、４・・・パッド、５・・
・リード、６・・・ワイヤ、７・・・接着剤はみ出し。Fig. 1 is a plan view of one embodiment of the present invention, Fig. 2 is a partially enlarged plan view of a semiconductor chip mounted on the lead frame of Fig. 1, and Fig. 3 is a semiconductor chip fixed to the island with deviation to the permissible limit. 4 is a plan view of an example of a state in which a semiconductor chip is mounted on a conventional lead frame and wired, and FIG. 5 is a side view of an example of the shape of wires connecting the semiconductor chip and leads. It is. 1.11... Island, 2... Island support lead, 3... Semiconductor chip, 4... Pad, 5...
・Lead, 6... Wire, 7... Adhesive protruding.
Claims (1)
ドの角に結続するアイランド支持リードと、前記アイラ
ンドの周囲に配置されたリードとを有する半導体用リー
ドフレームにおいて、前記アイランド支持リードと結続
する前記アイランドの角を丸め、かつ、前記アイランド
支持リードを厚さと同一の巾としたことを特徴とする半
導体用リードフレーム。 ２、前記アイランド支持リードと結続するアイランドの
角を面取りの形状としたことを特徴とする請求項１記載
の半導体用リードフレーム。[Scope of Claims] 1. In a semiconductor lead frame having an island on which a semiconductor chip is mounted, island support leads connected to corners of the island, and leads arranged around the island, the island support A lead frame for a semiconductor, characterized in that the corners of the island connected to the lead are rounded, and the width of the island support lead is the same as the thickness. 2. The semiconductor lead frame according to claim 1, wherein the corner of the island connected to the island support lead is chamfered.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26576490A JPH04142767A (en) | 1990-10-03 | 1990-10-03 | Lead frame for semiconductor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26576490A JPH04142767A (en) | 1990-10-03 | 1990-10-03 | Lead frame for semiconductor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04142767A true JPH04142767A (en) | 1992-05-15 |
Family
ID=17421698
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26576490A Pending JPH04142767A (en) | 1990-10-03 | 1990-10-03 | Lead frame for semiconductor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04142767A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5594274A (en) * | 1993-07-01 | 1997-01-14 | Nec Corporation | Lead frame for use in a semiconductor device and method of manufacturing the semiconductor device using the same |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5516450A (en) * | 1978-07-24 | 1980-02-05 | Hitachi Ltd | Semiconductor device |
| JPS62188350A (en) * | 1986-02-14 | 1987-08-17 | Nec Ic Microcomput Syst Ltd | Lead frame |
| JPS63164254A (en) * | 1986-12-26 | 1988-07-07 | Hitachi Ltd | Semiconductor device |
-
1990
- 1990-10-03 JP JP26576490A patent/JPH04142767A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5516450A (en) * | 1978-07-24 | 1980-02-05 | Hitachi Ltd | Semiconductor device |
| JPS62188350A (en) * | 1986-02-14 | 1987-08-17 | Nec Ic Microcomput Syst Ltd | Lead frame |
| JPS63164254A (en) * | 1986-12-26 | 1988-07-07 | Hitachi Ltd | Semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5594274A (en) * | 1993-07-01 | 1997-01-14 | Nec Corporation | Lead frame for use in a semiconductor device and method of manufacturing the semiconductor device using the same |
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