JPS63289841A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS63289841A
JPS63289841A JP12521687A JP12521687A JPS63289841A JP S63289841 A JPS63289841 A JP S63289841A JP 12521687 A JP12521687 A JP 12521687A JP 12521687 A JP12521687 A JP 12521687A JP S63289841 A JPS63289841 A JP S63289841A
Authority
JP
Japan
Prior art keywords
contact hole
wiring
metal film
melting point
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12521687A
Other languages
Japanese (ja)
Inventor
Takaaki Kuwata
孝明 桑田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP12521687A priority Critical patent/JPS63289841A/en
Publication of JPS63289841A publication Critical patent/JPS63289841A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the generation of disconnection, electromigration, etc., by forming a high melting point metal film with an inclination on the contact hole wall in the direction of a first metal wiring. CONSTITUTION:A high melting point metal film 14 is buried in grooves formed on the side surface of a first metal wiring 11 in contact holes. On the side surface of the contact hole wall vertical to the first metal wiring 11 in the contact hole, the high melting point metal film 14 is left with an inclination. By anisotropic etching applying an etching gas having a large selection ratio between the high melting point metal film 14 and a second metal film 15, the second metal wiring 15 is formed so as to pass on the contact holes keeping a line width larger than or equal to the short side of the contact hole. Thereby, the wiring pitch is reduced, and the generation of disconnection, electromigration, etc., can be prevented.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に係り、特に多層金属配
線の金属配線間の接続方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of connecting metal wires in a multilayer metal wire.

〔従来の技術〕[Conventional technology]

従来、この種の金属配線間の接続方法は、コンタクト孔
を開孔すべき領域の第1の金属配線の線幅を、開孔すべ
きコンタクト孔の大きさよりも。
Conventionally, in this type of connection method between metal wirings, the line width of the first metal wiring in the region where the contact hole is to be formed is set to be larger than the size of the contact hole to be formed.

目金せずれのマージンを予め含んだ分だけ通常配線部分
に比べ太く形成する工程と、その領域の第1の層間絶縁
膜にコンタクト孔を異方性エツチングに依り開孔し、第
1の金属配線を露出させる工程と、第2の金属配線を、
前記コンタクト孔を目金せずれのマージンを予め持友せ
、完全に覆う様に、コンタクト孔部で通常配線部分に比
べ線幅を太く形成する様に、配線する工程とを含んで槽
底されていた。
A process of forming a contact hole thicker than a normal wiring part by an amount that includes a margin for misalignment of the metal plate in advance, and opening a contact hole in the first interlayer insulating film in that area by anisotropic etching, The process of exposing the wiring and the second metal wiring,
The bottom of the tank is formed, including the step of wiring the contact hole so as to maintain a margin for misalignment in advance and to completely cover the contact hole so that the line width is thicker than that of the normal wiring portion. was.

以下に、従来の製造方法を第2図−】乃至第2図(g)
を用いて説明する。第2図(劫セ平面図であり、第2図
ら)乃至(−ハエ種属に示し几断面図である。
Below, the conventional manufacturing method is shown in Figures 2-] to 2(g).
Explain using. FIG. 2 is a plan view of the fly, and FIG.

第2囚偽) 、 (d) 、 (f)は第2図(&)の
A−A’線にそつ九位置で見比断面図、第2図(c) 
、 (e) 、 (g)は第2図(a)のB−B’線に
そった位置で見た断面図である。
(2nd prisoner), (d), (f) are comparative cross-sectional views taken along line A-A' in Fig. 2 (&), Fig. 2 (c)
, (e) and (g) are cross-sectional views taken along line BB' in FIG. 2(a).

第2図ら) 、 (c)に示す様に、第1の金属配線(
膜厚5000A ) 21上の第1の層間絶縁膜22の
所定の位置に7オトレジスト#i23をパターン形成グ
する0通常、コンタクト孔25の端部と。
As shown in Figure 2, etc.) and (c), the first metal wiring (
A film thickness of 5000 A) is used to form a pattern of photoresist #i23 at a predetermined position of the first interlayer insulating film 22 on the film 21 (usually at the end of the contact hole 25).

第1の金属配線21の端部とは、目金せずれを考慮し、
0.4μm程度の目金せマージンを持tせである。
The end of the first metal wiring 21 is
It is necessary to have a margin of about 0.4 μm.

次に第2図(d) 、 (e)に示す様に、異方性エツ
チングにエフ、第1の層間絶縁膜(膜厚約500OA)
22をエツチングし、第1の金属配線2を露出させる。
Next, as shown in FIGS. 2(d) and 2(e), the first interlayer insulating film (film thickness of approximately 500 OA) was etched by anisotropic etching.
22 to expose the first metal wiring 2.

次に第2図(f) 、 (g)に示す様に、第2の金属
配線<ytii、厚約800OA )24を、コンタク
ト孔を目金せマージンを持って、完全に覆う様にコンタ
クト孔部では、線@を太して、形成する。こうして、第
2図(a)に示すような平面図が得られる。
Next, as shown in FIGS. 2(f) and 2(g), the second metal wiring <ytii, thickness of approximately 800 OA) 24 is inserted into the contact hole with a margin and completely covered. In the section, make the line @ thicker and form it. In this way, a plan view as shown in FIG. 2(a) is obtained.

〔発明が解決しょうとする問題点〕[Problem that the invention seeks to solve]

以上説明した、従来の配線接続方法に於いてa1コンタ
クト孔は必ず第1の金属配線21上に開孔されなければ
ならない。、なぜならば、第1の金属膜a21よりコン
タクト孔24が、例えば目金せずnなどに工9、はみ出
した場合、第1の金属配線21の側面に溝が形成され、
i@2の金属膜−24がその溝部でカバレッヂが悪くな
り、断線する可能性がある。従って、コンタクト孔24
を開孔する領域では、第1の金属膜a21の線幅をコン
タクト孔より目金せずれを考慮した分だけ広く(通常α
4μm)する必要がある。
In the conventional wiring connection method described above, the a1 contact hole must be formed above the first metal wiring 21. This is because, if the contact hole 24 protrudes from the first metal film a21, for example, without a metal fitting, a groove is formed on the side surface of the first metal wiring 21.
Coverage of the metal film 24 of i@2 becomes poor in the groove, and there is a possibility of disconnection. Therefore, the contact hole 24
In the area where the hole is to be drilled, the line width of the first metal film a21 is made wider than the contact hole by an amount that takes into account the misalignment of the metal fitting (usually α
4 μm).

まt、コンタクト孔24を覆う様に配線さnる第2の金
属膜@24の場合では、目金せずれによって、コンタク
ト孔中の第1の金属配線21が露出する様な事が生じた
場合、第2の金属膜!24のエツチング時に、第1の金
属膜[21も同時にエツチングされてしまうため、第2
の金属配線24の線幅も、コンタクト部に於いて、目金
せずれを考慮した分だけ、広くする必要がある。
In addition, in the case of the second metal film @24, which is wired so as to cover the contact hole 24, the first metal wire 21 in the contact hole may be exposed due to misalignment of the metal fitting. If the second metal film! When etching 24, the first metal film [21 is also etched at the same time, so the second metal film [21] is etched at the same time.
The line width of the metal wiring 24 also needs to be widened in consideration of the misalignment of the metal wire in the contact portion.

この友め、第1.第2の金属膜M21.24の配線ピン
チが短縮されず、半導体集積回路装置の面積を増大せし
めていた。特に、ゲートアレー、マイクロコンビエータ
などの集積回路に於いては、配線領域の面積がチップ面
積の増大を招いてい比。
My friend, number one. The wiring pinch of the second metal film M21.24 was not shortened, increasing the area of the semiconductor integrated circuit device. In particular, in integrated circuits such as gate arrays and micro combinators, the wiring area increases the chip area.

ま九、従来の方法では、コンタクト孔の段部に於ける第
2の金属配線のカバレッヂが悪く、断線。
(9) In the conventional method, the coverage of the second metal wiring at the step of the contact hole is poor, resulting in disconnection.

又はエレクトロマイグレーションの発生するおそnが6
つ九。
Or the probability of electromigration occurring is 6
Nineteen.

本発明の目的に、前記欠点を解決し、配線ビー・チが短
縮さn1断線やエレクトロマイグレーション等の発生す
る心配のない工うにし九半導体装置の製造方法を提供す
ることにある。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for manufacturing a semiconductor device that solves the above-mentioned drawbacks and eliminates the risk of shortening of the wiring beach and the occurrence of N1 disconnection, electromigration, and the like.

〔問題漬を解決するための手段〕[Means for solving problems]

本発明の構成は、パターン形成された第1の金属配線上
に第1の層間P3縁膵1−、第1の金属配線とほぼ同−
伊厚底長させる工程と、第1の金猫配線上の所定の位置
に、第1の金MA配線の癲暢エクも大なる長辺を有する
コンタクト孔を異方性エツチングに依t)rM孔すると
同時に、第1の金属配線の側面部の縞1の層間絶縁膜に
所定の深さの舅を形成する工程と減圧CVD法にエフ、
高融点金属膜を半導体基板上に厚く成長する工程と、第
1の金属膜と高融点金属膜との大なる遇択比1&:有す
るエツチングガスを用いた異方性エツチングに依り、高
融点金S膜を全面エツチングすることに依り。
The structure of the present invention is such that a first interlayer P3 edge plate 1- is formed on the patterned first metal wiring, and the first metal wiring is substantially the same as the first metal wiring.
t) rM hole by anisotropic etching process to lengthen the thick bottom and to form a contact hole having a large long side at a predetermined position on the first gold MA wiring. At the same time, a step of forming a predetermined depth in the interlayer insulating film of stripe 1 on the side surface of the first metal wiring and a low pressure CVD method are performed.
The process of growing a high melting point metal film thickly on a semiconductor substrate and anisotropic etching using an etching gas having a large selection ratio of the first metal film and the high melting point metal film of 1 &: By etching the entire surface of the S film.

前記コンタクト孔中の第1の金属配線側面部に形成され
t溝中に高融点金属膜を埋込むと同時に、コンタクト孔
中の第1の金属配線の配線方向に垂直なコンタクト孔壁
の側面に高融点金属膜管傾斜を有して残し、他の平担部
で汀、高融点金属をすべてエツチングする工程と、第2
の金属膜を半導体基板上に放炎させる工程と、第2の金
属配線を前記コンタクト孔上をコンタクト孔の短辺と同
一寸法以上のN5ll@lで通道する様に高融点金ms
と。
At the same time, a high melting point metal film is buried in the T-groove formed on the side surface of the first metal wiring in the contact hole, and at the same time, a high melting point metal film is filled in the side surface of the contact hole wall perpendicular to the wiring direction of the first metal wiring in the contact hole. A step of leaving the high melting point metal film tube with a slope and etching all the slag and high melting point metal in the other flat part;
A process of irradiating a metal film on the semiconductor substrate, and a high melting point gold ms so that the second metal wiring is passed over the contact hole with N5ll@l having the same size or more as the short side of the contact hole.
and.

第2の金属膜との大なる選択比金有するエツチングガス
を用いた異方性エツチングにより形成する工程とを含む
ことを特徴とする。
The second metal film is characterized in that it includes a step of forming by anisotropic etching using an etching gas having a large selectivity with respect to the second metal film.

〔実施例〕〔Example〕

次に本発明について図面を参照して詳細に説明する。 Next, the present invention will be explained in detail with reference to the drawings.

第1図((転)乃至第1寵ωぼ本発明の一実施例の半導
体装置の製造方法を示す平面図、断面図である。
FIG. 1 is a plan view and a sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

第1図((転)は本実施例で製造し几配線接続部の平面
図、第1図へ)乃至(社)に本実施例の製造方法を工程
順に示した断面図である。第1図(b) 、 (c)に
示す様に、半導体基板上に@1の金属配線11.例えば
アルミニウム配線(膜厚的5000A″)を形成し。
FIG. 1 is a plan view of the interconnection connection portion manufactured in this embodiment, and FIG. 1 is a cross-sectional view showing the manufacturing method of this embodiment in the order of steps. As shown in FIGS. 1(b) and 1(c), metal wiring 11.@1 is placed on the semiconductor substrate. For example, aluminum wiring (film thickness: 5000 A'') is formed.

その上部に第1の1聞納縁$12.例えばバイアス・ス
パッタ酸化膜を第1の金属配線11とほぼ同一の膜厚(
約500OA ) t−区長させる0次に。
At the top of it is the first 1-monno-rim $12. For example, the bias sputter oxide film is formed to have approximately the same thickness as the first metal wiring 11 (
Approximately 500 OA) t-length zero order.

フォトレジスト13を塗布し、所定の位置にコンタクト
孔を開孔するための7オトレジスト13のパターニング
を行なう。このQ1コンタクト孔の長辺方向の大きさは
、第1の金属配#11ニジ0.2吊)μ−大きく形成す
る。
A photoresist 13 is applied, and the photoresist 13 is patterned to form contact holes at predetermined positions. The size of this Q1 contact hole in the long side direction is set to be larger than the first metal interconnect #11 by 0.2μ.

次に第1図(d) 、 (e)に示す様に、異方性エツ
チングにより、第1の眉間絶縁膜lit所定の深さ約4
00OAまでエツチングし、第1の金属配線11上部t
−g出させると同時に、第1の金属配−11の側面部に
溝を形成する。第1の眉間絶縁v!12の溝の深さに、
第1の金属配線11の厚さより浅く形成する。
Next, as shown in FIGS. 1(d) and 1(e), the first glabella insulating film lit is etched to a predetermined depth of approximately 4 mm by anisotropic etching.
The upper part of the first metal wiring 11 is etched to 00OA.
At the same time that -g is allowed to come out, a groove is formed in the side surface of the first metal interconnection 11. First eyebrow insulation v! The depth of 12 grooves,
It is formed to be shallower than the thickness of the first metal wiring 11.

さらに第1図(f)1.(g)K、示す様に、減圧CV
D法により、高融点金属膜14例えばタングステンを厚
<、  (Itの深さの約3倍程度)区長させる。この
時、第2の金属配置fi15の配線方向(A −A’断
面)に於いては溝の幅が狭いtめ、高融点金属膜上部で
は、少しのくびれを残すだけでほぼ平担となる。
Furthermore, FIG. 1(f) 1. (g) K, as shown, reduced pressure CV
By method D, the high melting point metal film 14, for example, tungsten, is made to have a thickness less than (approximately three times the depth of It). At this time, in the wiring direction (A-A' cross section) of the second metal arrangement fi15, the width of the groove is narrow t, so the upper part of the high melting point metal film is almost flat with only a slight constriction remaining. .

一方、B−B’の断面に於いてa、コンタクト孔が溝に
比べ大きいため、コンタクト孔の段差を反影し次形状と
なる。
On the other hand, in the cross section BB', since the contact hole is larger than the groove, the step of the contact hole is reflected, resulting in the following shape.

第1図(h) 、 (i)に示す様に、高融点金属膜1
4t−1第1の金属11411と高融点金属膜14との
間で大きな選択比CFJ 系のエツチングガスを使用l
、、異方性エツチングに依り、全面エッチを行ない、第
1の金属配線11の側面の溝中に、高融点金属14を埋
込むと同時に、第1の金属配線11の配線方向(B−8
’断面)に於いては、コンタクト段部に高融点金M14
のサイドウオール(Side−Wall)を傾斜をもっ
て形成する。この時、第1の金属配線11がアルミニウ
ムの場合、高融点金属14のエツチング時に露出しても
、第1の金属配線llはエツチングさnない。
As shown in FIG. 1(h) and (i), the high melting point metal film 1
4t-1 Using a CFJ-based etching gas with a large selectivity between the first metal 11411 and the high melting point metal film 14.
,, The entire surface is etched by anisotropic etching, and the refractory metal 14 is buried in the groove on the side surface of the first metal wiring 11. At the same time, the wiring direction (B-8) of the first metal wiring 11 is etched.
'Cross section), high melting point gold M14 is used at the contact step.
A side wall is formed with an inclination. At this time, if the first metal wiring 11 is made of aluminum, even if the high melting point metal 14 is exposed during etching, the first metal wiring 11 will not be etched.

第1図(j) 、 (k)に示す様に、第2の金属配線
15例えばアルミニウム(膜厚的800OA )’i全
全面底長させ、次に第2の金属配線15上の7オトレジ
ストヲ所定のパターンにパターニングシを後、高融点金
属膜14と第2の金属膜15との間で大きな選択比t−
有するCt系のエツチングガスを使用しt異方性エツチ
ングに依り、パターニングを行なう。
As shown in FIGS. 1(j) and 1(k), the second metal wiring 15, for example, aluminum (800 OA in film thickness), is made to have a bottom length over the entire surface, and then a predetermined photoresist is placed on the second metal wiring 15. After patterning into a pattern, a large selection ratio t-
Patterning is performed by t-anisotropic etching using a Ct-based etching gas.

この時、コンタクト孔上を通過する第2の金属線15の
lIJ幅がコンタクト孔の短辺の寸法と同一の線毛であ
って、かつ多少の目金ずれが生じt場合に於いても、コ
ンタクト段に傾斜をもって形成され比高融点金属ps1
4が存在するため、第1の金属配allが露出すること
がない、また、露出した高融点金属%i14はCt系の
エツチングガスでは、エツチングさルない、第1図(a
)がこのように製造さn九最終工1の平面図である。
At this time, even if the lIJ width of the second metal wire 15 passing over the contact hole is the same as the short side dimension of the contact hole, and some misalignment occurs, The contact stage is formed with a slope and a relatively high melting point metal ps1
4, the first metal arrangement %i14 is not exposed, and the exposed high melting point metal %i14 is not etched with Ct-based etching gas.
) is a plan view of the final construction 1 manufactured in this manner.

〔発明の効果〕〔Effect of the invention〕

以上説明し九様に、本発明に、第1の金属配線の配線方
向のコンタクト孔壁に高融点金属膜が傾斜をもって形成
されているtめ、第2の金属配線形成時に、多少の目金
せずれが生じた場合でも、高融点金属膜が露出するだけ
で、コンタクト孔中の第1の金属配線が露出せず、その
ため第2の配線層の喝をコンタクト孔よりも広くする必
要がなく、コンタクト領域に於いても通常配線部と同様
の配線幅、配線ピッチで配線することができ、さらVc
第1の金属配線に於いてもコンタクト孔形成部に於いて
、コンタクト孔エクも線幅を広げる必要がないtめ1通
常配線部と同様の配線幅、配線ピッチで配線することが
できる効果がある。
As explained above, in the present invention, since the high melting point metal film is formed with an inclination on the wall of the contact hole in the wiring direction of the first metal wiring, some amount of metallization is required when forming the second metal wiring. Even if misalignment occurs, only the high melting point metal film is exposed, and the first metal wiring in the contact hole is not exposed, so there is no need to make the width of the second wiring layer wider than the contact hole. , the contact area can also be wired with the same wiring width and wiring pitch as the normal wiring part, and furthermore, Vc
In the first metal wiring, there is no need to widen the line width of the contact hole in the contact hole forming part.1) There is an effect that wiring can be done with the same wiring width and wiring pitch as in the normal wiring part. be.

まt1本発明は、第2の金属配線の配線の配線方向に於
いて、第1の金属配線とその両側の溝に埋込まれた高融
点金属膜とfa2の金属配線が接続するため、接続面積
が大きく、配線間接続の抵抗値を小さくすることができ
、接続部の段差は、溝中に埋込まれt高融点金属膜とコ
ンタクト孔壁に傾斜をもって形成されt高融点金属膜の
几め、低減さnており、第2の金属配線のコンタクト部
に於けるカパレッヂは良好であり、段切れやエレクトロ
マイグレーシlン等の心配がなく、高信頼度の配線間接
続が可能になるなどの効果がある。
Also, in the present invention, in the wiring direction of the second metal wiring, the first metal wiring and the high melting point metal film embedded in the grooves on both sides of the first metal wiring are connected to the fa2 metal wiring. The area is large, and the resistance value of the interconnection connection can be made small. Since the contact area of the second metal wiring has good coverage, there is no need to worry about breakage or electromigration, and highly reliable connections between wirings are possible. There is an effect.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(aJに本発明の実施例の半導体装置の製造方法
によって製造され次子面図、第1図(b)、第1図(山
、第1図(f)、第1図(に、第1図(j)はいずれも
第1図ら)のA−A’線にそった位置で切断して見て、
本発明の実施例の製造方法を工程順に示し九断面図、第
1図(c)、第1図(e)、第1図□□□)、第1図(
i)、第1図(転)はそれぞれ第1図(b)、第1図(
d)%第1図(f)、第1図面、第1図Q)と同一工程
であって。 いずれも@1図6》のB−B’線にそつ次位置で切断し
て見た断面図、第2図(mlは従来の製造方法で製造さ
′n几亀子図、第2図(旬、第2図(d)、第2図(f
)は従来の製造方法を工程順に示し、いずれも第1図(
a)のA−A’線に七っ次位置から見た断面図、第2図
(c)、第2図(e]、第2図−)はそnぞn第2図(
b)、第2図(d)、第2図(f)と同一工程中の半導
体基板を示し、いずれも第21図(mlのB−B’線に
そつ次位置で切断して見た平面図である。 11.21・旧軸第1の金属配線、12,22・・・・
・・第1の層間絶縁膜、13.23・・・・・・フォト
レジスト、14・・・・・・高融点金属膜、15.24
・・・・・−第2の金践配線、25・・・・・・コンタ
クト孔。 □ヘ ニ       痴
FIG. 1 (aJ) shows a cross-sectional view of a semiconductor device manufactured by the method of manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 1 (b), FIG. , Fig. 1(j) are both cut along the line A-A' in Fig. 1 et al.
The manufacturing method of the embodiment of the present invention is shown in the order of steps, including nine cross-sectional views, FIG. 1(c), FIG. 1(e), FIG.
i) and Figure 1 (translation) are respectively Figure 1 (b) and Figure 1 (
d) % Same process as Figure 1 (f), Figure 1, Figure 1 Q). Both are cross-sectional views taken along the line B-B' of Figure 6, Figure 2 (ml is manufactured using the conventional manufacturing method), Figure 2 (ml) , Figure 2(d), Figure 2(f)
) shows the conventional manufacturing method in the order of steps, and both are shown in Figure 1 (
The sectional view taken from the 7th position along line A-A' in a), Figure 2(c), Figure 2(e), Figure 2-) are similar to Figure 2(a).
b), Fig. 2(d), and Fig. 2(f) show the semiconductor substrate in the same process, all of which are plane views taken along the line BB' of Fig. 21 (ml). This is a diagram. 11.21 Old shaft first metal wiring, 12, 22...
...First interlayer insulating film, 13.23...Photoresist, 14...High melting point metal film, 15.24
...-Second metal wiring, 25...Contact hole. □heni slut

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上に第1の金属配線を形成する工程と、この
主表面に第1の層間絶縁膜を前記第1の金属配線とほぼ
同一膜厚で成長させる工程と、前記第1の金属配線上の
所定の位置に、前記第1の金属配線の線幅より大なる長
辺を有するコンタクト孔を、異方性エッチングに依り開
孔し、前記第1の金属配線の側面部の前記第1の層間絶
縁膜に所定の深さの溝を形成する工程と、減圧CVD法
により高融点金属膜を前記半導体基板上に厚く成長する
工程と、前記第1の金属膜と高融点金属膜との大なる選
択比を有するエッチングガスを用いた異方性エッチング
に依り、前記高融点金属膜を全面エッチングすることに
依り前記コンタクト孔中の第1の金属配線側面部に形成
された溝中に前記高融点金属膜を埋込むと同時に、コン
タクト孔中の前記第1の金属配線の配線方向に垂直なコ
ンタクト孔壁の側面に、前記高融点金属膜を傾斜を有し
て残し、他の平担部では前記高融点金属をすべてエッチ
ングする工程と、第2の金属膜を前記半導体基板上に成
長させる工程と、前記第2の金属配線を前記コンタクト
孔上をコンタクト孔の短辺と同一寸法以上の線幅で通過
する様に、前記高融点金属膜と前記第2の金属膜との大
なる選択比を有するエッチングガスを用いた異方性エッ
チングにより形成する工程とを含むことを特徴とする半
導体装置の製造方法。
forming a first metal wiring on a semiconductor substrate; growing a first interlayer insulating film on the main surface of the first metal wiring to have a thickness substantially the same as that of the first metal wiring; and over the first metal wiring. A contact hole having a longer side larger than the line width of the first metal wiring is opened at a predetermined position of the first metal wiring by anisotropic etching. a step of forming a groove of a predetermined depth in an interlayer insulating film, a step of growing a high melting point metal film thickly on the semiconductor substrate by low pressure CVD, and a step of growing a high melting point metal film thickly on the semiconductor substrate; By etching the entire surface of the refractory metal film by anisotropic etching using an etching gas having a selectivity of At the same time as embedding the melting point metal film, the high melting point metal film is left with a slope on the side surface of the wall of the contact hole perpendicular to the wiring direction of the first metal wiring in the contact hole, and another flat part is buried. Then, a step of etching all the high-melting point metal, a step of growing a second metal film on the semiconductor substrate, and a step of growing the second metal film on the contact hole with a size equal to or larger than the short side of the contact hole. A semiconductor characterized by comprising a step of forming by anisotropic etching using an etching gas having a large selectivity between the high melting point metal film and the second metal film so as to pass through the semiconductor with a line width. Method of manufacturing the device.
JP12521687A 1987-05-21 1987-05-21 Manufacture of semiconductor device Pending JPS63289841A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12521687A JPS63289841A (en) 1987-05-21 1987-05-21 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12521687A JPS63289841A (en) 1987-05-21 1987-05-21 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS63289841A true JPS63289841A (en) 1988-11-28

Family

ID=14904741

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12521687A Pending JPS63289841A (en) 1987-05-21 1987-05-21 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS63289841A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0788160A3 (en) * 1996-02-05 1999-06-16 Matsushita Electronics Corporation Semiconductor device having a multi-layered wire structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0788160A3 (en) * 1996-02-05 1999-06-16 Matsushita Electronics Corporation Semiconductor device having a multi-layered wire structure

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