JPS63289594A - Musical sound generator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention samples a sound signal input from the outside and stores it in a memory, and then samples the waveform sample data stored in this memory in response to a key operation, etc. Regarding a sampling type musical tone generation device that generates musical tones by reading out at a desired pitch, in particular, by first reading out waveform sample data stored in a memory in a backward direction and then reading out in a forward direction, The present invention relates to a musical tone generator capable of realizing new performance effects.

[Conventional technology]

As a sampling type musical tone generator, there is one disclosed in Japanese Patent Publication No. 47435/1983, for example.

There, it is disclosed that sampled waveform data of a plurality of periods is repeatedly read out.

In that case, a start address and an end address are detected corresponding to the beginning and end of the waveform data, reading is started from the start address, and when it reaches the end address, it returns to the start address and repeats reading. . Therefore, when reproducing and producing sound signals from externally sampled sound signals, although the sampled sound signals can be repeatedly produced, they can only be produced regularly according to the time order in which they were sampled.

[Problem that the invention seeks to solve]

As mentioned above, in conventional sampling-type musical tone generators, it is possible to read the waveform data stored in the memory in the forward direction once or repeatedly in the forward direction many times. It was not possible to produce musical tones based on sampled sounds in variations.

The present invention has been made in view of the above-mentioned points, and is achieved by performing at least one sequence of first reading the waveform sample data stored in the memory once in the reverse direction and then reading it once in the forward direction. It is an object of the present invention to provide a musical tone generating device that realizes new performance effects.

[Means for solving problems]

A musical sound generation device according to the present invention includes an external sound sampling means for sampling a sound signal inputted from the outside, a readable and writable storage means for storing waveform sample data, and a sound signal sampled by the external sound sampling means. a write control means for writing waveform sample data into the storage means; and when a musical tone is to be generated, the waveform sample data of the storage means is first read out in a direction opposite to the address order at the time of writing, and then the storage means readout control means for performing at least one sequence of reading out the waveform sample data in the forward direction in the address order at the time of writing, the musical tone signal corresponding to the waveform sample data read from the storage means; It is designed to occur.

This is illustrated in FIG. 1, where 1 is an external sound sampling means, 2 is a storage means, 3 is a write control means, and 4 is a read control means.

[Effect]

The sound signal input from the outside is sent to external sound sampling means 1.
The waveform sample data of the sampled sound signal is written into the storage means 2 under the control of the write control means 3. In the read control means 4,
When a musical tone is to be generated, the waveform sample data of the storage means 2 is first read out in the reverse direction of the address order at the time of writing, and then the waveform sample data of the storage means 2 is read out in the forward direction of the address order at the time of writing. A musical tone signal corresponding to the waveform sample data read out from the storage means 2 is generated by performing a sequence consisting of reading out at least once.

As a result, a musical tone obtained by rearranging sampled external sounds in the backward direction in time is played once, and then the sampled sound is rearranged in the forward direction in time and played again. Performance effects can be achieved.

In the embodiment, it is possible to select whether the sequence consisting of backward reading and forward reading is performed only once or repeatedly. Performing this sequence only once is hereinafter referred to as "U-turn/reverse." In addition, repeating the sequence multiple times is hereinafter referred to as "
It's called a U-turn reverse loop. According to the "U-turn reverse loop", the above-mentioned "U-turn reverse" can be repeated many times to realize a new performance effect.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 shows the hardware configuration of an embodiment of an electronic musical instrument to which the musical tone generator according to the present invention is applied.
Various operations and processes are controlled by a microcomputer section including a program ROM (read only memory) 12 and a data and working RAM (random access memory) 13. The keyboard 14 includes a plurality of keys for specifying pitches of musical tones.

The operation panel unit 15 includes a sampling control operator group 16 for controlling the external sound sampling operation and its readout operation, an envelope control operator group 17 for setting and controlling the envelope waveform of musical tones, and various types of controls. an effect control operator group 18 for setting and controlling musical tone effects;
A group of operators 19 for setting and controlling various musical tones are also provided.

In the sampling control operator group 16, the sampling switch SMPL and the override switch 0VRWR
is a switch that instructs to write the external sound waveform sample data into the data memory 21 in the tone generator section 20. reverse switch rvr
5 and U-turn switch UTRN and loop switch LOO
P and the echo switch ECHO are switches for instructing the performance mode when reading the waveform sample data stored in the memory 21 and performing the performance.

The sampling switch SMPL is operated to instruct that external sound sampling should be performed.

The override switch 0VRWR is operated to instruct that external sound sampling should be performed in the same way as described above, but it is used to override external sound waveform sample data that has already been stored in the memory 21. This operation is used to instruct to overwrite waveform sample data of another external sound without erasing it (this is called r override). On the other hand, when sampling is instructed by the sampling switch SMPL, the previously stored external sound waveform sample data is erased.

The reverse switch RVR3 is operated to instruct a performance to be performed by reading out the external sound waveform sample data stored in the memory 21 in the reverse direction. This kind of reading is simply called "reverse". In addition, the memory 21
Reading in the reverse direction means reading in order from the address with the largest value. On the other hand, reading the memory 21 in the forward direction means reading data in order from the address with the smallest value.

The U-turn switch UTRN is operated to instruct a performance in which the external sound waveform sample data stored in the memory 21 is read out in the forward direction and then turned back and read out in the reverse direction. This type of readout is simply called a "U-turn".
That's what it means.

In addition, it is possible to select and instruct "U-turn" and "reverse" at the same time. In that case, after reading out the external sound waveform sample data stored in the memory 21 in the reverse direction, the data is turned back in the forward direction. read out. This is called a "U-turn reverse."

The loop switch LOOP is operated to instruct repeated reading of external sound waveform sample data stored in the memory 21. This kind of reading is simply called a "loop." A normal "loop" is memory 2
The external sound waveform sample data stored in step 1 is repeatedly read out in the forward direction.

This is called a "normal loop."

It is possible to select and instruct "loop" and "reverse" at the same time, and in that case, the external sound waveform sample data stored in the memory 21 is repeatedly read out in the reverse direction. This is called a "reverse loop."

It is possible to select and instruct "loop" and "U-turn" at the same time. In that case, after reading out the waveform sample data of the external sound stored in the memory 21 in the forward direction, it is read out in the reverse direction. repeat. This is called “
It's called a U-turn loop.

It is possible to select and instruct "loop", "U-turn" and "reverse" at the same time, in which case the memory 21
After reading out the waveform sample data of the external sound stored in the memory in the backward direction, the process repeats the process of reading it back in the forward direction.

This is called a "U-turn reverse loop."

A list of performance modes as described above is shown in FIG. There are eight performance modes, and each mode is distinguished by symbols M1 to M8. The left column shows the mode name, which corresponds to the names mentioned above. Therefore, the conditions under which each mode is selected will be clear from the above description. In addition, "Normal" mode M
1 is a mode in which the external sound waveform sample data stored in the memory 21 is read out only once in the forward direction, and this "normal" mode is selected when no special modes M2 to M8 are selected.
mode. The right column schematically shows the readout condition of the waveform sample data from the memory 21 in each mode, and the direction of the arrow indicates whether the readout is forward or backward. Mode M3 related to “loop”. M
5. M6. At M8, reading as shown is repeated. The starting point in forward reading is a predetermined start address, and the ending point is a predetermined end address. vice versa.

The starting point in backward reading is the end address, and the ending point is the start address.

The start address and end address serve as reference addresses that indicate the starting point or ending point in forward or backward reading. In this embodiment, one reference address, or start address, is always fixed at a predetermined initial address (for example, address 0), and the other reference address, or end address, corresponds to the final zero-crossing address of the sampled waveform data. It is designed to change as appropriate. Further, the value of this reference address, that is, the end address, can be increased or decreased as appropriate by the performer. In this embodiment, the value of the end address is increased or decreased in mode M3. M5. This is possible when M6° to M8.

In the sampling control operator group 16, an increase switch I is used to instruct increase/decrease change of the above-mentioned end address.
NC and a reduction switch DEC are provided. The address value increases according to the operation of the increase switch INC, and the address value decreases according to the operation of the decrease switch DEC. In this embodiment, - As an example, the increase or decrease of the end address by the increment switch INC and the decrement switch DEC is 1
This is done not in units of addresses, but in units of blocks consisting of multiple addresses.

Here, the data memory 2 in the tone generator section 20
An example of the address structure in No. 1 will be explained with reference to FIG. The entire range of addresses for storing waveform sample data of external sound for one tone consists of 16 blocks from 0 to 15, and one block consists of 256 addresses. The first address of this entire address range is the start address, and has an address value of O. The end address changes as appropriate in response to the final zero-crossing address of the sampled waveform data. In this embodiment, this end address is also determined on a block-by-block basis. The value of this end address is increased or decreased according to the operation of the increase switch INC and decrease switch DEC.

An echo switch ECHO provided in the sampling control operator group 16 is for selecting an echo effect. The echo effect referred to here is when the performance mode is set to
Loop” and automatically lengthen the release time of the volume envelope of the generated musical note (for example, to the longest)
By this, sampled waveform data is repeatedly read out from a memory 21, and the musical tone is repeatedly sounded while gently attenuating the volume envelope of the musical tone signal corresponding to the read waveform data.

The all-cancel switch CANSEL provided in the sampling control operator group 16 cancels all or predetermined various data set, selected, changed, or adjusted on the operation panel section 15 in relation to the sampled waveform sample data. However, the contents of these data are manipulated to return them to the state they were in when they were first sampled.

In other words, it is for canceling the edited contents of various data edited in relation to the sampled waveform sample data and returning to the initial state before editing. By being able to cancel the edited content and return to the initial state before editing, it becomes possible to freely edit without fear of failure, and editing functions related to sampled waveform sample data are now available. can be improved.

Envelope control operator group 1 in operation panel section 15
Reference numeral 7 includes operators for setting and controlling the characteristics of the volume envelope waveform to be applied to the waveform sample data read from the data memory 21, such as A, D, S, R, attack time, decay time, which determines the characteristics, It consists of operators that set and control the sustain level and release time, respectively.

The effect control operator group 18 on the operation panel section 15 includes operators for setting and controlling musical sound effects such as vibrato, tremolo, and reverb, for example.

The tone generator unit 20 has a function of sampling a sound signal input from the outside through a microphone 22 and converting it into digital waveform sample data, a function of writing the sampled digital waveform sample data into the data memory 21, and! It has a function of reading waveform sample data from the data memory 21 in response to key presses on the I board 14, and a function of controlling the volume envelope of the read waveform sample data and adding various musical sound effects. The digital musical tone signal generated from the tone generator section 20 is converted into an analog signal and then provided to the sound system 23.

The timer beep circuit 24 is a circuit for generating a beep sound for a certain period of time when sampling of external sound is started. The beep sound generation time is, for example, about 300 m5, and the sound starts in response to the operation of the sampling switch SMPL, and when it ends, the beep end pulse BPEND is generated.
occurs. Based on the beep end pulse BPEND, the tone generator section 20 starts a sampling operation.

Key scanning and sound generation assignment processing for detecting key presses and key releases in @fi14, scanning for detecting operation of switches and the like on the operation panel section 15, and lighting/extinguishing processing for indicators, etc., and processing on the tone generator section 20. Various processes such as writing and reading control of sampling data are executed by the microcomputer section.

Among the processes executed by the microcomputer unit, examples of flowcharts of processes related to the present invention are shown in FIGS. 8 to 19.

Data and working R used in connection with this process
An example of the contents stored in AM13 is shown in FIG.

SMPFLG is a sampling flag and becomes 1'' in normal sampling mode.

0VWFLG is an override sampling flag and becomes "1" in override mode.

RVFLG is a reverse flag, and becomes 1 when in the "reverse" performance mode.This flag is reversed from 1 to 0 or from 0 to 1 every time the reverse switch RVR3 is turned on. do.

UTFLG is a U-turn flag, and becomes "1" in the "U-turn" performance mode. This flag is inverted from 1 to 0 or from O to 1 every time the U-turn switch UTRN is turned on.

LPFLG is a loop flag, which becomes "1" in the "loop" performance mode. This flag changes from "1" to "0" or to "1" each time the loop switch LOOP is turned on.
10” is inverted to “1”.

ECFLG is an echo flag, and becomes "1" when an echo effect is selected. This flag changes from “1” to “0” or “0” every time the echo switch ECHO is turned on.
” to “1”.

LPFLGB is a loop flag buffer, and is used to store the contents of the immediately preceding loop flag LPFLG in order to forcibly set the contents of the loop flag LPFLG to "1" when an echo effect is selected. be. The contents stored in this buffer LPFLGB are returned to the loop flag LPFLG when the echo effect is no longer selected.

NKEY is a new key code register, which stores the key code of a newly pressed or released key.

KCODE is a key code register that stores the key code corresponding to the musical tone currently being produced.

ZCRADB is a zero-crossing address buffer,
It stores the final zero-crossing address of waveform sample data sampled externally.

LPADB is an end address buffer that stores the aforementioned end address.

ATB is attack time buffer, DTB is decay time buffer, SLB is sustain level buffer, R
TB is a release time buffer, which stores data on the attack time, decay time, sustain level, and release time set and controlled by the envelope control operator group 17, respectively.

RTBUF is the release time storage buffer, when the echo effect is selected the release time buffer RT
This is to save the immediately preceding contents of the release time buffer RTB in order to forcibly set the contents of B to the longest time. The contents saved in this buffer RTBUF are returned to the release time buffer RTB when the echo effect is no longer selected.

Areas are provided in the data and working RAM 13 for registers, flags, or buffers as described above. Also, in the data and working RAM 13, there is a group of effect control operators 18 in the operation panel section 15.
and other areas for storing operation detection data of the operator group 19, and other data and working areas.

A detailed example of the tone generator section 20 is shown in FIG.

In the tone generator section 20 of FIG. 6, an interface 26 is provided to exchange data with the microcomputer section via the data bus 25. Interface 26 includes a buffer register. The data given from the microcomputer section is sent to the tone generator section 2 via the interface 26.
0 to a predetermined circuit. Furthermore, data output from a predetermined circuit within the tone generator section 20 is given to the microcomputer section via an interface 26 and a data bus 25.

To briefly explain the main circuits in the tone generator section 20, the data memory 21 has an address structure as shown in FIG. If it is 40'', it is a read mode, and if it is 40'', it is a write mode. AD is an address input, and DT is a data input/output terminal.

The external sound signal picked up by the microphone 22 is converted into a clock pulse φ□ by the analog/digital converter 27.
sampled and digitally converted. The digitally converted waveform sample data is applied to the data input/output terminal DT of the data memory 21 via an adder 28 for overwriting, a latch circuit 29, and a gate 3o.

Further, the waveform sample data output from the analog/digital converter 27 is given to a rising edge detection circuit 31,
The rise of the sound is detected. A trigger pulse TRG is output in response to the detection of the rise of the sound. This trigger pulse TRG
is used as a signal to instruct the timing to start writing waveform sample data to the data memory 21.

Further, the waveform sample data output from the analog/digital converter 27 is provided to a zero cross detection circuit 32, and zero crosses are detected. In this embodiment, in order to simplify the configuration of the zero cross detection circuit 32, the level of the waveform sample data is determined to be within a predetermined zero judgment range (range of ±α of the zero level, where α is an appropriate level). is detected, and a zero cross detection pulse ZCR is output when the zero determination range is exceeded. The zero-crossing detection pulse ZCR is applied to the latch control of the zero-crossing address latch circuit 33, and the write address when the zero-crossing is detected is latched into the latch circuit 33. Since the zero-crossing detection pulse ZCR is generated every zero-crossing of the waveform sample data, the zero-crossing address of the latch circuit 33 is rewritten many times, and finally, the zero-crossing address of the latch circuit 33 is
The data left at 3 is the final zero-crossing address in the waveform sample data.

The note clock generation circuit 34 has a new key code NK.
Node clock pulse φ in response to C. occurs. The two-knee key code NKC is for specifying the write rate or read rate of the data memory 21, and is set to a key code of a predetermined standard pitch (for example, A4 tone) at the time of sampling, and is set to a key code of a predetermined standard pitch (for example, A4 note), and is used to specify the write rate or read rate of the data memory 21. will be changed accordingly. Node clock pulse φ. are divided by 1/2 by the frequency divider 35, and the note clock pulses φ0 . φ2 is obtained. The phase-advanced note clock pulse φ is inputted to the count clock CLK of the address counter 37 via the AND circuit 36. The slow phase note clock pulse φ2 is generated by the NAND circuit 4.
Read/write control input R/W of data memory 21 via 4
and control its read/write mode.

As described below, the sampling mode (normal sampling mode or override sampling mode)
At this time, the signal SMI or 5M2 becomes 1'', and 111 P+ is applied from the OR circuit 45 to the NAND circuit 44.

As a result, the NAND circuit 44 inverts the delayed note clock pulse φ2 and applies it to the manual read/write control R/W of the data memory 21. Therefore, the data memory 21 is in the read mode when the leading phase node clock pulse φ is "1", and in the write mode when the slow phase node clock pulse φ2 is 1", and is time-divisionally operated within the time of one address. The read/write mode is switched to "OF+", and the NAND circuit 44 is set to "OF+" in the various performance modes M1 to M8. always 11
1 JP is output, and the data memory 21 is always in write mode. Note that since the address counter 37 counts the note clock pulse φ1 whose frequency is divided by 2, the note clock generation circuit 34 generates the note clock pulse φ with twice the frequency of the target note clock pulse φ1. shall occur.

The address counter 37 generates an address signal specifying a read/write address of the data memory 21, and is a preset pulse PRP applied to the preset control input PR.
The preset data added to the preset data human power PRD is preset according to the preset data, and the note clock pulse φ□ added to the count clock human power CLK is counted using this preset value as a starting point. The address counter 37 is an up/down counter and has a direction indication signal DIR.
When is "1", it counts up, and when (l OH) it counts down.

The output of the address counter 37 is applied to the address input AD of the data memory 21 and also to the comparator 38, and the higher 4 bits are input to the zero-cross address latch circuit 33. The address signal consists of 12 bits, the upper 4 bits identify each block from 0 to 15, and the lower 8 bits identify 256 addresses within one block. By latching the upper four bits of the address signal in the zero-crossing address latch circuit 33, the zero-crossing address is detected in block units. Latch circuit 33
The zero-crossing address data ZCRAD latched in is supplied to the microcomputer section via the interface 26.

Comparator 38 is for detecting whether the address signal generated from address counter 37 has reached the end point. When the address signal is progressing in the forward direction (that is, increasing), the end address data LPAD is selected by the selector 39 and stored in the end point address register 40, and the end address data LPAD stored in this register 40 and The comparator 38 compares the address signal with the address signal, and when the two match, outputs the end pulse END (
On the other hand, when the address signal is progressing in the opposite direction (that is, decreasing), the selector 39 selects the initial address data in which all 12 bits are "0" and sets the end point address. The initial address data stored in the register 40 and the address signal are compared by the comparator 38, and when the two match, an end pulse END is output.

Selection control of the selector 39 is performed by a T-flip-flop 41
This is done in response to the direction instruction signal DIR output from the.

When this direction instruction signal DIR is "'1", that is, when it instructs a forward change of the address, the B input is selected,
60'', that is, when instructing a reverse change in address, select 6 inputs.

As will be described later, the end address data LPAD is given from the microcomputer section based on the above-mentioned zero-cross address data ZCRAD, and is 4-bit data that indicates the end address in units of blocks. This block unit end address data LP
In order to convert AD into an address unit, 8 bits of all "1°'" are added to the lower part of AD and the result is applied to the B input of the selector 39.As a result, the end address data LPAD is the last address in the block. It is assumed to indicate an address.

The output of the selector 42 is added to the preset data input PRD of the address counter 37. This selector 42 is
Contrary to the selector 39 described above, when the direction instruction signal DIR is "1", that is, when instructing a forward change of the address, the initial address data of all 12 bits "0" applied to the A input is selected. In other words, when instructing a reverse change in address, end address data LPAD to be applied to the B input is selected. This end address data LPAD also has 8 bits of all LL I in its lower order.
I+ is added to indicate the final address within the block.

Note that the end point address register 40 loads the end point address data from the selector 39 at the same time as the address counter 37 is preset by the same pulse PRP as the preset pulse PRP applied to the preset control input PR of the address counter 37.

T-flip-flop 4 for generating direction indication signal DIR
1 is sampling mode or various performance modes M
1 to M8, as will be described later.

The generation conditions of the preset pulse PRP for presetting the address counter 37 are also controlled in accordance with the sampling mode or various performance modes M1 to M8, as will be described later.

The AND circuit 36 which controls adding the note clock pulse φ□ to the count clock CLK of the address counter 37 is controlled in accordance with the output signal of the flip-flop 43. The state of this flip-flop 43 is controlled as described later in accordance with the sampling mode or various performance modes M1 to M8.

The waveform sample data read from the data memory 21 is input to a multiplier 46 and multiplied by envelope waveform data provided from an envelope generator 47. The envelope generator 47 generates an envelope waveform having a shape set based on attack time data AT, decay time data DT, sustain level data SL, and release time data RT given from the microcomputer section via the interface 26, and generates it as a key-on pulse K.
ONP, 0KONP and key-off pulse KOFP, 0K
Occurs in response to OFP. As is well known, an envelope waveform portion consisting of attack, decay, and sustain is generated in response to a key-on pulse, and a release portion is generated in response to a key-off pulse. Here, one key-on pulse KONP and key-off pulse KOFP are given based on normal key pressing operations, and the other key-on pulse 0KONP and key-off pulse 0KOF
F is given to immediately and automatically generate the musical tone that has just been sampled.

The waveform sample data whose volume envelope has been controlled by the multiplier 46 is supplied to the digital/analog converter 48, where it is converted into an analog signal, and finally supplied to the sound system 23. It is also applied to an effect circuit 49 as appropriate to provide musical sound effects such as reverb, tremolo, and vibrato.

Next, various operations of this electronic musical instrument will be explained with reference to FIGS. 8 to 19.

FIG. 8 shows the main routine. First, in the key scan process, each key on the keyboard 14 is scanned to detect key presses and key releases. A predetermined process is executed in response to this detection. Here, when a new key press is detected, the key-on event routine shown in FIG. 12 is executed, and when a new key release is detected, the key-off event routine shown in FIG. 13 is executed.

In the sampling control operator scanning process, the operation of each switch of the sampling control operator group 16 is detected, and a predetermined process is executed in response to this detection. here,
When it detects that the sampling switch SMPL has changed from off to on, the sampling event routine in Figure 9 is executed, and when it detects that the override switch 0VRWR has changed from off to on, the override event routine in Figure 10 is executed. do. Also, a beep end pulse BPE given from the timer beep circuit 24 when the beep sound at the start of sampling ends.
ND is detected, and in response to this detection, the timer beep end event routine of FIG. 11 is executed. Furthermore, when sampling of the external sound is completed, the sampling end event routine shown in FIG. 14 is executed in response to a sampling end signal SMPEND given from the tone generator section 20 as described later. Also, reverse switch RVR3, U-turn switch UTRN, loop switch LOOP, echo switch ECHO1 increase switch IN
C1 reduction switch DEC, all cancel switch C
When it is detected that ANSEL changes from off to on, the reverse event routine, U-turn event routine, loop event routine, echo event routine, increase event routine, and
A decrease event routine and an all cancel event routine are executed respectively.

In the envelope control operator scanning process, the operation of each operator of the envelope control operator group 17 is detected,
A predetermined process is executed in response to this detection. Here, the attack time, decay time, sustain level, and release time data set and controlled by the envelope control operator group 17 are stored in the attack time buffer ATB, decay time buffer DTB, and sustain level buffer SL.
B and release time buffer RTB.

In the effect control operator scanning process, the operation of each operator of the effect control operator group 18 is detected, and a predetermined process is executed in response to this detection. In the other operator scanning process, the operation of each operator of the other operator group 19 is detected, and a predetermined process is executed in response to this detection.

Normal Sampling Operation When performing a normal sampling operation, the sampling switch SMPL is first turned on. In response to this, the sampling event routine of FIG. 9 starts. Here, the sampling flag SMPFLG is set to "1",
Other flags 0VWFLG-ECFLG are reset to "0" (step 101). Next, new key code N
A key code of a predetermined reference pitch (for example, A4 pitch) is sent to the tone generator section 20 as KC (step 1).
02). Then, a start trigger signal is sent to the timer beep circuit 24 to generate a beep sound (step 10).
3). In addition, in the flowchart, the tone generator section 20 is indicated by TG.

The timer beep circuit 24 emits a beep sound for a predetermined period of time (for example, 300 m5) in response to this start trigger signal, and when this time elapses, a beep end pulse BPEN is emitted.
Output D.

Referring to FIG. 6, the tone generator unit 20' generates a node clock pulse φ of the reference pitch (A4 tone) from the note clock generation circuit 34 in response to the given new key code NKC. occurs. This note clock pulse is now stably generated during the beep sound generation time, and preparation for sampling is completed. in this way,
The beep serves to signal completion of 4gB sampling.

The routine of FIG. 11 starts in response to the beep end pulse E3PEND. In step 104, it is confirmed that the sampling flag SMPFLG is 1'', and
Go to step 105. Here, the sampling mode signal SMI corresponding to the normal sampling mode is set to 11.
1 II and set the sampling mode signal SM2 corresponding to the override sampling mode to LI OII.
and sends it to the tone generator section 20.

In the next step 106, data to be given to the tone generator section 2o is initialized as follows and sent to the tone generator section 20. The various mode signals M1 to M8 of the performance mode are set to 110 J+. The end address data LPAD is set to the value "15" indicating the final block. Attack time data AT, decay time data DT, and release time data RT are each set to rOJ, and sustain level data SL is set to maximum value rMAXJ. This sets a direct keying type envelope waveform that maintains a constant envelope level from key-on to key-off. With this direct keying type envelope waveform, musical tones are produced at the same volume level as sampled.

In the next step 107, the contents of the attack time buffer ATB, decay time buffer DTB, sustain level buffer SLB, and release time buffer RTB in the microcomputer section are also initialized to those for setting a direct keying type envelope waveform in the same way as above. . In the next step 108, data for various musical tone effects are also initialized to predetermined contents.

Meanwhile, the performer picks up a desired external sound using the micro-on 22 while checking the beep sound. Referring to FIG. 6, as mentioned above, the picked up signal is sampled by the analog/digital converter 27,
converted to digital. A rising edge of the sound of the digitally converted waveform sample data is detected by a rising edge detection circuit 31, and a trigger pulse TRG is output in response to the detection of the rising edge of the sound. This trigger pulse TRG is input to the AND circuit 5o. "'1" of the sampling mode signal SMI is applied to the other input of the AND circuit 5o via the OR circuit 51, and the output of the AND circuit 50 becomes "1" in synchronization with the trigger pulses T and RG. , which is applied as a sampling start pulse SMPST to the set input S of the flip-flop 43 via the OR circuit 52, and is applied to the preset control input PR of the address counter 37 via the OR circuit 53 as a preset pulse PRP, and is also applied to the end point address. applied to register 40. Further, the sampling start pulse SMPST is inputted to the AND circuit 56 via the OR circuit 54, and the sampling mode signal SMI is inputted to the AND circuit 56 via the OR circuit 55.
The output 111 II of the AND circuit 56 is applied to the set input S of the T-flip-flop 41.

As a result, the direction indicating signal DIR output from the T-flip-flop 41 becomes l (171), and the selector 42
The selector 39 selects the initial address (all 110 II) and presets it in the address counter 37. The selector 39 selects the end address LPAD indicating the final block and loads it into the end point address register 40, and the address counter 37 is set to count up. Ru. Then, by the set output "1" of the flip-flop 43, the AND circuit 3
6 is enabled, and a note clock pulse φ, at a rate corresponding to the A4 tone, is input to the address counter 37.

In this way, in response to the generation of the trigger pulse TRG, the address counter 37 starts counting up the note clock pulse φ at a rate corresponding to the A4 tone, and the generated address signal is set to the initial address (all "0"). It changes in the forward direction with the start point as the end point and the end address LPAD as the end point.

On the other hand, when the sampling mode signal SMI becomes "1", a signal obtained by inverting the note clock pulse φ2 is applied from the NAND circuit 44 to the read/write control manual R/W of the data memory 21, and the data memory 21 , when the leading phase note clock pulse φ□ is “1”, it is the read mode, and when the slow phase note clock pulse φ2 is “1”, it is the write mode, and the read/write mode is switched in a time-division manner within the time of one address. . However, when the sampling mode signal SMI is "1", the sampling mode signal SM2 is "0", the gate 57 for adding the read signal of the data memory 21 to the adder 28 is closed, and the envelope A key-on pulse for generating envelope waveform data from the generator 47 is also not generated (therefore, the multiplier 46 is not connected to the data memory 2).
1 readout signal is cut), the readout has no meaning.

Digital waveform sample data of the external sound output from the analog/digital converter 27 is applied to one input of the adder 28 . The output of the gate 57 is given to the other input of the adder 28, which is '0' as described above.
'', the digital waveform sample data of the external sound simply passes through the adder 28 and is applied to the latch circuit 29. The latch circuit 29 performs a latch operation at the timing of the note clock pulse φ2, which is the write timing.

Note that the analog/digital conversion operation in the analog/digital converter 27 is performed at the timing of the advanced note clock pulse φ1.

The output of latch circuit 29 passes through gate 30 and enters data input DT of data memory 21. The gate 30 is controlled by the output of an OR circuit 58 which receives the sampling mode signal SMI and 8M2, and the output of an AND circuit 59 which receives the note clock pulse φ2. As a result, the gate 30 is opened only in the sampling mode (normal sampling mode and override sampling mode) and only when the note clock pulse φ2 is "1", that is, only at the write timing. In addition, in various performance modes M1 to M8, the signals SMI and 3M2 are "Ol+", and the AND circuit 59
always outputs "O" and the gate 30 is always closed, so even if noise is picked up by the microphone 22, it can be cut here.

In this way, the digital waveform sample data of the external sound is
At the write timing, the data is input to the data input DT of the data memory 21 and written to the address specified by the address signal given from the address counter 37.

On the other hand, the waveform sample data output from the analog/digital converter 27 is given to the zero cross detection circuit 32, and as described above, zero crosses are detected in parallel with the write operation. In response to the zero-crossing detection pulse ZCH output from the zero-crossing detection circuit 32, the write address when the zero-crossing is detected is latched in the zero-crossing address latch circuit 33. Zero cross detection pulse Z
Since the CR is generated for each zero cross of the waveform sample data, the zero cross address of the latch circuit 33 is rewritten many times, and the data finally left in the latch circuit 33 is the final zero cross address of the waveform sample data. Therefore, when the sampling is finished,
The final zero-crossing address is already known.

When the write address reaches the final address of the memory 21, the end address LPAD indicating the final address of the final block stored in the end point address register 40 is
The comparator 38 outputs an end pulse END. This end pulse END is input to the AND circuit 60. Since this AND circuit 60 is enabled by 1'' of the sampling mode signal SMI from the OR circuit 61, 111 II corresponding to the end pulse END
is from the AND circuit 60 to the OR circuit 62. It is input to the reset manual power R of the flip-flop 43 via the delay flip-flop 63. The delay flip-flop 63 delays the note clock pulse φ by one clock. As a result, one clock after the count value reaches the final address, the flip-flop 43 is reset, the AND circuit 36 is closed, and the note clock pulse φ is stopped.

In this way, the address counter 37 stops counting. Incidentally, since no preset operation is performed at this time, the count value is held at the final value.

In this way, in the sampling mode, data memory 2
Writing is performed over the entire address range from the initial address of 1 to the final address.

End pulse END is applied to AND circuit 64. Since this AND circuit 64 is enabled by "1" of the sampling mode signal SMI from the OR circuit 65, II II II corresponding to the end pulse END is output from the AND circuit 64, and this is used as the sampling end signal SMPEND. Sent to the microcomputer section. Further, the zero-cross address data ZCRAD latched in the zero-cross address latch circuit 33 is also sent to the microcomputer section.

If you want to write waveform sample data of a newly sampled sound superimposed on the sampled sound at the override sampling destination, turn on the override switch 0VRWR. In response, the override event routine of FIG. 10 is executed. Here, first, override flag 0VWFLG
is set to 1'' and other flags are reset to 11011 (step 101a), followed by step 102.
a.

The process at step 103a is the same as steps 102 and 103 in FIG. 9, and an A4 key code is set as the new key code NKC, and a timer beep sound is generated.

When the beep ends, the timer beep end event routine of FIG. 11 is executed as described above. here,
In step 104, the sampling plug SMPFLG
is 0'', the determination is NO and the process goes to step 109. In step 109, the sampling mode signal SMI
is set to 0", 3M2 is set to 111 It, and sent to the tone generator section 20. Thereafter, in the same way as in the normal sampling mode, step 106.10
7. Execute the process in 108.

In this way, the override sampling mode is opposite to the normal sampling mode in that the sampling mode signal SMI is O" and 3M2 is 111 II, and the other points are the same as in the normal sampling mode. be.

Referring to FIG. 6, the sampling mode signal S M
2 is the OR circuit 45.51.55 as in S M 1.
．． 58, 61, and 65, and in this respect, the tone generator section 20 operates in exactly the same manner as in the normal sampling mode described above. The difference is that
The signal SM2 is applied to the control input of the gate 57. As a result, the waveform sample data read from the data memory 21 is input to the adder 28 and added to new waveform sample data provided from the analog/digital converter 27.

That is, as mentioned above, from the OR circuit 45 to the NAND circuit 4
4, a signal obtained by inverting the note clock pulse φ2 is applied to the read/write control manual R/W of the data memory 21, and the data memory 21 is read out in the first half of one address time. mode, and then enters write mode in the latter half. The waveform sample data of the previously sampled sound read from the data memory 21 in the first half of one address time is 11 of the signal SM2.
The signal is input to the adder 28 through the gate 57 opened by 1 II, and is added to the newly sampled external sound waveform sample data. As described above, the added waveform sample data is latched by the latch circuit 29 at the timing in the second half of one address time (timing when φ2 is r+111), inputted to the data memory 21 via the gate 30, and stored at the corresponding address. will be written to.

In this way, data obtained by adding the waveform sample data of the newly sampled sound to the waveform sample data of the already sampled sound is written into the memory 21. As described above, when the write address reaches the final address, the AND circuit 64 outputs the sampling end signal SMPE.
ND is generated. Further, as described above, the last zero-crossing address of the newly sampled waveform sample data is finally latched by the latch circuit 33.

Changing the Sampling Rate The writing rate of waveform sample data in the normal sampling mode and the override sampling mode is not limited to the standard pitch (A4 tone), and can be changed as appropriate by pressing keys on the keyboard 14.

When a key of a desired pitch desired to be set as the sampling rate is pressed on the keyboard 14, the microcomputer section detects the new pressed key and executes the key-on event routine shown in FIG. 12. In step 110, the key code related to the new key press is stored in the new key code register NKE.
Store in Y.

In the next step 111, the normal sampling flag S
MPFLG or override sampling flag 0
Check whether VWFLG is "1'". If YES, that is, either sampling mode, step 11
2, and set the contents of the new key code register NKEY as the new key code NKC to the tone generator section 2.
Send to 0. Based on this, the tone generator section 2
The node clock pulse φ generated from the note clock generation circuit 34 of 0. (that is, φ1.φ2) is the keyboard 14
It corresponds to the pitch specified by .

In this way, the desired external sound may be sampled after changing the sampling rate to one corresponding to the desired pitch.

Example of Use of Override Sampling Various overwriting modes are possible depending on the wishes of the performer, but as an example, the following harmony sampling will be explained.

For example, in the case of a C major chord, first, the sampling rate is set to the C4 note, and a tone signal of the C4 line of the desired tone is sampled externally. Next, the sampling rate is set to E4 sound, and the same C4 sound signal as above is input from the outside for override sampling. Furthermore, the sampling rate is set to 04 tone, and the same C4 tone sound signal as above is input from the outside for override sampling. In this way, C4, E4. The sum of the waveform sample data of the three tones of pitch G4 is stored in the data memory 21. In this case, by reading out the waveform sample data from the data memory 21 at a desired pitch rate corresponding to the pressed key, a musical tone signal of a major chord having the pressed key as the root note can be generated.

In this way, for example, override sampling is useful when attempting to play chords with simple key press operations. For example, when the keyboard 14 is divided into key ranges and a chord is to be played in a part of the key range, if the data memory 21 is read in response to a key press in the chord performance key range, the above-mentioned method can be used. You can play simple chords.

Processing at the end of sampling As described above, when the sampling end signal SMPEND is generated at the end of writing the external sound waveform sample data, the sampling end event routine shown in FIG. 14 is executed.

Here, first, the zero-crossing address data ZCRAD latched in the zero-crossing address latch circuit 33 of the tone generator section 20 is taken into the zero-crossing address buffer ZCRADB in the microcomputer section (step 113).

As described above, this data ZCRAD indicates the address where the last sample data of the sampled sound is stored in the memory 21.

In the next step 114, the override sampling flag 0VWFLG is set to 141 I? Check whether N
O, that is, in the normal sampling mode, the process proceeds to step 115, and the zero cross address buffer ZC:RA
Store the contents of DB in the end address buffer LPADB. In this way, the last zero-crossing address data of the waveform sample data is stored in the buffer LPADB as end address data.

Next, the sampling flag SMPFLG and 0VWFL
In step 116), the content of the signal sent to the tone generator unit 20 is set to S M
1 and 3M2 are both “0”, Ml is “1”, M2 to M8
are set to 11011, respectively, and the contents of buffer LPADB are sent as end address data LPAD (
Step 117).

And key-on pulse 0KONP for parrot sound.
is sent to the tone generator section 20 (step 11
8). This key-on pulse 0KONP is used to immediately generate a musical tone corresponding to the sampled waveform sample data immediately after sampling, and to confirm its contents.

O: Tsumu Nishibai' - Kono 2ri] Jikogu 薯1'1 omission 1゜When override sampling is completed, the first
Step 114 in Figure 4 is determined to be YES, and Step 1
Proceed to step 19 and save the current end address buffer LPADB.
Check whether the contents of ZCRADB (which indicates the final zero-crossing address of the waveform sample data sampled last time) are smaller than the contents of the zero-crossing address buffer ZCRADB (which indicates the final zero-crossing address of the waveform sample data sampled this time). . If YES, the process advances to step 115 and the contents of the buffer LPADB are rewritten to the current final zero-crossing address data. If No, step 115 is not performed and step 1
20 to step 116.

In this manner, in the case of overwriting, the final zero-crossing address of the data with the longest address length among the plurality of overwritten external sound sampling data is stored in the buffer LPADB as end address data.

Note that in step 120, the end address buffer L
Transfer the contents of PADB to zero-cross address buffer ZCRA
Set it in DB. This means that among the overwritten external sound sampling data, the final zero-crossing address of the currently sampled data (this was stored in the buffer ZCRADB at the previous step 119) is higher than the final zero-crossing address of the previously sampled data. Because of the small size, it was found that the final zero-crossing address could not be specified from the perspective of the entire overwritten data, so the true final zero-crossing address was determined from the perspective of the entire overwritten waveform sample data. This is to store the contents of the buffer LPADB specifying the buffer ZCRADB. As will be described later, during all cancel processing, it is necessary to return the contents of the zero-crossing address buffer ZCRADB to the end address buffer LPADB, and return the contents of the buffer LPADB to the true final zero-crossing address. It is necessary to save the final zero-crossing address in the buffer ZCRADB. For this purpose, the process of step 120 is inserted.

Automatic sound generation operation immediately after sampling When writing of externally sampled waveform sample data is completed, step 11 in FIG. 14 is completed as described above.
Key-on pulse 0KONP for parrot sound by 8
is generated automatically.

Referring to FIG. 6, in the tone generator section 20,
This parrot sounding key-on pulse KONP is input to the envelope generator 47 via the OR circuit 66, and is also input to the OR circuits 52, 53, 54 and the set manual S of the flip-flop 67.

Furthermore, the performance mode signal M1 is set to "1" by the processing in step 117 of the sampling end event routine (FIG. 14) described above, and this signal M1 is sent to the OR circuits 55, 61, and 68 of the tone generator section 20. is input.

The condition of the AND circuit 56 is established by the key-on pulse 0KONP and the signal M1 being "1", and the T-flip-flop 4
1 is set, and the direction indication signal DIR becomes "1".

Also, in response to the key-on pulse 0KONP, the OR circuit 53
A preset pulse PRP is output from. As a result, the initial address data (all “0”) is set in the selector 42.
is selected and preset in the address counter 37,
End address data LPAD is selected by selector 39 and loaded into register 40 . Further, the flip-flop 43 is set in response to the key-on pulse 0KONP, and the address counter 37 starts counting operation.

In this case, the new key code NKC has not been changed, so the note clock pulse φ has the same rate as when writing.
1 is counted. In this way, the address counter 37
performs an up-count, starting from the initial address,
The address signal changes in the forward direction with the end address LPAD as the end point.

In the data memory 21, the signals SMI and SM2 are both 110.
By being ++, the mode is always read.

In this way, the waveform sample data that was just written is read from the beginning.

On the other hand, the envelope generator 47 generates a key-on pulse of 0K.
Envelope waveform data is generated according to ONP.

In this case, each data AT, D for envelope waveform setting
As mentioned above, T, SL, and RT are initially set to the contents that set the direct keying type envelope waveform in step 106 of the timer beep end event routine (Figure 11), so they are set at a constant level from key-on to key-off. Envelope waveform data is generated. As a result, the sampled waveform sample data is produced at the same volume level. In this way, the state of the sampled external sound signal can be immediately confirmed. When the read address reaches a value corresponding to the end address data LPAD, the comparator 38 generates an end pulse END, which is applied to the AND circuit 69. The other input of this AND circuit 69 is the output 11117 of the flip-flop 67 set by the key-on pulse 0KONP.
is given, the output of the AND circuit 69 becomes "1" in response to the end pulse END, and this is sent to the OR circuit 70 as the key-off pulse OKOFP for parroting sound.
is applied to the envelope generator 47 via. Due to the key-off pulse 0KOFF automatically generated in this way, the direct keying type envelope waveform data generated from the envelope generator 47 falls to level 0. In this way, the automatic pronunciation of parrots ends. In addition, the flip-flop 67 is a key-off pulse ○KOF
It is reset by a signal obtained by delaying F by a delay flip-flop 88.

Determination of performance mode The aforementioned eight performance modes M1 to M8 (see FIG. 3) are determined according to the operation of each switch RVR8, UTRN, and LOOP.

When the reverse switch RVR8 is turned on, the reverse on event routine shown in FIG. 15 is executed, and the reverse flag RVFLG is inverted from "O" to "1" or from '1' to tg Oyt (step 121). Next Then go to step 124.

When the U-turn switch UTRN is turned on, the U-turn event routine shown in FIG. 15 is executed, and the U-turn flag UTFLG is changed from "0" to 11" or from '1" to 1 (
Olj (step 122). Next step 1
Go to 24th.

When the loop switch LOOP is turned on, the loop event routine shown in FIG. 15 is executed, and the loop flag LPF is
LG from 110 I+ to “1” or “’1” to 0
'' (step 123).

Next, go to step 124.

In step 124, each of the above flags RVFLG.

Based on the contents of UTFLG and LPFLG, performance modes M1 to M8 are determined according to the table below.

Table 1 Next, in step 125, mode signals M1 to M8 having contents corresponding to the determined performance mode are sent to the tone generator section.
Send to 0. That is, only one mode signal determined according to Table 1 above is 111 I+, and the other mode signals are 0''.

When reading out the waveform sample data stored in the key-on/off processing data memory 21 in the performance mode and generating a sound, a desired key on the keyboard 14 is pressed.

When a key is pressed, the key-on event routine shown in FIG. 12 is executed, and the key code of the pressed key is taken into the second key code register NKEY (step 110). In the next step 111, since the sampling flags SMPFLG and 0VWFLG are 10'' in the performance mode, the determination is NO and the process goes to step 126.Step 1
In step 26, a predetermined pronunciation assignment process is performed, which is a single note priority process since the single note priority pronunciation method is adopted in this embodiment.In the 0th order step 127, a new key press is performed according to the result of the single note priority process in the previous step. It is determined whether or not it is necessary to generate the musical tone related to the tone. If it is not necessary to generate the tone, the process goes to return, but if it is necessary, the process goes to step 128. As the single note priority criteria, as is well known, high note priority, late arrival priority, etc. may be adopted as appropriate. In step 128, register NK is used to allocate the new key code.
Store the new key code of EY in register KCODE. In the next step 129, the key code of the register KCODE (that is, the key code related to the newly pressed key to which the sound generation has been assigned) is sent to the tone generator section 20 as the new key code NKC. Further step 13
At 0, the key-on pulse KONP is sent to the tone generator section 20.

When the pressed key is released, the key-off event routine shown in FIG. 13 is executed. Load the key code of the newly released key into the new key code register NKEY (step 131), and set the SAMP+J'7 flag SM.
It is checked whether PFLG and 0VWFLG are 111" (step 132), and N.

If this is the case, that is, the performance mode is set, the process proceeds to step 133, and it is checked whether the released key is the key currently being sounded (NKEY=KCODE). in that case,
A key-off pulse KOFP is sent to the tone generator section 20.

4) d1 operation Next, the operation of the tone gelator section 20 in each of the performance modes M1 to M8 will be explained.

(Common explanation for each mode) In response to a key press, the key code of the pressed key is given as the new key code NKC as described above, and based on this, the note clock generation circuit 34 generates the note clock pulse φ of the pressed key. is generated. Further, the flip-flop 43 is set by the key-on pulse KONP via the OR circuit 52, and the node clock pulse φ is inputted to the count input CLK of the address counter 37, and counting of address signals is started.

The contents of the direction indicating signal DIR generated from the T-flip-flop 41 differ depending on the states of the signals M1 to M8 corresponding to each performance mode, as will be described later. Accordingly, the counting direction of the address counter 37 is determined, the address signal changes according to the note clock pulse φ1, and the waveform sample data is read from the data memory 21.

Furthermore, the key-on pulse KONP and key-off pulse KOF generated in response to key presses and key releases as described above are also used.
P passes through OR circuit 66.70 to envelope generator 4
7, and envelope waveform data is generated accordingly. The volume envelope of the waveform sample data read from the data memory 21 is controlled in accordance with this envelope waveform data, and the sound is generated. Note that the envelope waveform setting data AT, DT, SL, and RT are set by the envelope operator group 17, and the waveform sample data is controlled by the envelope waveform of an appropriate shape set accordingly. The volume envelope is controlled.

Note that the processing performed when the end pulse END is generated from the comparator 38 differs depending on the state of the signals M1 to M8 corresponding to each performance mode, as will be described later.

(Mode M1: Normal performance) When mode signal M1 is 141 PI, OR circuit 54
．． The condition of the AND circuit 56 is satisfied by the key-on pulse KONP applied through the input signal 55 and the signal M1 of 11'', the T-flip-flop 41 is set, and the direction indicating signal I0R becomes "1".

Further, a preset pulse PRP is generated from the OR circuit 53 in response to the key-on pulse KONP.

As a result, the waveform sample data is read out from the data memory 21 only once in the forward direction starting from the initial address (all "0") and ending at the end address LPAD, as in the case of the above-mentioned parrot sound generation.

When the read address reaches the end address LPAD, the comparator 38 generates an end pulse END. This end pulse END is generated by AND circuits 60, 71, 72.
, 73. "1" of the signal M1 is applied to the other input of the AND circuit 60 via the OR circuit 61, and in response to the end pulse END, the AND circuit 60. OR circuit 6
2. '1'' is applied to the reset input R of the flip-flop 43 via the delay flip-flop 63.

As a result, the read address becomes the end address LPAD.
When the address counter 37 reaches , the address counter 37 stops counting. The other AND circuits 71, 72, 73 receive the signal M1
It does not work when is "1".

In this manner, in the performance mode M1, that is, the normal memory read mode, the data memory 21 is read out only once in the forward direction to generate sound.

(Mode M2: Reverse) When mode signal M2 is 111 fi+, OR circuit 5
The condition of the AND circuit 75 is established by the key-on pulse KONP given through the circuit 4.74 and the signal M2 being "1", and the reset force R of the T-flip-flop 41 is set to "1".
” is given. This gives T-flip-flop 4
1 is reset, and the direction indication signal DIR becomes 0''.

The selector 42 selects the end address data LPAD in response to N″OI+ of the direction instruction signal DIR, and the selector 39 selects the initial address data (all “0”).
). Further, a preset pulse PRP is generated from the OR circuit 53 in response to the key-on pulse KONP. As a result, contrary to the mode M1 described above, waveform sample data is read out from the data memory 21 only once in the reverse direction starting from the end address LPAD and ending at the initial address.

When the read address reaches the initial address, comparator 3
An end pulse END is generated from 8.

This end pulse END is generated by AND circuits 60, 71.7
Join 2,73. '1'' of the signal M2 is applied to the other input of the AND circuit 60 via the OR circuit 61.
AND circuit 60 in response to the end pulse END. OR circuit 62. “1” is applied to the reset input R of the flip-flop 43 via the delay flip-flop 63. Thereby, when the read address reaches the initial address, the address counter 37 stops counting. The other AND circuits 71, 72, and 73 do not operate when the signal M2 is R1)l.

In this way, in the performance mode M2, that is, the "reverse" mode, the data memory 21 is read out only once in the reverse direction to generate sound.

(Mode M3: Loop) When mode signal M3 is “1”, OR circuit 54.55
key-on pulse KONP and signal M3 given via
The condition of the AND circuit 56 is satisfied by “1” of T-
Flip-flop 41 is set and direction indication signal DI
R becomes "1".

Further, a preset pulse PRP is generated from the OR circuit 53 in response to the key-on pulse KONP.

As a result, similarly to mode M1, waveform sample data is read out from the data memory 21 in the forward direction starting from the initial address and ending at the end address LPAD.

When the read address reaches the end address LPAD, the comparator 38 generates an end pulse END. This end pulse END is applied to the AND circuit 6o,
Since mode signals M3 to M8 are not applied to the OR circuit 61, the flip-flop 43 is not reset by the end pulse END, and the address counter 37 is not reset.
0 count does not stop.

On the other hand, due to 110 I+ of signals Ml and M2, OR circuit 6
The output of 8 is 41 Q Tl, the output of inverter 76 which inverts this becomes 1", and the output of AND circuit 72 becomes "1" in response to end pulse END.

The output “1” of the AND circuit 72 is applied to the AND circuit 77. The output signal of inverter 83, which is the other input of AND circuit 77, is signal M4. Since it is always "1" when M7 is "O", the AND circuit 77
The condition is satisfied, and the output signal 1411j of the AND circuit 77
A preset pulse PRP is generated via the delay flip-flop 78 and the OR circuit 53 in response to the delay flip-flop 78 and the OR circuit 53.

On the other hand, the end pulse END is also applied to the AND circuit 71, but since the output of the OR circuit 79 is '0'', the condition of the AND circuit 71 is not satisfied and the state of the T-flip-flop 41 does not change. Therefore, The direction signal DIR is '''
The initial address data (all LL O11) is preset in the address counter 37 again in response to the preset pulse PRP generated as described above when the read address reaches the end address LPAD. , and the end address data LPAD is loaded into the register 40. Also, the address counter 37 remains in the up-count mode.
The waveform sample data is read out again from the data memory 21 in the forward direction starting from the initial address and ending at the end address LPAD.

In this way, in the case of "loop", the waveform sample data in the data memory 21 is repeatedly read out in the forward direction, and when a musical tone based on the sampled external sound is repeatedly produced, the pressed key is released and the volume is controlled. The sound generation can be ended by attenuating the envelope.

(Mode M4: U turn) When mode signal M4 is “1”, OR circuit 54.55
○NP and signal M4 to the key-on pulse given through
1'1'', the condition of the AND circuit 56 is established, and T
- Flip-flop 41 is set and direction indicating signal D
IR becomes LL I 11.

Further, a preset pulse PRP is generated from the OR circuit 53 in response to the key-on pulse KONP.

As a result, similarly to mode M1, waveform sample data is read out from the data memory 21 in the forward direction starting from the initial address and ending at the end address LPAD.

When the read address reaches the end address LPAD, the comparator 38 generates an end pulse END. This end pulse END is applied to the AND circuit 60, but
Since mode signals M3 to M8 are not applied to the OR circuit 61, the output of the AND circuit 60 remains at "0". Furthermore, the end pulse END is applied to the AND circuit 73, and its output is also "0". In other words, signal M4 is 1
111#, if the direction indication signal DIR is '41' (that is, the address is changing in the forward direction), the signal M
The output of the AND circuit 85 to which the signal M7 and the inverted signal of the direction instruction signal DIR are input is II O'', and the output of the AND circuit 86 to which the signal M7 and the signal DIR are input is also rto'', and from the OR circuit 87 to the AND circuit 73. The applied signal is "0", and the condition of the AND circuit 73 is not satisfied. Therefore, the output of the OR circuit 62 inputting the outputs of the AND circuits 60 and 73 is "0", and the flip-flop 43 is not reset by the end pulse END generated during forward counting operation, and the address counter 37 does not stop counting.

On the other hand, OR circuit 6 is activated by 110 jl of signals Ml and M2.
The output of the inverter 76 becomes "1", and the output of the AND circuit 72 becomes "1" in response to the end pulse END.

The output It 199 of AND circuit 72 is applied to AND circuit 77. Direction indication signal DIR when signal M4 is "'1"
is “”1” (that is, the address is changing in the forward direction)
Then, the output of the AND circuit 80 to which the signal M4 and the inverted signal of the direction instruction signal DIR are input is 410'', and the output of the AND circuit 81 to which the signal M7 and the signal DIR are input is also '0''.
The output of the OR circuit 82 which inputs the outputs of the AND circuits 80 and 81 is "O", and the output of the inverter 8 which inverts this is "O".
The output of 3 is 11117, and the output of the AND circuit 77 which is manually generated is "1". Therefore, AND circuit 77
A preset pulse PRP is generated via the delay flip-flop 78 and the OR circuit 53 in response to the output signal II I N of.

On the other hand, the end pulse END is also applied to the AND circuit 71, and the output of the OR circuit 79 becomes "1" due to the signal M4 being "1".
Therefore, the AND circuit 710 condition is satisfied, ``1'' is added to the count C of the T-flip-flop 41 via the delay flip-flop 84, and the state of the T-flip-flop 41 changes from ``1'' to ``. Therefore, the direction instruction signal DIR becomes "O". As a result, the selector 42 selects the end address data LPAD, and the selector 39 selects the initial address data (all "'o"). These are selected and preset into the counter 37 and loaded into the register 40 by the preset pulse PRP generated as described above.

In this way, contrary to the previous time, waveform sample data is read out from the data memory 21 in the reverse direction starting from the end address LPAD and ending at the initial address.

When the read address reaches the initial address, comparator 3
An end pulse END is generated from 8.

This time, the direction indication signal DIR is 1 (OII), and its inverted signal is "1", and the conditions of AND circuits 80 and 85 are satisfied. As a result, the output of AND circuit 73 is "1".
Therefore, the flip-flop 43 is reset. This changes the read address to the initial address (all 110
0 ), the address counter 37 stops counting. Further, due to the output "1" of the AND circuit 80, the output of the AND circuit 77 becomes 1 (OII), and the preset pulse PRP is no longer generated.

In this manner, in the case of a "U turn", the waveform sample data in the data memory 21 is read out once in the forward direction, and then the waveform sample data in the data memory 21 is turned around in the reverse direction and read out once.

(Mode M5: Reverse loop) When mode signal M5 is II I II, OR circuit 5
The condition of the AND circuit 75 is satisfied by the key-on pulse KONP applied through the signal 4.74 and the signal MS "'11", and 1111+ is applied to the reset force R of the T-flip-flop 41. As a result, the T-flip-flop 41 is reset and the direction indication signal DIR is set to ii.
It turns on. With this direction instruction signal DIR "O)l", waveform sample data is read out from the data memory 21 in the reverse direction starting from the end address LPAD and ending at the initial address, as in the above-described mode M2.

When the read address reaches the initial address, comparator 3
An end pulse END is generated from 8.

As in mode M3 (loop), the flip-flop 43 is not reset by the end pulse END, and the address counter 37 does not stop counting. Further, the condition of the AND circuit 77 is satisfied in response to the end pulse END, and the preset pulse PRP is generated. Further, even if the end pulse END occurs, the condition of the AND circuit 71 is not satisfied, and the state of the T-flip-flop 41 does not change. Therefore, the direction instruction signal DIR remains "0" and does not change, and in response to the preset pulse PRP generated as described above when the read address reaches the initial address, the end address data LPAD is sent to the address counter 37 again. is preset, and initial address data (all 'O's) is loaded into the register 40. Further, the address counter 37 remains in the down count mode. In this way, the waveform sample data is read out again from the data memory 21 in the reverse direction starting from the end address LPAD and ending at the initial address.

In this way, in the case of "reverse loop", the waveform sample data in the data memory 21 is repeatedly read out in the reverse direction, and musical tones obtained by rearranging the sampled external sounds in the reverse direction in time are repeatedly produced. . This sound generation can be ended by releasing the pressed key and attenuating the volume control envelope.

(Mode M6: U-turn loop) When mode signal M6 is 61", OR circuit 54.55
key-on pulse KONP and signal M6 given via
1'', the condition of the AND circuit 56 is established, the T-flip-flop 41 is set, and the direction indication signal DIR
becomes 1”.

Further, a preset pulse PRP is generated from the OR circuit 53 in response to the key-on pulse KONP.

As a result, similarly to mode M1, waveform sample data is read out from the data memory 21 in the forward direction starting from the initial address and ending at the end address LPAD.

When the read address reaches the end address LPAD, the comparator 38 generates an end pulse END. When the signal M6 is "1", the condition of the AND circuit 73 is not satisfied, the flip-flop 43 is not reset by the end pulse END, and the address counter 37 does not stop counting. Furthermore, the condition of the AND circuit 77 is satisfied by the end pulse END, and the preset pulse PRP
is generated. Furthermore, since the output of the OR circuit 79 is "1" due to the signal M6 being "1", the condition of the AND circuit 71 is satisfied due to the end pulse END, and the count input signal of the T-flip-flop 410 is passed through the delay flip-flop 84. "1" is added to the T-flip-flop 4.
The state of 1 is reversed from "1" to "0". Therefore, the direction indication signal DIR becomes "0". As a result, the counting direction of the address counter 37 is reversed from the previous time, and the waveform sample data is read out from the data memory 21 in the reverse direction starting from the end address LPAD and ending at the initial address.

When the read address reaches the initial address, an end pulse END is generated, and as described above, the AND circuit 71
and 77 are satisfied, the preset pulse PRP is generated, and the state of the T-flip-flop 41 becomes 46.
0 I+ is inverted to 1'' and the direction indication signal DIR is “1”.
As a result, the counting direction of the address counter 37 returns to the forward direction, and the waveform sample data is read out from the data memory 21 in the forward direction starting from the initial address and ending at the end address LPAD. When END is generated, address counter 3
The counting direction of 7 is reversed.

Thereafter, similarly, every time the end pulse END is generated,
Repeat U-turn reading.

In this way, in the case of "U-turn loop", after reading the waveform sample data in the data memory 21 in the forward direction,
A U-turn reading operation in which the waveform sample data in the data memory 21 is read out by turning it in the opposite direction is repeated many times.

(Mode M7: U-turn/reverse) When mode signal M7 is 111 IP, OR circuit 54
．． The condition of the AND circuit 75 is satisfied by the key-on pulse KONP applied via the signal M74 and "12'" of the signal M7, the T-flip-flop 41 is reset, and the direction indicating signal DIR becomes "0".

With this direction indication signal DIR of "0", the end address L
Waveform sample data is read from the data memory 21 in the reverse direction starting from PAD and ending at the initial address.

When the read address reaches the initial address, comparator 3
An end pulse END is generated from 8.

This end pulse END is applied to the AND circuit 73, and its output is "O". In other words, signal M7 is "1"
If the direction instruction signal DIR is 0'' (that is, the address is changing in the opposite direction), the output of the AND circuit 86 inputting the signal M7 and the direction instruction signal DIR is "0", and the output of the AND circuit 85 is "0". is also "O", the signal applied from the OR circuit 87 to the AND circuit 73 is "O", and the condition of the AND circuit 73 is not satisfied.Therefore, in mode M7, the signal applied to the AND circuit 73 is "O". The flip-flop 43 is not reset by the end pulse END, and the address counter 37 does not stop counting.

Furthermore, the output of the AND circuit 81 and the OR circuit 82 is 110 N due to 111 Pl of the signal M7 and "0" of the direction indicating signal DIR, and the output of the AND circuit 77 is 110 N in response to the end pulse END, and the delay flip-flop preset pulse PRP via the OR circuit 53
is generated.

On the other hand, the end pulse END is also applied to the AND circuit 71, and the output of the OR circuit 79 becomes "1" due to the signal M7 being "1".
Therefore, the condition of the AND circuit 71 is satisfied, "1" is added to the count C of the T-flip-flop 41 via the delay flip-flop 84, and the state of the T-flip-flop 41 changes from "10" to "1". Therefore, the direction instruction signal DIR becomes "1". As a result, the selector 42 selects the initial address data (all IO).
is selected, and the selector 39 selects the end address data L.
PAD is selected and these are preset into the counter 37 and loaded into the register 40 by the preset pulse PRP generated as described above. In this way, contrary to the previous time, the waveform sample data is read out from the data memory 21 in the forward direction starting from the initial address and ending at the end address LPAD.

When the read address reaches the end address LPAD, the comparator 38 generates an end pulse END. This time, the direction instruction signal DIR is "1" and the conditions of AND circuits 81 and 86 are satisfied.

As a result, the output of the AND circuit 73 becomes ii 1 yt, and the flip-flop 43 is reset. As a result, when the read address reaches the end address LPAD, the address counter 37 stops counting. Further, the output of the AND circuit 77 becomes "0" due to the output "1" of the AND circuit 81, and the preset pulse PRP is no longer generated.

In this way, in the case of "U-turn reverse", the waveform sample data in the data memory 21 is read out once in the reverse direction, and then the waveform sample data in the data memory 21 is turned around in the forward direction and read out once.

As a result, a new performance effect is realized in which a musical tone in which the sampled external sounds are rearranged temporally backward is produced once, and then the sampled tone is rearranged temporally in the forward direction and produced once again. be able to.

(Mode M8: U-turn reverse loop) When the mode signal M8 is "1", the key-on pulse KONP given through the OR circuit 54.74 and the "1" of the signal M8
``, the condition of the AND circuit 75 is satisfied, the T-flip-flop 41 is reset, and the direction instruction signal DIR becomes 0''.

With this direction instruction signal DIR being "0", the waveform sample data is sent from the data memory 21 in the reverse direction starting from the end address LPAD and ending at the initial address, as in the above-mentioned mode M7 (U-turn/reverse). Read out.

When the read address reaches the initial aviles, comparator 3
An end pulse E ND is generated from 8.

When the signal M8 is "1", the condition of the AND circuit 73 is not satisfied, the flip-flop 43 is not reset by the end pulse END, and the address counter 37 does not stop counting. Furthermore, the condition of the AND circuit 77 is satisfied by the end pulse END, and the preset pulse PR
P is generated.

Furthermore, the output of the OR circuit 79 is set to ``1'' by the signal M8.
1'', the condition of the AND circuit 71 is satisfied by the end pulse END, and the count input C of the T-flip-flop 41 is input to the count input C of the T-flip-flop 41 through the delay flip-flop 84.
1'' is added, and the state of the T-flip-flop 41 becomes “
0” to “1”. Therefore, the direction indication signal DI
R becomes "1'". As a result, address counter 3
The counting direction of 7 is reversed from the previous time, and the initial address (
Waveform sample data is read out from the data memory 21 in the forward direction starting from all "0") and ending at the end address LPAD.

When the read address reaches the end address LPAD, the end pulse END is generated, and the conditions of the AND circuits 71 and 77 are satisfied as described above, and the preset pulse P is generated.
At the same time that RP is generated, the state of the T-flip-flop 41 is inverted from "P1" to "0" and the direction indicating signal DIR is generated.
becomes 0″.

As a result, the counting direction of the address counter 37 returns to the opposite direction, and the waveform sample data is read out from the data memory 21 in the reverse direction starting from the end address LPAD and ending at the initial address. Next, when the end pulse END is generated, the counting direction of the address counter 37 is set to the forward direction.

Thereafter, similarly, every time the end pulse END is generated,
Repeat the "U-turn/reverse" reading.

In this way, in the case of "U-turn reverse loop",
After reading out the waveform sample data in the data memory 21 in the reverse direction, "U-turn reverse" reading is repeated many times, in which the waveform sample data in the data memory 21 is turned around and read out in the forward direction.

As a result, a musical tone in which the sampled external sounds are rearranged temporally backwards is produced once, and then the sampled sounds are rearranged temporally in the forward direction and produced once again.
You can create new performance effects by repeating ``U-Turn Reverse'' many times. This sound generation can be ended by releasing the pressed key and attenuating the volume control envelope.

Increase/decrease end address゛Processing By the process of step 115 in FIG. 14 described above.

End address buffer L in the microcomputer section
As the end address data stored in the PADB, the address storing the data of the final zero-crossing portion of the sampled original waveform, that is, the final zero-crossing address (for example, an address in block units) is initially set. End address data L used by the tone generator section 20 in each of the aforementioned performance modes M1 to M8.
PAD is the data stored in this end address buffer LPADB, and if the initial settings remain as described above, the end address data LPAD described above
is the final zero-crossing address itself in the sampled original waveform (that is, the zero-crossing address buffer ZC
data stored in RADB).

In this way, when the final zero cross address data itself in the sampled original waveform is used as the end address data LPAD, musical tones corresponding to all the original waveforms sampled from the outside are produced in the performance mode. However, if the end address data LPAD used by the tone generator section 20 in each of the above-mentioned performance modes M1 to M8 is not limited to the final zero cross address data itself in the sampled original waveform, but can be changed as appropriate, the performance effect can be improved. can be further increased.

To that end, changing this end address data LPAD requires an increment switch INC and a decrement switch DE
This can be done by operating C. In this embodiment, when the sampled waveform data is repeatedly read out to produce sound, that is, when the mode is set to "r loop", "reverse loop", "return loop", or "return loop",
Such changes are possible during the "reverse loop." This is because during such repeated performances, it is quite effective to control the length of one repetition cycle by adjusting the end address. However, the present invention is not limited to this, and the end address data LPAD may be increased or decreased in other performance modes as well.

When the increment switch INC is turned on, the increment event routine shown in FIG. 17 is executed. Here, step 13
In Step 5, it is checked whether the loop flag LPFLG is "1", and if YES, the process goes to step 136, but if No, the process goes to return. This is the above-mentioned “loop” related performance mode M3. M5, M6. This is to perform this control at M8. In step 136, the contents of the end address buffer LPADB are incremented by one. Note that if the contents of the buffer LPADB reach the maximum value in this increment operation, the maximum value is held.

Since the data stored in the above-mentioned passing buffer LPADB is in block units, this increase is also performed in block units. In this case, the maximum value is "15". In the next step 137, the contents of the end address buffer LPADB are sent to the tone generator section 20 as end address data LPAD.

When the decrease switch DEC is turned on, the decrease event routine shown in FIG. 18 is executed. Step 135a here
The processing at steps 136a and 137a is almost the same as the processing at steps 135, 136, and 137 in FIG.
While the content of PADB was increased by 1, step 13
6a only decrements the contents of this buffer LPADB by 1.

In this way, by increasing or decreasing the contents of the end address buffer LPADB, it is possible to increase or decrease the value of the end address data LPAD used by the tone generator section 20.

By increasing/decreasing the value of the end address data LPAD in this way, it is possible to change and adjust the end point address in forward reading and the starting point address in backward reading, and the starting point of repetition in loop performance. You can change the address freely. Therefore, the mode of repeated reading can be freely changed by adjusting the increase/decrease change of the end address data LPAD.

For example, if noise is included in the waveform sample data stored at an address before the final address of the waveform sample data, the end address data LPA
By decreasing the value of D and adjusting the address closer to the front, it is possible to prevent addresses containing noise from falling within the range of addresses to be read from the data memory 21 during performance. You can cut the pronunciation of the sample data part.

Alternatively, by increasing the value of the end address data LPAD and adjusting it to an address beyond the final address of the waveform sample data, the data memory
The range of addresses to be read from 1 can be expanded to addresses where waveform sample data is not actually stored, and by repeatedly reading in this expanded address range, you can consciously read out data at the joints of repeated reading. It is also possible to create a special performance effect in which the sound is repeated intermittently by creating a silent section of an appropriate length.

Note that the end address buffer 7LPADB is changed by the increase switch INC and decrease switch DEC.
is the content of zero-crossing address buffer ZC:RA
The original final zero-crossing address in the original waveform stored in the DB is not changed.

This is used to return the contents of the end address buffer LPADH to the original final zero-crossing address in the original waveform during all cancel processing to be described later.

When the echo effect echo switch ECHO is turned on, the echo event routine shown in FIG. 16 is executed. In step 138, the echo flag ECFLG is inverted from "0" to "1" or from "1" to "O". In step 139, it is checked whether the echo flag ECFLG is "1" and "
1”, go to step 140 and set the loop flag L.
After saving the contents of PFLG in the loop flag buffer LPFLGB, the loop flag LPFLG is set to "1". In this way, the performance mode can be changed to modes related to "loop", i.e. "r loop", "reverse loop", "
Automatically set to ``U-turn loop'' or ``U-turn reverse loop.''

In the next steps 124a and 125a, the same processing as steps 124 and 125 in FIG. 15 is performed, and the performance mode is set to M.
Decide on one from 1 to M8. However, in this case, since the loop flag LPFLG is set to "1", r
Loop” related performance mode M3. MS, M6. It is always determined to be one of M8.

Next, in step 141, the release time buffer RT
The contents of B are stored in the release time storage buffer RTBUF, and in step 142, the contents of the release time buffer RTBUF are stored in the release time storage buffer RTBUF.
Set the contents of B to the maximum value MAX. Then, in step 143, the contents of the release time buffer RTB are sent to the tone generator section 20 as release time data R.
Send as T.

As a result, the release time of the envelope waveform data generated by the envelope generator 47 is set to be the longest, and the generated musical tone attenuates extremely slowly after the key is released. Moreover, the performance mode is “loop” related mode M
3. M5. M6. M8, the waveform sample data stored in the data memory 21 is read out repeatedly in the forward direction, reverse direction, or alternately switching between forward and reverse directions, and the volume of the corresponding musical tone gradually decreases. Repeatedly sounded at the level. Note that since the waveform sample data that is repeatedly read is a sample of external sound, it generally has its own amplitude envelope extending from the rise to the fall of the sound. Therefore, it is possible to realize an echo-like effect in which a sound with an amplitude envelope ranging from the rise to the fall of the sound is repeatedly produced many times, and the volume gradually attenuates. Moreover, the difference from a simple conventional echo is the "loop" related performance mode M3. M5. By controlling the sound production by M6 and M8, sounds may be produced in the opposite direction to their original chronological order, may be produced according to the original chronological order, or may be produced alternately in a combination thereof. Furthermore, by combining this with the above-mentioned end address increase/decrease adjustment control, it is possible to realize a free echo effect that was completely absent in the past.

When the echo flag ECFLG becomes “0”, step 1
By returning the contents of the loop flag buffer LPFLGB to the loop flag LPFLG through the process of 44, the contents of the loop flag LPFLG are returned to the state before the echo effect was applied. In the next steps 124b and 125b,
Perform the same processing as steps 124 and 125 in FIG.
The performance mode is determined to be one of M1 to M8. In the next step 145, the release time storage buffer RTBU
By returning the contents of F to the release time buffer RTB, the contents of the release time buffer RTB are returned to the state before the echo effect was applied.

All Cancel When all or certain data set, selected, changed, or adjusted on the operation panel unit 15 in relation to sampled waveform sample data is canceled and the contents of these data are sampled for the first time. If you want to return to the previous state, operate the all cancel switch CANSEL. Then, the all cancel event routine shown in FIG. 19 is executed.

First, in step 146, each flag SMPFLG, 0
VWFLG, LPFLG, UTFLG, RVFLG, E
Reset CFLG to “0”. This corresponds to each switch SMPL, 0VRWR, LO on the operation panel section 15.
This is to cancel the sampling mode and performance modes M2 to M8 set according to the operations of OP, UTRN, RVR3, and ECHO, and to initialize the performance mode M1.

In the next step 147, the original final zero cross address data in the original waveform stored in the zero cross address buffer ZCRADB is transferred to the end address buffer L.
Store in PADB. This is because, as mentioned above, the contents of the end address buffer LPADB may be changed depending on the operation of the increase switch INC and the decrease switch DEC, so such changes can be canceled and the contents of the end address buffer LPADB can be changed. This is to return to the original final zero cross address in the original waveform.

In step 148, the attack time buffer ATB,
The contents of the decay time buffer DTB, sustain level buffer SLB, and release time buffer RTB are initialized to the contents for setting the above-mentioned direct keying type envelope waveform.

This corresponds to each buffer ATB, DTB, SLB, RTB changed according to the operation of the envelope control operator group 17.
This is to cancel the contents of , and initialize the contents of the direct keying type envelope waveform.

In step 149, data to be given to the tone generator section 20 is initialized as follows and sent to the tone generator section 20. Sampling mode signal SMI
and set 8M2 to “O”.

End address data L that sets the performance mode signal M1 to "1" and sets the remaining performance mode signals M2 to M8 to "O"
Set PAD to the last zero-crossing address data stored in the end address buffer LPADB. As attack time data AT, decay time data DT, sustain level data SL, and release time data RT, the above buffers ATB, DTB, SLB, RT are used, respectively.
In the next step 150 for setting the contents of B, data for various musical tone effects are also initialized to predetermined contents.

In this way, when the all cancel switch CANSEL is operated, all or predetermined data set, selected, changed, or adjusted on the operation panel section 15 in relation to the waveform sample data are canceled. The data contents are returned to the state they were in when they were first sampled. In other words, the edited contents of various data edited in relation to the sampled waveform sample data are canceled, and the initial state before editing is returned. By being able to cancel the edited content and return to the initial state before editing, it becomes possible to freely edit without fear of failure, and editing functions related to sampled waveform sample data are now available. can be improved.

In the embodiment of Fumiyoshi Kenjo, it is assumed that the waveform sample data stored in the data memory is expressed using the PCM (Pulse Code Modulation) method, but the method is not limited to this.
The data may be expressed using an appropriate data compression method, such as adaptive differential PCM, delta modulation (DM), or adaptive delta modulation (ADM). Alternatively, the sampled waveform sample data may be written into the data memory after being subjected to appropriate data correction processing (for example, processing to normalize the amplitude level so that it is approximately constant over the entire interval). In this case, the data correction process (level standardization process, etc.) may be performed on an analog sound signal picked up by a microphone.

The processes shown in FIGS. 8 to 19 executed by software processing in the microcomputer section may be executed by a dedicated hardware circuit.

On the other hand, although the data memory read/write control circuit in the tone generator section is constituted by a dedicated hardware circuit in FIG. 6, it can also be executed by software processing in the microcomputer section. Further, in FIG. 6, some common circuits (such as an address counter) are used for read/write control, but write control and read control may be performed by separate circuits.

In the above embodiment, a single tone pronunciation method is used, but it goes without saying that a multiple tone pronunciation method may also be used. In that case, a well-known technique for processing sound generation assignment for multiple channels may be used.

Further, in the above embodiment, the musical tone generating device of the present invention is applied to an electronic musical instrument equipped with a keyboard, but the present invention is not limited to this, but it is applicable to other electric or electronic musical instruments, a modular keyboard, or an appropriate input device. The musical sound generating device of the present invention may be applied to a sound source device module that is used by selectively connecting to equipment, a sound system, an effect device, a general-purpose computer, etc. as appropriate.

Although not specifically shown in the above embodiment, the operation panel section also displays the currently selected performance mode, the contents of the currently set end address data LPAD, the contents of various envelope setting data, and other various settings. It is preferable to provide a display consisting of an LED or the like to display the contents of data, etc.

Further, in the above embodiment, three switches RVR3, UT
Eight performance modes M1~ depending on the operation of RN and LQOP
M8 is determined, but each mode M1 to M8
A separate switch may be provided for individually selecting the .

Although the tone generator section in Figure 6 uses only externally sampled sounds as its sound source, it is not limited to this, and may have other appropriate sound sources, and can select desired tones from among a plurality of ready-made tones and externally sampled tones. The configuration may be such that the tone color can be selected as appropriate.

In the above embodiment, a key-on pulse 0KONP is generated by software processing (step 118 in FIG. 14) as a trigger for automatically reproducing the sampled sound immediately after sampling the external sound. may be generated by a dedicated hardware circuit in the tone generator section. For that purpose, for example, the sampling end signal SMPE
When ND is output, that is, when the end pulse END is output, the address counter 37 does not stop counting, but continues to count up from the initial address by allowing the overflow, and the sampling end signal SMP
Input END to the envelope generator 47 as KONP (as a key-on pulse for parrot return), and set the sampling mode signals SMI and SM2 to "091", respectively.
It is preferable to set the mode signal M1 to 1''.

Furthermore, in the embodiment described above, the read rate of the data memory in the parrot pronunciation immediately after sampling the external sound is the same as the write rate, but this may be different.

The method of detecting a zero cross is not limited to the one shown in the above embodiment, and any method may be used. For example, it may be possible to detect that the level of the waveform sample data actually changes from plus to minus or from minus to plus, instead of adopting the zero judgment range with a certain width as in the above embodiment. . Alternatively, zero crossings may be detected in an analog sound signal picked up by a microphone.

Further, in the above embodiment, the addresses corresponding to the detected zero crosses are stored as data in block units, but this may be stored as data in address units.

Similarly, the end address data (LPAD) corresponding to the final zero-crossing address is not limited to data in units of blocks, but may be stored in data in units of addresses. In this case, it is preferable that the amount of increase and decrease when increasing or decreasing the end address data can also be finely adjusted for each address. In addition, the reference address to be subject to increase/decrease adjustment is not limited to the end address as in the above example.
It may be the initial address or both.

In addition, if the actual final zero-crossing address is stored for each block and the end address data is increased or decreased in block units, the actual final zero-crossing address in the block defined as the end address is stored as the end address (12-bit (end address in address units).

Furthermore, in the above embodiment, the increase/decrease adjustment of the end address data is possible when the loop flag is set, that is, when the musical tone corresponding to the sampled external sound is repeatedly sounded, but this is not limited to this, and in other cases. Alternatively, the end address data (reference address data) may be increased, decreased, or adjusted.

Furthermore, in the above embodiment, in the all-cancel process, all data set and controlled by the operation panel are canceled and returned to a predetermined initial state, but this is based on data closely related to the sampled external sound. It may be possible to cancel only 0 and return to a predetermined initial state.
For example, it is not necessary to cancel data for various musical tone effects.

〔Effect of the invention〕

As described above, according to the present invention, the waveform sample data of a sound signal inputted from the outside is read out from the storage means in the opposite direction to the address order at the time of writing, and then the waveform sample data is written. Since the sequence consisting of forward reading in the address order of the time is performed at least once, after the first sound of the musical tone in which the sampled external sounds are rearranged in the backward temporal direction, It is possible to realize a new performance effect in which the sampled sound is adjusted forward in time and sounded again. Also, new performance effects can be achieved by repeating this sequence multiple times. Therefore, an excellent effect can be achieved in that the performance performance as a sampling type musical tone generating device can be improved.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram showing an overview of a musical tone generating device according to the present invention, FIG. 2 is a hardware configuration diagram showing an embodiment of an electronic musical instrument to which the musical tone generating device according to the present invention is applied, and FIG. 2 is a diagram schematically showing the data memory read format in various performance modes realized in the embodiment of FIG. 2; FIG. 4 is a diagram showing an example of the address structure of the data memory included in the tone generator section of FIG. 2; Figure 5 is the second
Figure 6 is a block diagram showing a detailed example of the tone generator unit in Figure 2. Figure 7 is the generation of note clock pulses in Figure 6. Timing chart showing an example. 8 to 19 are flowcharts showing examples of programs executed in the microcomputer section of FIG. 2, in which FIG. 8 shows a main routine and FIG. 9 shows a sampling event routine. Figure 10 shows the override event routine, Figure 11 shows the timer beep end event routine, Figure 12 shows the key-on event routine, Figure 13 shows the key-off event routine, Figure 14 shows the sampling end event routine, and Figure 15 shows the reverse. Event routine, U-turn event routine, and loop event routine, FIG. 16 is an echo event routine, FIG. 17 is an increase event routine, FIG. 18 is a decrease event routine,
FIG. 9 shows the all cancel event routine. 1...External sound sampling means, 2...Storage means,
3...Write control means, 4...Read control means, 1
4...Keyboard, 15...Operation panel section, 16...Sampling control operator group, 17...Envelope control operator group, 18...Effect control operator group, 20...Tone Generator section, 21... data memory, 22.
...Microphone, 24...Timer beep circuit, 2
7... Analog/digital converter, 28... Adder for overwriting, 32... Zero cross detection circuit, 33
. . . Zero cross address latch circuit, 34 . . Note clock generation circuit, 37 . . . Address counter, 3
8... Comparator, 40... End point address register, 4
7...Envelope generator. Patent applicant Yamaha Co., Ltd. Representative Patent attorney Yoshihito Iizuka Figure 1 Figure 2 Figure 17 Figure 18 and Figure 19

Claims (4)

[Claims] (1) External sound sampling means for sampling a sound signal input from the outside; readable/writable storage means for storing waveform sample data; and said storage for storing the waveform sample data of the sound signal sampled by said external sound sampling means. a write control means for writing into the means; when a musical tone is to be generated, the waveform sample data of the storage means is first read out in a direction opposite to the address order at the time of writing, and then the waveform sample data of the storage means is written to the A musical tone generating device, comprising a read control means for performing at least one sequence of reading forward in the address order at the time of writing, and generating a musical tone signal corresponding to the waveform sample data read from the storage means. (2) The write control means writes waveform sample data of the sound signal into the storage means starting from a predetermined initial address, and the read control means writes waveform sample data of the sound signal in the storage means. The end address corresponding to the address to which the final part of 2. The musical tone generating device according to claim 1, wherein reading is performed with the end address as the end point. (3) The musical tone generating device according to claim 1, wherein the readout control means includes means for selecting whether to perform the sequence only once or to repeat it a plurality of times. (4) The readout control means includes U-turn readout selection means for selecting to read the waveform sample data stored in the storage means in the forward direction and then read out the waveform sample data in the reverse direction, and the storage means a reverse read selection means for selecting to read out the waveform sample data stored in the storage means in the reverse direction; and a loop read selection means for selecting to repeatedly read out the waveform sample data from the storage means; When U-turn readout and reverse readout are simultaneously selected by the selection means and the reverse readout selection means, a sequence of first reading out the waveform sample data in the reverse direction and then reading out the waveform sample data in the forward direction is performed once. , the above-mentioned sequence is repeatedly executed a plurality of times when, in addition to the selection of U-turn readout and reverse readout by the U-turn readout selection means and reverse readout selection means, repeat readout is selected by the loop readout selection means. A musical tone generator according to claim 1.