JPS599260Y2 - Tone setting device for electronic musical instruments - Google Patents

Description

[Detailed description of the invention] This invention is designed to improve the performance of an electronic musical instrument such as a music synthesizer, when setting performance sound modes such as various modulations and timbre switching settings using a plurality of voltage information signals. The present invention relates to a musical tone setting device for an electronic musical instrument that effectively executes setting and storage control.

In electronic musical instruments, when a key is operated, a sound source signal with a frequency corresponding to the pitch of the operated key is generated, this sound source signal is shaped into a timbre by a filter circuit, etc., and an amplitude envelope is set to generate a musical sound signal. This musical tone signal is expressed as a performance sound by a sound system including speakers.

In this case, in a music synthesizer, for example, the sound source circuit that generates the sound source signal is configured with a voltage-controlled variable frequency oscillator (hereinafter abbreviated as CO), and the voltage signal corresponding to the pitch of the operating key is used to control the VCO. The oscillation frequency is set to generate a sound source signal of a predetermined pitch.

This sound source signal is further shaped into a timbre by a voltage-controlled variable filter (hereinafter referred to as VCF), and an amplitude envelope is set by a voltage-controlled variable gain amplifier (hereinafter referred to as VCA) to produce a predetermined musical tone signal. do.

In this case, the above vCO, vCF, and vCA control envelope waveform signals whose voltage values change over time, such as rising, sustaining, and further attenuating in relation to key operations such as key presses and key releases. In addition, the oscillation frequency of the CO is changed in accordance with the envelope waveform, the cutoff frequency that determines the frequency characteristics, that is, the tone color, of the VCF is changed in accordance with the envelope waveform, and the amplification gain of the VCA is changed in accordance with the envelope waveform.

Then, the pitch, timbre, amplitude, etc. are modulated so that an effective performance musical tone can be expressed.

That is, in the electronic chestnut machine as described above, the VCO,
The form of the musical sound to be played is specified by the state of the waveform of the control signal supplied to the VCF and VCA, and by selecting the shape of the envelope waveform, etc., a wide variety of arbitrary performance sounds can be expressed. be done.

For this reason, the control signal generation circuit (envelope generator EG) that generates the control envelope waveform signal to be supplied to the VCO, VCF, and VCA is designed to respond to multiple condition signals to shape the waveform. Waveform signal generation control is performed.

For example, the generated envelope waveform rises to the attack level set by the attack time AT when a key is pressed, and then rises to the sustain level S at a predetermined decay time DT.
It attenuates to L and continues, and falls at the release time RT when the key is released. By applying condition signals corresponding to the above AT, DT, SL, and RT, an envelope waveform is generated in response to the key movement. Ru.

The above-mentioned condition signals are set independently to the control signal generation circuits corresponding to the VCO, VCF, and VCA, and are supplied as voltage signals, and the condition signals are applied to each variable resistor, etc. The voltage generator is set by a variable voltage generator consisting of:

In other words, by operating and setting each variable resistor,
The aspect of the musical sound played by this electronic chestnut machine is specified.

Therefore, in this type of electronic musical instrument, a large number of variable resistors that set a large number of condition signals that set the performance sound mode are set corresponding to the panel surface, and a large number of operations provided on the panel surface. Each of the variable resistors is operated and set by the child.

However, when actually playing an electronic musical instrument, it is a very complicated task to manipulate the numerous controls on the panel for each performance to create the sound of the performance, and it is difficult to create the desired sound. is difficult.

Additionally, during a performance, there are many cases where it is desired to change the performance sound to match the mood of the piece, but it is virtually impossible to directly change the sound using the panel controls as described above. .

As a means to improve this problem, a large number of combinations of condition signals based on the settings of the controls on the panel are stored in a storage device by specifying addresses, and one of them is read out by preset operation as appropriate, and the musical tone shape or It has been considered to couple it to the control signal generating section of the circuit.

For example, as shown in Japanese Patent Laid-Open No. 52-154620, a multiplexer sequentially reads a plurality of analog voltage signals corresponding to the above-mentioned condition signals from a voltage signal generating section using a plurality of variable resistors, and converts them into digital signals. It is converted into a signal and written into a storage device such as RAM by specifying an address.

The signal read from this storage device is then converted back into an analog signal and distributed as a condition signal to the control signal generating section of the musical tone forming circuit by a demultiplexer, so that a predetermined performance sound can be obtained. be.

In this case, in the voltage signal generation section, the analog voltage signal from this generation section is directly supplied to the musical tone forming section as a condition signal, and the performance sound is actually generated based on the condition signal, and the mode of the performance sound is controlled. After confirming the sound by hearing, it is necessary to digitize the analog voltage signal at that time as described above and write it into the storage device. Only by doing this can it be ensured that the condition signal to create the desired performance sound can be written and memorized. It is carried out in

However, when actually performing the above-mentioned sound creation and memorization work, the direct analog voltage signal from the voltage signal generator is used as a condition signal, and the information to be digitized and stored is determined while listening to the musical sound performed. However, there are various problems.

That is, the information stored in the storage device and used during the actual performance is obtained by converting the analog voltage signal from the voltage signal generating section into a digital signal, and converting it into a digital signal when used.
/A conversion to generate an analog voltage signal again.

In other words, the signal from the voltage signal generator is first used for musical tone formation through two signal conversion systems, an A/D converter and a D/A converter, which are set independently. Due to the conversion error of the two sets of signal conversion systems, the final D/A
A difference arises between the analog voltage signal obtained via the converter and the analog voltage signal initially obtained at the voltage signal generator.

In particular, in order to set the performance sound, a large number of condition signals are required as mentioned above, and depending on the value of the condition signal, the
The error states occurring in the /D and D/A conversion systems are different.

For this reason, the relative relationship between the analog voltage signals corresponding to each of the plurality of condition signals generated by the voltage signal generator,
A difference occurs between the relative relationships of the plurality of analog voltage signals obtained via the signal conversion system.

For example, the envelope waveform for VCO, VCF, and VCA control generated by a direct condition signal from a voltage signal generator is different from the envelope waveform shaped by a condition signal obtained via a signal conversion system. It becomes the shape,
The form of Kurion Kata precept becomes different.

In other words, there will be a difference in tone and sensation between the performance sound that was assumed when creating the sound and the performance sound that is shaped based on the stored information when actually playing the electronic instrument. It becomes difficult to set accurate performance sound.

This idea was created in view of the above points, and when creating sounds by operating the panel, it is possible to listen to the same performance sound as the performance sound generated based on the information actually stored, and to make sure it is possible. The purpose of the present invention is to provide a musical tone setting device for an electronic musical instrument that enables performance sound settings to be stored, and analog voltage signals obtained by operating settings on the panel are stored in the A/D as well as information to be stored. Then, like the readout information, it is D/A converted and provided in the form of a musical tone, and the A/D converted signal is stored.

An embodiment of this invention will be described below with reference to the drawings.

Figure 1 shows the structure of an electronic musical instrument.The keyboard circuit 11
As the key is operated, a tone pitch signal KV having a voltage value corresponding to the pitch of the operated key and a key trigger signal KTR corresponding to the key operations of key depression and key release are generated.

The pitch signal KV from the keyboard circuit 11 is supplied to the VCO 12, and the VCO 12 generates a sound source signal having a frequency corresponding to the pitch of the operated key.

The sound source signal generated by this VCO 12 is converted into a sound source signal with a sine wave, a triangular wave, a sawtooth wave, and a rectangular wave in the waveform shaping circuit 13, and each contains a large amount of high frequency and Triangular wave, sawtooth wave, and rectangular wave sound source signals in different states are supplied to the selection gate circuit 14,
A signal of one waveform is selectively derived.

The sound source signal taken out from the selection gate circuit 14 is converted into a timbre form or musical tone signal by the VCF 15.

In this case, this VCF 15 has the functions of a high-pass filter HP, a band-pass filter BP, and a low-pass filter LP, and the output musical tone signals from each of the HP, BP, and LP are supplied to the selection gate circuit 16 to Select one and derive it.

The output musical tone signal from the selection gate circuit 16 is combined with the sine wave signal obtained by the waveform shaping circuit 13 via an appropriate resistor, and then supplied to the VCA 17.

This VCA 17 controls the level or amplitude of the supplied musical tone signal, and sends it to a sound system 18 consisting of an amplifier, speakers, etc., so that it is produced as a performance sound.

In the main circuit for such a musical tone shape, first the VC
For O12, the modulation element Vib of the oscillation source signal
is added.

As this modulation element, the signal selected by the selection gate circuit 19 is taken out via the buffer amplifier 20 whose gain is controlled by the modulation degree control signal OMD. The signal E+ from the circuit 21 and the signal E which is inverted by the inverting circuit 22 are combined, and further a sine wave from the low frequency oscillation circuit section,
A sawtooth wave, an inverted waveform of the sawtooth wave, a rectangular wave, and a sampled and held signal S/H are combined, and one signal is selectively derived by the discrimination output of the voltage discrimination circuit 23.

This voltage discrimination circuit 23 is supplied with a switching command voltage signal OMS.

Here, as shown in FIG. 2, the low frequency oscillation circuit section includes a low frequency oscillator 24 that oscillates and outputs, for example, a sawtooth wave signal, and converts the output of this oscillator 24 into waveform conversion circuits 25, 2.
By converting with 6 and inverting with inverting circuit 27,
A low frequency output signal of a sine wave, a sawtooth wave, an inverted signal thereof, and a rectangular wave is obtained, and by sampling, for example, a white noise signal from the noise oscillator 28 using the rectangular wave in a sample hold circuit 29 and extracting it. , a sample-and-hold signal S/H whose level changes randomly corresponding to the period of the low-frequency oscillation signal is taken out.

Further, as shown in FIG. 3, the voltage discrimination circuit 23 sends an input voltage signal Vin corresponding to the signal OMS to multiple comparators 3
0a, 30b, . . . in parallel, and voltage signals having different values are sequentially supplied to the comparators 30a, 30b, .

Then, the output of the comparator 30a and the output of the comparator 30b.
The signals from ... are added to the higher order comparators 30a, 3.
Inverter 31a to which signals from 0b... are added
, 31b...
The generation state of the output from ... is selected by the input voltage Vin, and the input voltage Vin (OMS)
The selection gate circuit 19 selects one signal and outputs it from the gate.

A voltage discrimination circuit having such a structure is referred to as voltage discrimination circuit 3, which will be described later.
3, 35, 37, 42, 44, and 47 are similarly constructed.

Further, for the control signal generation circuit 21, the generated v
The condition signals of the time signal OX5, attack time OAT, and release time ORT of the envelope waveform for CO control are supplied, and the key trigger signal KTR from the keyboard circuit 11 generates an envelope waveform signal that rises with the key press and meets the above conditions. controlled.

That is, by selecting the envelope signal E+ or E1 in the selection gate circuit 19 based on the signal OMS, the pitch pitch of the sound source signal generated by the VCO 12 changes with the passage of time from the key depression, resulting in a sound source rich in naturalness. It is considered a signal.

Furthermore, when the selection gate circuit 19 selects a signal from the low frequency oscillation circuit section, the VCO
The 12 oscillation frequencies are periodically changed, and a sound source signal output with a vibrato effect can be obtained.

Then, the VC due to the output from this selection gate circuit 19
The degree of change in the oscillation frequency of O12 is determined by the signal OMD to the buffer amplifier 20.

Further, for this VCO 12, a voltage discrimination circuit 33 to which a foot selection voltage signal OFT is supplied performs appropriate foot selection of output sound source signals 2' to 64'.

The signals E+ and E1 from the control signal generation circuit 21 are supplied to the selection gate circuit 34 together with a low frequency sine wave signal.

This selection gate circuit 34 uses the output of the voltage discrimination circuit 35 to which the selection voltage signal PMS is supplied as one of the input signals.
is selected, and the phase modulated signal PW is sent to the waveform shaping circuit 13 via the Puffer amplifier 36 whose gain is controlled by the signal PMD.
Supplied as M.

Then, phase modulation is applied to the sound source signal from the VCO 12 to cause a change in timbre state.

Further, the selection gate circuit 14 to which the output signal from the waveform shaping circuit 13 is supplied is gate selection controlled by the output signal of the voltage discrimination circuit 37 to which the selection voltage signal WSS is supplied.

A control signal generation circuit 38 is also provided for the VCF 15 as in the case of the VCO 12.

Condition signals such as the FX5 time setting signal, attack time FAT, decay time FDT, sustain level FSL, and release time FRT are supplied to this circuit 38, and an envelope waveform signal corresponding to these conditions is applied to the key trigger KTR. Then it rises and occurs.

Then, the polarity selection circuit 39 selects the waveform polarity using the selection signal FEP, and the buffer amplifier 40 sets the level using the signal FED and supplies it to the VCF 15 as a frequency f characteristic control signal that specifies, for example, its cutoff frequency, resonance frequency, etc. .

Further, low frequency signals of various waveforms from the low frequency oscillation circuit section as described above are applied to the selection gate circuit 41, and one of the waveforms is selected by the output of the voltage discrimination circuit 42 supplied with the selection voltage signal FMS. , is applied as an f control signal to the VCF 15 via a buffer amplifier 43 whose gain is controlled by signal FMD.

In addition, this VCF15 has a frequency characteristic setting signal FFC.
, and pitch signal KV are also supplied, so that the tone color is set corresponding to the pitch.

In addition, a signal FQC for resonance Q control is also supplied.

The selection gate circuit 16 to which the output musical tone signal from the VCF 15 is supplied is subjected to gate selection control by the voltage discrimination circuit 44 to which the selection voltage signal FSS is supplied.

The envelope waveform signal from the control signal generation circuit 45 is supplied to the VCA 17 as a gain control signal.

This control signal generation circuit 45 includes a time signal of Ax5,
Each condition signal of attack time AAT, decay time ADT, sustain level ASL, and release time ART is supplied, and an envelope waveform signal that rises and decays in response to the key trigger KTR is selected, and the opening/closing of the musical tone signal and the amplitude envelope are set. become.

Further, a low frequency signal selected by a voltage discrimination circuit 47 discriminated by a selection voltage signal AMS from a selection gate circuit 46 is supplied to the VCA 17 via a buffer amplifier 48 controlled by a signal AMD, and a musical tone signal corresponding to the waveform is supplied. The amplitude is modulated to create a tremolo effect.

That is, the electronic musical instrument configured as described above can control various musical tones,
Further, the timbre aspect is set, and such musical tone setting is performed by the above-mentioned control signals and switching selection signals, and these signals are set, for example, by an operating section on the instrument panel.

This operation section includes, for example, control signal generation circuits 21, 38, 4
Analog control signals OAT, ORT, FAT, FDT, etc. for shaping the envelope waveform added to 5 etc.
. . . etc. are performed using an operator that slides the variable resistor to select, for example, the voltage discrimination circuits 23, 33, 35, 3.
Switching selection signal O for 7, 42, 44, 47, etc.
MS, OFT, PMS, FMS, FSS, MS
Digital selective signals such as the following are provided by a selector switch operator.

Specifically, as shown in FIG. 4, an operation panel section is used, and the analog control signal is an analog signal based on a divided potential from a variable resistor.

In the digital changeover switch circuit, a voltage corresponding to each switch selection terminal is set,
Each of the selected switch terminals is taken out with the voltage changed.

That is, digital switching information is extracted as an analog voltage signal.

In FIG. 4, each operation section corresponds to each signal shown in FIG. 1, and the signal OMS in FIG.
, OFT, . . . are shown by adding a dash to each of the above symbols.

FIG. 5 shows a signal storage processing section interposed between the operation panel section as described above and the musical tone shape section shown in FIG. 1. OMS',OF
Voltage signals such as T', .

The output signal EQ from the comparator 50 is supplied to the clock oscillator 51 as an oscillation command.
The oscillation signal from the A/D converter 52 is supplied to a counter circuit 52a as a step clock signal.

This counter circuit 52a is connected to the comparator 5 as described above.
The count value output signal is incremented while the comparison difference output EQ is present at 0, and the count value output signal consisting of, for example, a 6-bit binary count value is supplied to the latch circuit 52b.

The latch circuit 52b sequentially reads and latches the combined count value information by the output clock of the NAND circuit 52C supplied with the oscillation clock signal and the output signal EQ from the comparator 50.
2. Immediately after the count step of step a, the new count value is sequentially read.

The latch count value information of this A/D converter 52 is
A D/A (digital-to-analog) converter 53 converts it into analog information, and supplies it to the comparator 50 as comparison information.

That is, the counter circuit 52a is incremented by the output signal of the comparator 50 until the output voltage signal from the multiplexer 49 and the output voltage signal from the D/A converter 53 match.
The output voltage value of the D/A converter 53 increases in accordance with the progress of the count value.

In other words, when the two input voltage values to the comparator 50 match, the signal EQ disappears (becomes "0" level) and the counting step of the counter circuit 52a is stopped.

On the other hand, at the falling edge when the signal EQ disappears, the clock oscillator 51
The output CK51 of the NAND circuit 52C and the output ND of the NAND circuit 52C change to the "O" and "1" levels respectively, and the final value of the counter 52a driven by the clock oscillator 51 is latched at the rising edge of the output ND. .

(See Figure 8). Then, the latch circuit 52 b at that time
The latch count value becomes digital information corresponding to the analog voltage signal given from the multiplexer 49 at that time.

This latched digital information is supplied as write information to a storage device 54 such as a RAM, and read information from this storage device 54 is sent to the D/A converter 53 via the same data path. is being supplied to.

Controls related to the above storage operations include preset commands, writing (WRITE), and panel (PANEL).
This is performed by a control command section 55, address generator 56, control signal generation section 57, etc., which issue mode selection commands such as the following.

The address generator 56 generates an address signal in response to the command from the control command generator 55, and generates an address signal to the multiplexer 4.
9 to read the input information, and also designate a write or read address for the storage device 54.

The command generator 55 supplies the control signal generator 57 with signals corresponding to the presence or absence of operations on the preset switch group and signals corresponding to the switch settings of the light panel, etc. It supplies a clock signal, an address clear command, etc., and also receives a finish signal at the final position of the address shift from the address generator 56.

The control signal generating section 57 further issues a clear command to the counter circuit 52a and the latch circuit 52b, and further issues an output stop command to the latch circuit 52b.

Further, for the storage device 54, write, read commands (RAMR /W), operation commands (RAM Enab
le), output stop command (RAM Out Disa)
ble), etc., and further provides an operation control command to a demultiplexer 58, which will be described later.

The readout digital signal of the storage device 54 is
The D/A converter 53 converts the signal into an analog signal and supplies it to the multiplexer 58, and in response to a command from the address generator 56, the signal OM for the chestnut-shaped part shown in FIG. 1 is generated.
S, OFT,... are output sequentially.

The output signal from the multiplexer 58 is appropriately stored in a sample and hold circuit and distributed to predetermined portions of the musical tone shape section.

That is, each discrimination circuit 23, 33, 3 shown in FIG.
5, 37, 42, 44, 47.

Although an internal storage means such as a RAM is shown as the storage device 54, an external storage device 59 such as a cassette tape may be used as appropriate. Writing and reading may be controlled in the same manner as 54, or information may be exchanged with the storage device 54 and used as an information stocking means.

FIG. 6 is a diagram showing the control section in the signal storage processing section shown in FIG. 5 in more detail, and the control command generation section 55 includes a preset switch PS for address selection.
S 1 , PSS 2 , . ．． A PSS 12 is provided, and each of the switches PSS 1 to PSS12 is a push button switch that is operated to close.

Then, when the operation is turned on, AND circuits al and a
2, . . . Give a signal "1" to al2.

The AND circuits a1 and al2 include a differentiating circuit 55 which outputs an output from an OR circuit OR which obtains an output signal when any one of the preset switches PSS1 to PSS12 is turned on.
The signal from the inverter 55b, which is supplied with the signal differentiated by a, is supplied as a gate signal, and after the differential pulse from the differentiation circuit 55a falls, it is output from the AND circuit corresponding to the operated switch. The signal is now available.

The output signals of AND circuits a1-al2 are supplied to set terminals of storage flip-flop circuits F1-F12, respectively.

The reset terminals of these flip-flop circuits F1 to F12 are given reset commands from OR circuits b1 to bl2, respectively.
OR circuit 55 is supplied with the output signal from the differentiating circuit 55a and the signal from the panel switch PANEL, which is a pushbutton switch that is turned on, respectively.
An output signal of C is provided.

This OR circuit 55C includes a power-on detection circuit 55d.
It also supplies a detection signal from.

That is, when the panel switch is turned on or the power is turned on, all flip-flop circuits F1
~F12 is reset.

Furthermore, when one of the flip-flop switches PSS1 to PSS12 is operated, all the flip-flop circuits are reset once at the rising timing of the differentiating circuit 55a, and are operated at the falling timing of the output of the differentiating circuit 55a. Only the flip-flop circuits F1 to F12 corresponding to the switches set are set.

The set output signals of the flip-flop circuits F1 to F12 are applied to the encoder 55e, and 6-bit digital information corresponding to the order of the turned-on preset switch is obtained from the terminals Qo-Q5. It becomes like this.

Further, the output signal from the encoder 55e and the output signal from the flip-flop circuit F1 having the first rank are detected by the OR circuit 55f, and the preset switch PS is detected.
A detection signal APS indicating that any one of S1 to PSS12 is in the on state is obtained, and this signal is supplied to the control signal generating section 57.

The output signal of the OR circuit 55C is further supplied to the flip-flop circuit 55g as a set command.

This flip-flop circuit 55g is the differential circuit 5
5a output, and the output signal at the time of setting is supplied to the control signal generation section 57 as the panel command signal PAL.

In addition, when the write command switch WRLTE is turned on, a write command signal WRT is generated.

The address generator 56 receives information corresponding to a preset address from the encoder 55e, and further receives a clock signal CKI for address shifting from the control signal generator 57.

In the address generator 56, the input/output information OMS' and OFT of the multiplexer 49 and the multiplexer 58 are
', . . . and 'OMS, OFT, . and outputs address information for the demultiplexer 58.

A finish signal FI is generated every time this address is specified.

Further, by adding the count value of the counter counted by the clock CK1 to the preset address information from the encoder 55e, address information corresponding to the storage device 54 is outputted, and the storage device 54 is connected to the preset switch PSS. 1 to PSS 12, and each block has OMS, OFT,
A plurality of digitized condition signal groups such as . . . are written and stored.

The control signal generating section 57 detects the write command WRT from the control command generating section 55 using a differentiating circuit 57a, and the differential pulse output Q corresponding to the turning on of the write switch WRITE is output to the AND circuit 57 together with the preset turning detection signal APS.
supply to b.

The output signal of this AND circuit 57b is
The output signal (2) from the sandwich circuit 57C is supplied to the set terminal of the flip-flop circuit 57d, and the AND circuit 57C is an inverter output to which the signal FI from the address generator 56 is supplied. The signal FI is further supplied as a reset command to the flip-flop circuit 57d.

The signal APS is supplied as a set command to the flip-flop circuit 57f via the AND circuit 57e, and the OR circuit 57 is supplied with the set output signal of the flip-flop circuit 57d and the panel command switch signal PAL. The gate of the AND circuit 57e is controlled by an inverter connected to the output side of the OR circuit 57g.

That is, the flip-flop circuits 57d and 57f are
This is set to take priority when there is a Noset directive.

Output signal O when flip-flop circuit 57 d is set
is supplied to an inverter 57h, and the output signal O of the inverter 57h is supplied to differentiating circuits 57i and 57j that obtain differential pulse outputs in the negative direction at the time of falling.

Then, the output signal of the differentiating circuit 57i is sent to the inverter 57
k to the address generator 56 as an address clear command ADDCL, and further supplies the address clear command ADDCL to the inverter 5.
7 Supply to 1.

The output signal O of the inverter 571 is supplied to the AND circuit 57m together with the set output signal of the flip-flop circuit 57C to obtain an output signal [F].

The output signal 1e) from the differentiating circuit 57j is supplied to the AND circuit 57H and also supplied as a clear command to the ring counter 57p via the inverter 570.

This ring counter 57p counts the clock signal CKO from the clock oscillator 57q of, for example, 55Q KHz, and obtains a count output of 0 to 9, and the count output of "0" is output as a signal via the inverter 57r. The output of the AND circuit 57H is supplied to the address generator 56 as an address shift clock signal CK1.

Then, the output signal of the count "O" of the ring counter 57p is output as the A/D clear command signal A/DCL, and the OR circuit 57 to which the outputs of the counts "7" and "8" are combined.
The output of S is driven by a storage device (RAM ChipEnab
le) as the signal RCE and further count “8”.
The demultiplex control signal DME is obtained from the inverter 57t supplied with the output of the inverter 57t.

The output signal of the OR circuit 57S is the output signal of the AND circuit 57m.
is supplied to the AND circuit 57 u together with the output signal [F] of
The output signal of this AND circuit 57u is sent to the inverter 57
It is output as a read/write command signal RRW of the storage device 54 via V.

Further, the set output signal of the flip-flop circuit 57f is outputted as the output prohibition command A/DD signal of the A/D converter 52 and further as the storage output prohibition control signal ROD via the inverter 57W.

FIG. 7 shows the signal conversion system in the storage processing section. As mentioned above, the A/D converter 52 is composed of the counter circuit 52a and the latch circuit 52b.
Count value information from the counter circuit 52a that counts the clock signal from the clock oscillator 51 is output as 6-bit binary count information and supplied to the latch circuit 52b.

And this? Six lines for obtaining 6-bit count value information from the latch circuit 52 b are led to the D/A converter 53 and connected to a data bus with a storage device 54 (not shown). The output information from the storage device b is led to the storage device 54, and the read information from the storage device 54 is supplied to the D/A converter 53.

The D/A converter 53 amplifies the signals from the six lines from the latch circuit 52b using a buffer amplifier and combines them via a resistor, and the resistance value of each resistor is set to 6. 128r, 64r, which is inversely proportional to the weighting given to each bit of the bit code signal.
32r, 16r, 8r, 4r, 2r, r so that 6-bit digital information is taken out as an analog voltage signal, and this analog voltage signal is sent to the OP amplifier 53a, as appropriate. 53b, it is output as analog information.

That is, in the initial state, the counter circuit 52a and the latch circuit 52b are cleared by the clear command A/DCL, and therefore the latch circuit 52b
The output of the D/A converter 53 is "0", and the output of the D/A converter 53 is also "r".

When the voltage information signal is given to the comparator 50 from the multiplexer 49 in this state, the output signal EQ=“1” is emitted because the two forces applied to the comparator 50 are not equal.
The clock oscillator 51 is driven to oscillate, and the counter circuit 52 is driven to oscillate.
A will be counted in steps.

In this case, at the falling edge of the clock pulse from the oscillator 51, the latch circuit 52 is sent from the NAND circuit 52C.
A clock signal is applied to counter circuit 52a, the latest count value information of counter circuit 52a is read and latched by latch circuit 52b, and analog information corresponding to the latched count value is supplied to comparator 50. , therefore D
The clock oscillator 51 is driven to oscillate until the output information from the /A converter 53 and the manual input information from the multiplexer 49 match.

Then, when the output information of the D/A converter 53 matches the input information from the multiplexer 49, the output from the comparator 50 becomes EQ=rO and disappears, and the oscillator 51 stops and the counter circuit 52a The counting stops, and the final count value is latched and held by the latch circuit 52b, and this continues until the clear signal A/DCL is generated.

In other words, in the electronic musical instrument constructed as described above, the operating elements shown in FIG. 4 are selected using the operating elements set on the panel surface, and a large number of conditional signals necessary for setting musical tones are individually controlled. ``Panel mode'' in which the performance sound is shaped by the conditional signals set with this operation section.
``Storage mode'' in which the set condition signals are specified at a preset address and written into the storage device 54, and a ``preset performance mode'' in which a group of condition signals is read out from this stored information by specifying a preset address to form a performance sound. exists, and especially in the case of "memory mode", "
The state of the condition signal to be stored is determined by comparing and confirming the setting state of the operating section and the state of the performance sound obtained thereby using the panel mode.

First, the case of "panel mode" will be explained. In this case, only the panel switch PANEL in the command generation section 55 shown in FIG. 6 is turned on, and the preset switch PSSn (n=1.2, -12) and the write switch WRITE is not input.

Therefore, signal PAL is "1" and signals APS and W
RT is "0".

In this state, the signals (■) are "0", and since the flip-flop circuit 57C is reset by the signal FI, the signal 0 is also "O".

Therefore, signals 0 and O become "1" and ADDCL becomes "0".
”, and the signal [F] is “0”, 0,
0 becomes "1", the output signal ROD from the control signal generator 57 becomes "1", and the output from the storage device 54 is prohibited.

At the same time, the A/D output stop signal A/DD becomes "0" and
The state is such that the output of the /D converter 52 is obtained, and RRW becomes "1" and the storage device 54 is put into a read state, but this is irrelevant because the signal ROD is "r1". becomes.

In such a "panel mode" state, the clock oscillator 57q of the control signal generating section 57 in FIG.
A clock signal as shown in FIG. 8 is oscillated, and the ring counter 57p is driven to count.
A clear command signal A/DCL to the A/D converter 52 is generated in response to the count value "O" of the ring counter 57p, and the A/D converter 52 is initialized every time the ring counter 57p counts. Ru.

At the same time, along with this signal A/DCL, the inverter 57 r
The output signal ■ is generated as shown in FIG. 8, and since the signal O is "1", the output CK1 of the AND circuit 57n is generated as shown in FIG. You will progress one step at a time.

That is, multiplexer 49, demultiplexer 58
The address address for is now shifted and incremented.

At this time, a signal RCE to the storage device 54 is generated in response to the counts of "7" and "8" on the ring counter 57p, and a drive control signal DME to the demultiplexer 58 is generated from the inverter 57t in response to the count of "8". Ru.

That is, multiplexer 49, demultiplexer 58
Immediately before address increment, DME is activated by signal DME.
The signal from the /A converter 53 is output to a designated address via a demultiplexer 58.

Further, the clock signal CK from the clock oscillator 51
A clock signal CK2 having a frequency sufficiently higher than 0 is supplied to a counter circuit 52a of the A/D converter 52, and count value information of this counter circuit 52a is latched by a latch circuit 52b.

In this case, as described above, the A/D converter 52 converts the signal A
/DCL, and this clearing operation is performed in synchronization with the address conversion of the multiplexer 49. Therefore, when the A/D converter 52 is cleared, new analog information is sent from the multiplexer 49 to the comparator 50. The supply will be switched to .

For example, if the A/D converter 52 is cleared and the address of the manufacturer 49 becomes the first one, then OMS', which is the first analog input information, is selectively derived from the manufacturer 49 and sent to the comparator 50. will be supplied.

At this time, the A/D converter 52 is cleared and its count value is "0", so the output analog information of the D/A converter 53 is "0", and therefore the output EQ of the comparator 50 is "0". 1'' level, the clock oscillator 51 is driven to oscillate, and the counter circuit 52a of the A/D converter 52 is incremented.

As the count of the counter circuit 52a increases, the output count value from the latch circuit 52b also increases, and the output analog voltage value from the D/A converter 53 increases in steps as shown in FIG. When the value matches OMS', the output signal EQ from the comparator 50 disappears (becomes "O" level)
However, the oscillation of the clock oscillator 51 stops and the counting step of the counter circuit 52a stops.

That is, as the signal EQ disappears, a latch hold state occurs as shown in FIG. 8, and analog voltage information corresponding to the latch count value at that time is supplied from the D/A converter 53 to the demultiplexer 58. .

Then, when the count value of the ring counter 57p reaches "8", the demultiplexer 58 is set to the operating state by the signal DME, and the output analog information from the D/A converter 53 is transferred to the previously addressed address. Output signal OMS
It will be output as .

Then, the A/D converter 52 is cleared by the signal A/DCL generated by the count "O" of the next ring counter 57p, and the address generator 56 is incremented by the signal CKI generated at the same time. , the multiplexer 49 outputs the next input information OFT', the multiplexer 58 specifies an address to obtain the output OFT, and the A/D converter 52 converts the input information OFT' into a digital signal in the same manner as above. , and is again converted into an analog signal by the D/A converter 53, and an output signal OFT is obtained from the multiplexer 58 in response to the next signal DME.

Thereafter, each signal is sequentially read from the operation unit shown in FIG. 4 coupled to the multiplexer 49 by the address increment of the multiplexer 49 and demultiplexer 58 of the address generator 56 in response to the signal CK1. Output signal OM corresponding to each signal
S, OFT, .

That is, performance sounds based on each condition signal from the operating section shown in FIG. 4, which is set on the panel, can be obtained as the performance sound of the electronic musical instrument shown in FIG. 1.

In this case, the signal digitally converted by the A/D converter 52 is also guided to the storage device 54, but as described above, the storage device 54 is in the read mode due to the signal RRW, so it is not written. .

Of course, since the signal ROD is "1", the storage device 54 is in a state where output is prohibited, so there is no read information.

Next, in the case of "memory mode", the write switch WRITE is operated in the control command section 55, and the preset switch PSS which specifies the order of the written information is operated.
One of PSS1 to PSS12 is operated.

For example, if the write order is No. 1, the preset switch PSS 1 is turned on, and the encoder 55e outputs a 6-bit code signal corresponding to PSS 1, for example, expressed as DooooooJ, and is guided to the address generator 56. .

Therefore, from the control command section 55 to the control signal generation section, the output signal APS from the OR circuit 55 f and the signal WRT from the write command switch WRITE are sent to the control signal generation section.
' will be supplied.

Therefore, when the signal WRT is generated as shown in FIG.
With d set, the signal O rises and the signal 0 inverts and falls.

Then, the signal ADDCL is output from the differentiating circuit 57f.
is generated, a clear command is given to the address generator 56, and the address generator 56 is set to the initial state.

Furthermore, the AND circuit 57m is gate-controlled by the signal ■ corresponding to the output of the differentiating circuit 57i, and after the signal p ends, the signal [F] rises, and furthermore, the signal O rises together with the signal C to reset and hold the flip-flop circuit 57f. I come to do it.

Therefore, the signal A/D falls and the A/D converter 52
At the same time, the signal ROD rises and the output of the storage device 54 is set to an inhibited state.

Further, the ring counter 57p is cleared by the differential pulse 0 corresponding to the falling edge of the signal 0.

During this time, the oscillation clock signal CKO is being generated from the clock oscillator 57 (1), and the ring counter 57p starts counting from the rising edge of the signal O, and when the count is "0", the clock signal CKO is generated by the clock oscillator 57 (1). Signal C
KI is issued and the address of address generator 56 is incremented.

That is, in the address generator 56, the multiplexer 49
, the addresses of the demultiplexer 58 are shifted in response to the signal CK1, and the addresses in the number division corresponding to the preset position information from the encoder 55e are sequentially shifted and assigned to the storage device 54. .

That is, in response to signal CK1, multiplexer 4 is first
The input analog information OMS' is read out from 9, and this information OMS' is supplied to the comparator 50, which drives the A/D converter 52 as described above and outputs the latch circuit 52.
Digital information corresponding to the input information OMS' can be obtained from b.

Then, this digital information is sent to the ring counter 57 I
) Signal RCE generated in response to counts “7” and “8”
The data is written to the specified address of the storage device 54 in response to a storage operation command by 1 and a write command by a signal RRW obtained via an inverter 57V in response to this signal.

Hereinafter, in response to the generation of signal CK1, multiplexer 4
9, the analog information OMS'~AR coupled to this multiplexer 49
All of T' is digitally converted and written and stored in the division range specified by the preset switch of the storage device 54. In this state, the finish signal FI is generated, which resets the flip-flop circuit 57d and exits from the write state. It will be inverted to the read state.

In the case of the above writing, the count of the ring count counter 57p is “
8", the signal DME is generated and the demultiplexer 58 is enabled to output. However, since the output of the storage device 54 is prohibited by the signal ROD, the musical tone form or No output condition signal can be obtained for this purpose.

That is, in the "panel mode", performance sounds corresponding to conditions set on the panel operation section are obtained from the electronic musical instrument, and operation settings can be made on the panel surface while confirming the performance sounds audibly.

In particular, in the above-mentioned "panel mode", the analog condition signal set on the operation section is not directly supplied to the musical tone form or circuit, but the set condition signal is used as in the "memory mode". OMS' to ART' are converted into digital signals, and this digital signal is again converted into an analog voltage signal OMS-ART by a D/A converter 53, and then supplied to a musical tone shape section to control the musical tone shape. ing.

That is, even in the "panel mode", the storage device 54
The performance sound is generated using the same digital information as the state to be stored in the A/D converter 52, the D/D converter 52, and the D/D converter 52.
Even if there is a conversion error in the A converter 53, the performance sound including the conversion error is expressed in the "panel mode."

Therefore, if you operate the panel while checking the performance sound in "panel mode", convert this panel operation setting state to "memory mode", and write and store each condition signal in the storage device 54, you can “Panel mode” depending on memory information? It is possible to reliably reproduce the obtained performance sound.

Next, a "preset performance mode" in which the electronic musical instrument is actually played using the information stored as described above will be explained.

In this case, the control command section 55 uses preset switches PSS1 to PSS1 for selecting the type of performance sound mode.
2, and the panel switch PANEL and write command switch WRITE are opened.

That is, the signal APS appears as "1" from the control command section 55, and a code signal corresponding to the operated preset switch is generated from the encoder 55e.

Therefore, in this state, the signals ■, ■, and O become "0", and the signal 0 becomes "1".

Therefore, the signal ADDCL becomes "O" and ■ becomes "1".

Since the signal O is "01", the signal [F], 0 is r
, -, and the signal 0 is held at "1".

Therefore, the flip-flop circuit 57f outputs the signal APS
The signal A/D becomes “1” and the A/D
The output of the D converter 52 is prohibited.

At the same time, when the signal ROD is "0", the output inhibition of the storage device 54 is canceled.

Also, since the signal [F] is "0", the signal RRW is r1
”, and the storage device 54 is placed in a read state.

In this state, as shown in FIG.
Ring counter 5 is activated by clock signal CKO from q.
7 p is counted, and this ring counter 57
A signal A/DCL is generated in response to an “O” count of p;
At the same time, a signal is generated, and the address generator 56 is controlled to advance the address from the initial state.

That is, the signal CKI
When this occurs, an address signal that is sequentially shifted is applied, and addresses are sequentially designated to the storage device 54 from the beginning in the storage area corresponding to the preset position information from the encoder 55e.

Then, in response to the signal RCE corresponding to the count of the ring counter 57 I), information is read from the designated address of the storage device 54, converted into an analog voltage signal by the D/A converter 53, and then sent to the demultiplexer 58. The signal DME is supplied and output in response to the signal DME.

That is, each time the signal CK1 is generated, the multiplexer 5
8, analog information OMS, OFT, . You will be able to get it.

Then, when the information in the preset selected range is read out and cycled through, the address address in the address generator 56 is returned to the initial state again.

Then, the stored information corresponding to the specified preset is repeatedly read out again, and the musical tone shape or control of the electronic musical instrument is continued.

As described above, according to this invention, a large number of condition information set on the panel is written into the storage device with preset selections, and the mode of the performance sound is selected as a preset during the performance, thereby fully demonstrating the expressive power of the performance. It will be possible to do so.

In particular, in the case of this invention, it is possible to perform performance by setting the musical sound form dictated by the stored information and the chestnut sound form when set on the panel in the same state, and it is possible to perform performance by setting the musical sound form dictated by the stored information and the chestnut sound form in the same state. When setting the tone while listening to the performance sound using a variable resistor, etc., the condition signal can be stored in the storage device, read out, and used to reliably monitor the condition without error. Its practical effects are remarkable.

[Brief explanation of the drawing]

Fig. 1 is a diagram illustrating an electronic musical instrument according to an embodiment of the invention, Fig. 2 is a diagram illustrating an example of a low frequency oscillation circuit of the above embodiment, and Fig. 3 is a diagram illustrating an example of a voltage discrimination circuit. , FIG. 4 is a diagram illustrating an operation control command section for setting various condition signals, etc. for musical tone shaping of the electronic musical instrument, and FIG. 5 is a diagram illustrating a storage processing control section for the various condition signals, etc. 6 is a diagram showing the storage processing control section in more detail, FIG. 7 is a diagram showing the signal conversion section taken out, and FIGS. 8 to 10 are diagrams showing the panel mode in the control section, respectively. FIG. 3 is a signal waveform diagram for explaining the effects in the storage mode and preset performance mode. DESCRIPTION OF SYMBOLS 11... Keyboard circuit, 12... Voltage controlled variable frequency oscillator, 13... Waveform shaping circuit, 14, 16, 1
9, 34, 41, 46... selection gate circuit, 1
5... Voltage controlled variable filter, 17... Voltage controlled variable gain amplifier, 21, 38, 45... Control signal generation circuit, 23, 33, 35, 37, 42,
44, 47... Voltage discrimination circuit, 49... Multiplexer, 50... Comparator, 51... Clock oscillator, 52... A/D converter, 53... D/A converter, 54...Storage device, 55...Control command generation unit, 5
6...Address generator, 57...Control signal generation section,
58...Demultiplexer.

Claims (1)

[Scope of utility model registration request] A musical tone shape or circuit that generates a tone source signal corresponding to a key operation and changes the tone color shape of this tone source signal to produce a musical tone signal, and a plurality of voltage information that sets the form of the musical tone signal formed by this musical tone shape or circuit. a plurality of variable voltage generators each generating a signal;
A storage device, the voltage information signals of each of the plurality of variable voltage generators are sequentially selected by a multiplexer, converted into digital signals, and sequentially written into the storage device, and the information stored in the storage device. In an electronic musical instrument, the digital signal is sequentially read out, converted into an analog signal, and then distributed and supplied to the musical tone forming circuit using a multiplexer. Comparing means for comparing the output analog signal of the A converting means and the voltage information signal from the multiplexer to detect a match; and a comparing means for performing a counting operation in accordance with a clock signal and supplying the counted value information to the D/A converting means. digital counting means for supplying the count value information of the counting means when the comparison means detects a match to the storage device as write information, and storing the count value information of the storage device together with the count value information of the counting means. The readout information is led to the D/A conversion means, and its analog output signal is supplied to the demultiplexer, and the D/A conversion means is configured to switch and select either the count value information or the readout information. What is claimed is: 1. A musical tone setting device for an electronic musical instrument, characterized in that the musical tone setting device is configured to supply a musical tone with