JPS63169696A - Musical sound generator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention samples a sound signal input from the outside and stores it in a memory, and then samples the waveform sample data stored in this memory in response to a key operation, etc. Regarding a sampling-type musical tone generation device that generates musical tones by reading out musical tones at a desired pitch, in particular, waveform sample data stored in a memory is read out in the forward or reverse direction with a predetermined reference address as the starting point or ending point. The present invention relates to a musical tone generating device in which the reference address can be adjusted arbitrarily by a performer.

[Conventional technology]

As a sampling type musical tone generating device, there is one disclosed in Japanese Patent Publication No. 33199/1983, for example.

In such a conventional sampling-type musical tone generator, a storage area for musical waveform sample data for one tone is determined in advance in the memory, and when reading data, all addresses in this fixed storage area are read out. It has become.

In addition, Japanese Patent Publication No. 61-47435 discloses that when repeatedly reading sampled waveform data of multiple cycles, a start address and an end address are detected corresponding to the beginning and end of the waveform data, and the end address is reached. The system returns to the start address and repeats reading. In this case, the start address and end address are detected based on the detection of zero crossings of waveform data.

[Problem that the invention seeks to solve]

In a sampling type musical tone generator, the waveform data stored in the memory is not only read out once in the forward direction, but also read out repeatedly in the forward direction many times, or read out once in the reverse direction.
read out multiple times, or read out in the opposite direction many times,
Alternatively, it has been considered to perform reading in various ways, such as reading once in the forward direction and then reading once in the reverse direction, to produce musical tones based on the sampled sounds in various variations.

In this case, in the prior art such as the former, a fixed storage area of the memory is read over all addresses, and therefore it is possible to repeat only a fixed pattern over all addresses. In addition, if the sampled sound is stored in only a portion of the storage area, addresses where no waveform data is stored will be read out repeatedly during repeated reading, resulting in a long blank period for sound production. Problems also arise, such as when the sound is too long or when the sound is read out in the reverse direction, the sound does not start immediately.

In the latter type of conventional technology, a start address and an end address are detected corresponding to the beginning and end of external sound waveform sample data stored in memory, and readout control is repeatedly performed between the start address and end address. , the above problem does not occur, but once the start address and end address have been detected, it is not possible to change or fine-tune them, so it is not possible to freely change the mode of repeated reading. .

Further, for example, if the waveform data stored at an address before the end address contains noise, it is not possible to cut it. Furthermore, it was not possible to create a special performance effect in which the sound was repeated intermittently by intentionally creating a silent section of an appropriate length at the joint between repeated readings.

This invention has been made in view of the above points, and when reading out waveform sample data stored in memory in a forward or reverse direction using a predetermined reference address as a starting point or end point, a performer can freely select the reference address. The present invention aims to provide a musical tone generating device with improved performance performance by making it possible to adjust the performance.

[Means for solving problems]

A musical sound generation device according to the present invention includes an external sound sampling means for sampling a sound signal inputted from the outside, a readable and writable storage means for storing waveform sample data, and a sound signal sampled by the external sound sampling means. write control means for writing waveform sample data into the storage means; read control means for reading out the waveform sample data from the storage means in a forward or reverse direction using a predetermined reference address as a starting point or end point; and a reference address adjustment means for increasing or decreasing the reference address, and is adapted to generate a tone signal corresponding to the waveform sample data read from the storage means.

This is illustrated in FIG. 1, where 1 is an external sound sampling means, 2 is a storage means, 3 is a write control means, 4 is a read control means, and 5 is a reference address adjustment means.

[Effect]

The sound signal input from the outside is sent to external sound sampling means 1.
The waveform sample data of the sampled sound signal is written into the storage means 2 under the control of the write control means 3. In the read control means 4,
The waveform sample data in the storage means 2 is read out in the forward direction or in the reverse direction using a predetermined reference address as the starting point or ending point.

The value of this reference address can be increased or decreased by the reference address adjustment means 5. A musical tone signal corresponding to the waveform sample data read out from the storage means 2 is generated.

By changing the value of the reference address by the reference address adjustment means 5, the address of the starting point or end point when reading the waveform sample data from the storage means 2 in the forward or reverse direction is changed. By changing the read start point or end point address, the range of addresses to be read from the storage means 2 is changed, and the range of generated sounds is changed.

As a result, 1. For example, if the original reference address is set to the final address of the waveform sample data, and the waveform sample data stored at the address before this final address contains noise, By appropriately adjusting the reference address toward the nearer address, it is possible to prevent addresses containing noise from falling within the range of addresses to be read from the storage means 2.

In this way, it is possible to cut out the sound of the part of the waveform sample data that includes noise.

Alternatively, when the original reference address of 1 is set to the final address of the waveform sample data, by appropriately adjusting the reference address to an address beyond this final address, the range of addresses to be read from the storage means 2 can be set to the waveform sample data. Sample data can be expanded to addresses where it is not actually stored, and by repeatedly reading in this expanded address range, a silent interval of an appropriate length can be intentionally created at the joint between repeated reads. It is also possible to create special performance effects in which sounds are repeated intermittently. Furthermore, the mode of repeated reading can be freely changed by other adjustment methods.

In this way, by allowing the performer to arbitrarily adjust the reference address that is the starting point or ending point when reading out the waveform sample data stored in the memory in the forward or reverse direction, it can be used as a sampling-type musical tone generator. performance performance can be improved.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 shows the hardware configuration of an embodiment of an electronic musical instrument to which the musical tone generator according to the present invention is applied.

In the electronic musical instrument of this embodiment, various operations and processes are controlled by a microcomputer section including a CPU (Central Processing Unit) 11, a program ROM (Read Only Memory) 12, and a data and working RAM (Random Access Memory) 13. . The keyboard 14 includes a plurality of keys for specifying pitches of musical tones.

The operation panel unit 15 includes a sampling control operator group 16 for controlling the external sound sampling operation and its readout operation, an envelope control operator group 17 for setting and controlling the envelope waveform of musical tones, and various types of controls. an effect control operator group 18 for setting and controlling musical tone effects;
A group of operators 19 for setting and controlling various musical tones are also provided.

In the sampling control operator group 16, the sampling switch SMPL and the override switch ○VRWR
is a switch that instructs to write the external sound waveform sample data into the data memory 21 in the tone generator section 20. reverse switch rvr
8 and U-turn switch UTRN and loop switch LOO
P and the echo switch ECHO are switches for instructing the performance mode when reading the waveform sample data stored in the memory 21 and performing the performance.

The sampling switch SMPL is operated to instruct that external sound sampling should be performed.

The override switch 0VRWR is operated to instruct that external sound sampling should be performed in the same way as described above, but it is used to override external sound waveform sample data that has already been stored in the memory 21. This operation is used to instruct to overwrite waveform sample data of another external sound without erasing it (this is called r override). On the other hand, when sampling is instructed by the sampling switch SMPL, the previously stored external sound waveform sample data is erased.

The reverse switch RVR8 is operated to instruct a performance to be performed by reading out the external sound waveform sample data stored in the memory 21 in the reverse direction. This kind of reading is simply called "reverse". In addition, the memory 21
Reading in the reverse direction means reading in order from the address with the largest value. On the other hand, reading the memory 21 in the forward direction means reading data in order from the address with the smallest value.

The U-turn switch UTRN is operated to instruct a performance in which the external sound waveform sample data stored in the memory 21 is read out in the forward direction and then turned back and read out in the reverse direction. This type of readout is simply called a "U-turn".
That's what it means.

In addition, it is possible to select and instruct "U-turn" and "reverse" at the same time. In that case, after reading out the external sound waveform sample data stored in the memory 21 in the reverse direction, the data is turned back in the forward direction. read out. This is called a ``U-turn reverse''.

The loop switch LOOP is operated to instruct repeated reading of external sound waveform sample data stored in the memory 21. This kind of reading is simply called a "loop." A normal "loop" is memory 2
The external sound waveform sample data stored in step 1 is repeatedly read out in the forward direction.

This is called a "normal loop."

It is possible to select and instruct "loop" and "reverse" at the same time, and in that case, the external sound waveform sample data stored in the memory 21 is repeatedly read out in the reverse direction. This is called a "reverse loop."

It is possible to select and instruct "loop" and "U-turn" at the same time. In that case, after reading out the waveform sample data of the external sound stored in the memory 21 in the forward direction, it is read out in the reverse direction. repeat. This is called “
It's called a U-turn loop.

It is possible to select and instruct "loop", "U-turn" and "reverse" at the same time. In that case, memory 2
After reading out the waveform sample data of the external sound stored in 1 in the backward direction, the process repeats the process of turning back and reading out the data in the forward direction. This is called a "U-turn reverse loop."

A list of performance modes as described above is shown in FIG. There are eight performance modes, and each mode is distinguished by symbols M1 to M8. The left column shows the mode name, which corresponds to the names mentioned above. Therefore, the conditions under which each mode is selected will be clear from the above description. In addition, "Normal" mode M
1 is a mode in which the external sound waveform sample data stored in the memory 21 is read out only once in the forward direction, and this "normal" mode is selected when no special modes M2 to M8 are selected.
mode. The right column schematically shows the readout state of waveform sample data from the memory 21 in each mode, and the direction of the arrow indicates whether the readout is in the forward or reverse direction. Mode M3 related to “loop”. M
5. M6. In M8, reading as shown in FIG. 1 is repeated. The starting point in forward reading is a predetermined start address, and the ending point is a predetermined end address. Conversely, the starting point in backward reading is the end address, and the ending point is the start address.

The start address and end address serve as reference addresses that indicate the starting point or ending point in forward or backward reading. In this embodiment, one reference address, or start address, is always fixed at a predetermined initial address (for example, address 0), and the other reference address, or end address, corresponds to the final zero-crossing address of the sampled waveform data. It is designed to change as appropriate. Further, the value of this reference address, that is, the end address, can be increased or decreased as appropriate by the performer. In this embodiment, the value of the end address is increased or decreased in mode M3. M5. This is possible when M6° to M8.

In the sampling control operator group 16, an increase switch I is used to instruct increase/decrease change of the above-mentioned end address.
NC and a reduction switch DEC are provided. The address value increases according to the operation of the increase switch INC, and the address value decreases according to the operation of the decrease switch DEC. In this example.

- As an example, an increase switch INC and a decrease switch DEC
Increasing or decreasing the end address is performed not in units of one address, but in units of blocks made up of multiple addresses.

Here, the data memory 2 in the tone generator section 20
An example of the address structure in No. 1 will be explained with reference to FIG. The entire range of addresses for storing waveform sample data of external sound for one tone consists of 16 blocks from 0 to 15, and one block consists of 256 addresses. The first address of this entire address range is the start address, and has an address value of O. The end address changes as appropriate in response to the final zero-crossing address of the sampled waveform data. In this embodiment, this end address is also determined on a block-by-block basis. The value of this end address is increased or decreased according to the operation of the increase switch INC and decrease switch DEC.

An echo switch ECHO provided in the sampling control operator group 16 is for selecting an echo effect. The echo effect referred to here means that the performance mode is automatically set to "loop" and the release time of the volume envelope of the generated musical sound is automatically set to be long (for example, to the longest). The purpose is to repeatedly read data from a memory 21 and to cause the musical tone to be repeatedly sounded while gently attenuating the volume envelope of the musical tone signal corresponding to the read waveform data.

The all-cancel switch CANSEL provided in the sampling control sensor group 16 cancels all or predetermined data of various types set, selected, changed, and adjusted on the operation panel section 15 in relation to the sampled waveform sample data. It is operated to cancel and return the contents of these data to the state they were in when they were first sampled.

In other words, it is for canceling the contents of the t1g collection of various data edited in relation to the sampled waveform sasiple data and returning to the initial state before editing. By being able to cancel the edited content and return to the initial state before editing, it becomes possible to freely edit without fear of failure, and editing functions related to sampled waveform sample data are now available. can be improved.

Envelope control operator group 1 in operation panel section 15
Reference numeral 7 includes operators for setting and controlling the characteristics of the volume envelope waveform to be applied to the waveform sample data read from the data memory 21, such as A, D, S, R, attack time, decay time, which determines the characteristics, It consists of operators that set and control the sustain level and release time, respectively.

The effect control operator group 18 on the operation panel section 15 includes operators for setting and controlling musical sound effects such as vibrato, tremolo, and reverb, for example.

The tone generator section 20 has a function of sampling a sound signal input from the outside through a microphone 22 and converting it into digital waveform sample data, a function of writing the sampled digital waveform sample data into the data memory 21, and a function of writing the sampled digital waveform sample data into the data memory 21. It has a function of reading waveform sample data from the data memory 21 in response to key presses, etc., and a function of controlling the volume envelope of the read waveform sample data and adding various musical sound effects. The digital musical tone signal generated from the tone generator section 20 is converted into an analog signal and then provided to the sound system 23.

The timer beep circuit 24 is a circuit for generating a beep sound for a certain period of time when sampling of external sound is started. The beep sound generation time is, for example, about 300 m5, and the sound starts in response to the operation of the sampling switch SMPL, and when it ends, the beep end pulse BPEND is generated.
occurs. Based on the beep end pulse BPEND, the tone generator section 2o starts a sampling operation.

Key scanning and sound generation assignment processing for detecting key presses and key releases on the keyboard 14, scanning for detecting shaking of switches and the like on the operation panel section 15, and lighting/extinguishing processing of indicators, etc., and processing on the tone generator section 20. Various processes such as writing and reading control of sampling data are executed by the microcomputer section.

Among the processes executed by the microcomputer unit, examples of flowcharts of processes related to the present invention are shown in FIGS. 8 to 19.

Data and working R used in connection with this process
An example of the contents stored in AM13 is shown in FIG.

SMPFLG is a sampling flag and becomes 1'' in normal sampling mode.

○VWFLG is an override sampling flag and becomes 14111 in override mode.

RVFLG is a reverse flag, and becomes "1" in the "reverse" performance mode. This flag changes from 1'1'' to 11 every time the reverse switch RV RS is turned on.
0” or from “0” to l(III).

UTFLG is a U-turn flag, and becomes "1" in the r[turn] performance mode. This flag is inverted from 1 to 0 or from 0 to 1 every time the U-turn switch UTRN is turned on.

LPFLG is a loop flag and becomes '1' in the 'loop' performance mode.This flag is inverted from '1' to 1101+ or from '0' to 111 II every time the loop switch LOOP is turned on. .

ECFLG is an echo flag and becomes "1" when an echo effect is selected. This flag is inverted from "1" to LL OII or from "O" to 0111 every time the echo switch ECHO is turned on.

LPFLGB is a loop flag buffer, and is used to store the contents of the immediately preceding loop flag LPFLG in order to force the contents of the loop flag LPFLG to 1''' when the echo effect is selected. The contents stored in this buffer LPFLGB are returned to the loop flag LPFLG when the echo effect is no longer selected.

NKEY is a double key code register, which stores the key code of a newly pressed or released key.

KCODE is a key code register that stores the key code corresponding to the musical tone currently being produced.

ZCRADB is a zero-crossing address buffer,
It stores the final zero-crossing address of waveform sample data sampled externally.

LPADB is an end address buffer that stores the aforementioned end address.

ATB is attack time buffer, DTB is decay time buffer, SLB is sustain level buffer, R
TB is a release time buffer, which stores data on the attack time, decay time, sustain level, and release time set and controlled by the envelope control operator group 17, respectively.

RTBUF is the release time storage buffer, when the echo effect is selected the release time buffer RT
This is to save the immediately preceding contents of the release time buffer RTB in order to forcibly set the contents of B to the longest time. The contents saved in this buffer RTBUF are returned to the release time buffer RTB when the echo effect is no longer selected.

Areas are provided in the data and working RAM 13 for registers, flags, or buffers as described above. Also, in the data and working RAM 13, there is a group of effect control operators 18 in the operation panel section 15.
and an area for storing operation detection data of the other operator group 19.

Other data and working areas are provided.

A detailed example of the tone generator section 20 is shown in FIG.

At the tone generator section 2° C. in FIG. 6, an interface 26 is provided to exchange data with the microcomputer section via the data bus 25. Interface 26 includes a buffer register. The data given from the microcomputer section is sent to the tone generator section 2 via the interface 26.
It is input to a predetermined circuit within 0. Furthermore, data output from a predetermined circuit within the tone generator section 20 is given to the microcomputer section via an interface 26 and a data bus 25.

To briefly explain the main circuits in the tone generator section 20, the data memory 21 has an address structure as shown in FIG. If it is "0", it will be a read mode, and if it is "0", it will be a write mode. AD is an address input, and DT is a data input/output terminal.

The external sound signal picked up by the microphone 22 is sampled by the analog/digital converter 27 in accordance with the clock pulse φ□ and converted into a digital signal. The digitally converted waveform sample data is transferred to an adder 28 for overwriting, a latch circuit 29 . The signal is applied to the data input/output terminal DT of the data memory 21 via the gate 30. Further, the waveform sample data outputted from the analog/digital converter 27 is provided to a rising edge detection circuit 31, and the rising edge of the sound is detected. A trigger pulse TRG is output in response to the detection of the rise of the sound. This trigger pulse T
RG is used as a signal to instruct the timing to start writing waveform sample data into the data memory 21.

Further, the waveform sample data output from the analog/digital converter 27 is provided to a zero cross detection circuit 32, and zero crosses are detected. In this embodiment, in order to simplify the configuration of the zero cross detection circuit 32, the level of the waveform sample data is determined to be within a predetermined zero judgment range (range of ±α of the zero level, where α is an appropriate level). is detected, and a zero cross detection pulse ZCR is output when the zero determination range is exceeded. - The zero cross detection pulse ZCR is applied to the latch control input of the zero cross address latch circuit 33, and the write address when the zero cross is detected is latched into the latch circuit 33. Since the zero cross detection pulse ZCR is generated every zero cross of the waveform sample data, the zero cross address of the latch circuit 33 is rewritten many times, and the data finally left in the latch circuit 33 is the final zero cross address of the waveform sample data. It is.

The note clock generation circuit 34 has a two-knee key code NK.
Note clock pulse φ in response to C. occurs. The new key code NKC is for specifying the write rate or read rate of the data memory 21, and is set to a key code of a predetermined reference pitch (for example, A4 note) at the time of sampling, and is used to specify the write rate or read rate of the data memory 21. Changes will be made accordingly. Note clock pulse φ. are divided into 1/2 by the frequency divider 35, and the note clock pulses φ1. φ2 is obtained. The phase-advanced note clock pulse φ is input to the count clock CLK of the address counter 37 via the AND circuit vfJ36. The slow-phase node clock pulse φ2 is transmitted through the NAND circuit 44 to the data memory 21 read/write control manual power R.
/Join W.

Control its read/write mode.

As described below, the sampling mode (normal sampling mode or override sampling mode)
At this time, the signal SMI or 5M2 becomes "1", and IJ I II is applied from the OR circuit 45 to the NAND circuit 44. As a result, the NAND circuit 44 inverts the delayed note clock pulse φ2 and applies it to the manual read/write control R/W of the data memory 21. Therefore, the data memory 21 is
When the leading phase note clock pulse φ is “1”, the read mode is activated, and the slow phase note clock pulse φ2 is 111 I
When it is I, the write mode is entered, and the read/write mode is switched in a time-sharing manner within the time of one address. This is a procedure for the override sampling mode, which will be described later. In the various performance modes M1 to M8, the signals SMI and 5M2 are 0'', the NAND circuit 44 always outputs 1, and the data memory 21 is always in the write mode. Since the frequency-divided note clock pulse φ1 is counted by the address counter 37, the note clock generating circuit 34 is assumed to generate a note clock pulse φ having twice the frequency of the target node clock pulse φ□.

The address counter 37 generates an address signal that specifies the read address of the data memory 21, and the preset pulse PRP applied to the preset control input PR.
The 6-address counter 37 is an up/down counter that presets the preset data added to the preset data human power PRD according to the preset data, and counts note clock pulses φ□ added to the count clock human power CLK using this preset value as a starting point. Instruction signal DIR
When is 1'', an up count is performed, and when is 0, a down count is performed.

The output of the address counter 37 is applied to the address input AD of the data memory 21 and also to the comparator 38, and the higher 4 bits are input to the zero-cross address latch circuit 33. The address signal consists of 12 bits, the upper 4 bits identify each block from 0 to 15, and the lower 8 bits identify 256 addresses within one block. By latching the upper four bits of the address signal in the zero-crossing address latch circuit 33, the zero-crossing address is detected in block units. Latch circuit 33
The zero-crossing address data ZCRAD latched in is supplied to the microcomputer section via the interface 26.

Comparator 38 is for detecting whether the address signal generated from address counter 37 has reached the end point. When the address signal is progressing in the forward direction (that is, increasing), the end address data LPAD is selected by the selector 39 and stored in the end point address register 40, and the end address data LPAD stored in this register 40 and The comparator 38 compares the address signal with the address signal, and when the two match, outputs the end pulse END (
On the other hand, when the address signal is progressing in the opposite direction (that is, decreasing), the selector 39 selects the initial address data in which all 12 bits are "0", and the end point address register 40 The initial address data stored in this register 40 and the address signal are compared by the comparator 38, and when the two match, an end pulse END is output.

Selection control of the selector 39 is performed by a T-flip-flop 41
This is done in response to the direction instruction signal DIR output from the.

When this direction instruction signal DIR is "1", that is, when it instructs a forward change of the address, the B input is selected and 0
”, that is, when instructing to change the address in the opposite direction, select the A input.

As will be described later, the end address data LPAD is given from the microcomputer section based on the above-mentioned zero-cross address data ZCRAD, and is 4-bit data that indicates the end address in units of blocks. This block unit end address data LP
In order to convert AD into address units, 8 bits of all "1" are added to the lower order of AD and the result is applied to the B input of the selector 39. Thereby, the end address data LPAD indicates the final address within the block.

The output of the selector 42 is added to the preset data input PRD of the address counter 37. This selector 42 is
In contrast to selector 39 described above.

When the direction instruction signal DIR is "1", that is, when instructing a forward change in address, the initial address data of all 12 bits "O" applied to the A input is selected, and when it is 60'', that is, when instructing a forward change in address, the initial address data is selected. When instructing, the end address data LPAD to be added to the B input is selected.This end address data LPAD also has 8 bits of all "1" added to its lower order to indicate the final address in the block.

Note that the end point address register 40 is preset at the same time as the address counter 37 by the same pulse PRP as the preset pulse PRP applied to the preset control input "PR" of the address counter 37.

Load end point address data from selector 39.

T-flip-flop 4 for generating direction indication signal DIR
1 is sampling mode or various performance modes M
1 to M8, as will be described later.

The generation conditions of the preset pulse PRP for presetting the address counter 37 are also controlled in accordance with the sampling mode or various performance modes M1 to M8, as will be described later.

The AND circuit 36 which controls adding the note clock pulse φ to the count clock input CLK of the address counter 37 is controlled in accordance with the output signal of the flip-flop 43. The state of this flip-flop 43 is controlled as described later in accordance with the sampling mode or various performance modes M1 to M8.

The waveform sample data read from the data memory 21 is input to the 1 multiplier 46, and is multiplied by the envelope waveform data provided from the envelope generator 47. The envelope generator 47 is.

An envelope waveform having a shape set based on attack time data AT, decay time data DT, sustain level data SL, and release time data RT given from the microcomputer section via the interface 26 is converted into key-on pulses KONP, 0KONP, and key-off pulses KOFP. , 0KOFP. As is well known, attack occurs in response to a key-on pulse.
It generates an envelope waveform section that continues with decay and sustain, and generates a release section in response to a key-off pulse. Here, one key-on pulse KONP and key-off pulse KOFP are given based on the normal press of two keys, and the other key-on pulse is 0.
KONP and key-off pulse 0KOFF are provided to immediately and automatically generate the musical tone that has just been sampled.

The waveform sample data whose volume envelope has been controlled by the multiplier 46 is supplied to the digital/analog converter 48, where it is converted into an analog signal, and finally supplied to the sound system 23. Also.

It is also applied to the effect circuit 49 as appropriate, reverb, tremolo,
Musical sound effects such as vibrato are added.

Next, various operations of this electronic musical instrument will be explained with reference to FIGS. 8 to 19.

Figure 8 shows the main routine, first.

In the key scanning process, each company on the keyboard 14 is scanned to detect key presses and key releases. A predetermined process is executed in response to this detection. Here, when a new key press is detected, the key-on event routine shown in FIG. 12 is executed, and when a new key release is detected, the key-off event routine shown in FIG. 13 is executed.

In the sampling control operator scanning process, the operation of each switch of the sampling control operator group 16 is detected, and a predetermined process is executed in response to this detection. here,
When it detects that the sampling switch SMPL has changed from off to on, the sampling event routine in Figure 9 is executed, and when it detects that the override switch 0VRWR has changed from off to on, the override event routine in Figure 10 is executed. do. Also, a beep end pulse BPE given from the timer beep circuit 24 when the beep sound at the start of sampling ends.
ND is detected, and in response to this detection, the timer beep end event routine of FIG. 11 is executed. Furthermore, when sampling of the external sound is completed, the sampling end event routine shown in FIG. 14 is executed in response to a sampling end signal SMPEND given from the tone generator section 20 as described later. Also, reverse switch RVR8, U-turn switch UTRN, loop switch LOOP, echo switch E CHO1 increase switch NC1 decrease switch DEC.

When it is detected that the all cancel switch CANSEL changes from OFF to ON, the 15th to 19th
The reverse event routine, U-turn event routine, loop event routine, echo event routine, increase event routine, decrease event routine, and all-cancel event routine shown in the figure are executed, respectively.

In the envelope control operator scanning process, the operation of each operator of the envelope control operator group 17 is detected,
A predetermined process is executed in response to this detection. Here, the attack time, decay time, sustain level, and release time data set and controlled by the envelope control operator [17] are stored in the attack time buffer ATB, decay time buffer DTB, and sustain level buffer SL.
B and release time buffer RTB.

In the effect control operator scanning process, the operation of each operator of the effect control operator group 18 is detected, and a predetermined process is executed in response to this detection. In the other operator scanning process, the operation of each operator of the other operator group 19 is detected, and a predetermined process is executed in response to this detection.

Normal sampling operation - When performing normal sampling operation, first turn on the sampling switch SMPL. In response to this, the sampling event routine of FIG. 9 starts. Here, the sampling flag SMPFLG is set to “1”,
Other flags 0VWFLG-ECFLG are reset to "0" (step 101). Next, new key code N
A key code of a predetermined reference pitch (for example, A4 pitch) is sent to the tone generator section 20 as KC (step 1).
02), and sends a start trigger signal to the timer beep circuit 24 to generate a beep sound (step 10).
3) In the flowchart, the tone generator section 20 is indicated by TO.

The timer beep circuit 24 emits a beep sound for a predetermined period of time (for example, 300m5) in response to this start trigger signal, and when this time elapses, a beep end pulse BPEN is emitted.
Output D.

Referring to FIG. 6, in the tone generator section 20,
A note clock pulse φ of a reference pitch (A4 tone) is generated from the note clock generation circuit 34 in response to the given new key code NKC. occurs. During the beep sound,
This node clock pulse is now stably generated and preparation for sampling is completed. In this way, the beep sound is 4 samples! ! It plays the role of letting you know when preparations are complete.

The routine of FIG. 11 starts in response to the beep end pulse BPEND. In step 104, it is confirmed that the sampling flag SMPFLG is 111", and the process goes to step 105. Here, the sampling mode signal SMI corresponding to the normal sampling mode is set to "111".
1", and the sampling mode signal SM2 corresponding to the override sampling mode is set to "0" and sent to the tone generator section 20.

In the next step 106, data to be given to the tone generator section 20 is initialized as follows and sent to the tone generator section 20. End address data LP that sets various mode signals M1 to M8 of the performance mode to 0''
Set AD to the value "15" indicating the final block. Attack time data AT, decay time data DT, and release time data RT are each set to rOJ, and sustain level data SL is set to maximum value rMAXJ.

This sets a direct keying type envelope waveform that maintains a constant envelope level from key-on to key-off. With this direct keying type envelope waveform, musical tones are produced at the same volume level as sampled.

In the next step 107, the contents of the attack time buffer ATB, decay time buffer DTB, sustain level buffer SLB, and release time buffer RTB in the microcomputer section are also initialized to those for setting a direct keying type envelope waveform in the same way as above. . In the next step 108, data for various musical tone effects are also initialized to predetermined contents.

On the other hand, after confirming the beep sound, the performer uses the microphone 22 to pick up a desired external sound. Referring to FIG. 6, as mentioned above, the picked up signal is sampled by the analog/digital converter 27,
converted to digital. A rising edge of the sound of the digitally converted waveform sample data is detected by a rising edge detection circuit 31, and a trigger pulse TRG is output in response to the detection of the rising edge of the sound. This trigger pulse TRG is input to an AND circuit 50. “1” of the sampling mode signal SM1 is applied to the other input of the AND circuit 50 via the OR circuit 51, and the output of the AND circuit 50 becomes “1” in synchronization with the trigger pulse TRG, which is the sampling mode signal SM1. It is applied as a start pulse SMPST to the set input S of the flip-flop 43 via the OR circuit 52, and is applied to the preset control input PR of the address counter 37 as a preset pulse PRP via the OR circuit 53, and to the end point address register 40. Given. Further, the sampling start pulse SMPST is inputted to the AND circuit 56 via the OR circuit 54, and the sampling mode signal SMI is inputted to the AND circuit 56 via the OR circuit 55.
is given to the set input S of .

As a result, the direction instruction signal DIR output from the T-flip-flop 41 becomes 1'1'', the selector 42 selects the initial address (all 0's) and presets the address counter 37, and the selector 39 selects the final block. Select the end address LPAD indicating the end point address LPAD and load it into the end point address register 4o.

Address counter 37 is set to count up.

Then, the AND circuit 36 is enabled by the set output 1"1" of the flip-flop 43, and the note clock pulse φ, whose rate corresponds to the A4 tone, is output to the address counter 3.
7 is input.

In this way, in response to the generation of the trigger pulse TRG, the address counter 37 starts counting up the note clock pulse φ1 at a rate corresponding to the A4 tone, and the generated address signal starts from the initial address (all "O"). , end address L)) AD changes in the forward direction with the end point as the end point.

On the other hand, as the sampling mode signal SMI becomes 1'', as described above, a signal obtained by inverting the note clock pulse φ2 is applied from the NAND circuit 44 to the read/write control R/W of the data memory 21, and the data memory 21 , when the leading phase node clock pulse φ1 is "111", the read mode is set, and the clock pulse φ2 to the slow phase node clock pulse φ2 is "It".
When I It, the write mode is entered, and the read-g mode is switched in a time-division manner within the time of one address. However, when the sampling mode signal SMI is 11'',
The sampling mode signal SM2 is "0", the gate 57 for applying the readout signal of the data memory 21 to the adder 28 is closed, and the key-on pulse is for generating envelope waveform data from the envelope generator 47. is not generated (therefore multiplier 46 cuts the read signal of data memory 21), the read is meaningless.

Digital waveform sample data of the external sound output from the analog/digital converter 27 is applied to one input of the adder 28 . The output of the gate 57 is given to the other input of the adder 28, which is 11 as described above.
0 '1, the digital waveform sample data of the external sound simply passes through the adder 28 and is applied to the latch circuit 29. The latch circuit 29 performs a latch operation at the timing of the note clock pulse φ□, which is the write timing. Note that the analog/digital conversion operation in the analog/digital converter 27 is performed at the timing of the advanced note clock pulse φ1.

The output of latch circuit 29 passes through gate 30 and enters data input DT of data memory 21. The gate 30 is controlled by the output of an OR circuit 58 which receives the sampling mode signal SMI and 8M2, and the output of an AND circuit 59 which receives the note clock pulse φ2. As a result, the gate 30 is opened only in the sampling mode (normal sampling mode and override sampling mode) and only when the node clock pulse φ2 is 1'', that is, only at the write timing. In performance modes M1 to M8, the signals SMI and 8M2 are 110", the AND circuit 59 always outputs '0', and the gate 30 is always closed, so if noise is picked up by the microphone 22, You can also cut here.

In this way, the digital waveform sample data of the external sound is
At the write timing, the data is input to the data input DT of the data memory 21 and written to the address specified by the address signal given from the address counter 37.

On the other hand, the waveform sample data output from the analog/digital converter 27 is given to the zero cross detection circuit 32, and as described above, zero crosses are detected in parallel with the write operation. In response to the zero-crossing detection pulse ZCR output from the zero-crossing detection circuit 32, the write address when the zero-crossing is detected is latched in the zero-crossing address latch circuit 33. Zero cross detection pulse Z
Since the CR is generated for each zero cross of the waveform sample data, the zero cross address of the latch circuit 33 is rewritten many times, and the data finally left in the latch circuit 33 is the final zero cross address of the waveform sample data. Therefore, when the sampling is finished,
The final zero-crossing address is already known.

When the write address reaches the final address of the memory 21, the end address LPAD indicating the final address of the final block stored in the end point address register 40 is
The comparator 38 outputs an end pulse END. This end pulse END is input to the AND circuit 60. This AND circuit 60 is enabled by "1" of the sampling mode signal SM1 from the OR circuit 61, so that l(I I
t is from the AND circuit 60 to the OR circuit 62. It is inputted to the reset input R of the flip-flop 43 via the delay flip-flop 63. The delay flip-flop 63 delays the node clock pulse φ□ by one clock. As a result, one clock after the output value reaches the final address, the flip-flop 43 is reset, the AND circuit 36 is closed, and the note clock pulse φ□ is stopped.

In this way, the address counter 37 stops counting. In particular, since no preset operation is performed at this time, the count value is held at the final value.

In this way, in the sampling mode, data memory 2
Writing is performed over the entire address range from the initial address of 1 to the final address.

End pulse END is applied to AND circuit 64. Since this AND circuit 64 is enabled by "1" of the sampling mode signal SMI from the OR circuit 65, the AND circuit 64
This is the sampling end signal SMPE.
It is sent to the microcomputer section as an ND. Further, the zero-cross address data ZCRAD latched in the zero-cross address latch circuit 33 is also sent to the microcomputer section.

Override sampling operation When writing waveform sample data of a newly sampled sound over the sampled sound in the light, turn on the override switch 0VRWR. In response, the override event routine of FIG. 10 is executed. Here, first, override flag 0VWFLG
is set to "1" and other flags are reset to "0" (step 101a), followed by step 102a.
.

The process at step 103a is the same as steps 102 and 103 in FIG. 9, and an A4 key code is set as the new key code NKC, and a timer beep sound is generated.

When the beep ends, the timer beep end event routine of FIG. 11 is executed as described above. here,
In step 104, the sampling flag SMPFLG
is "0", so the determination is NO and the process goes to step 109. In step 109, the sampling mode signal SM
1 is set to "0", 8M2 is set to "1", and sent to the tone generator section 2o.After that, steps 106 and 107 are performed in the same way as in the normal sampling mode.
．． 108 processing is executed.

In this way, in the case of the override sampling mode, the point that the sampling mode signal SMI is "0" and 8M2 is "1" is the opposite of the case in the normal sampling mode, and the other points are the same as in the case of the normal sampling mode. It is.

Referring to FIG. 6, like SMI, the sampling mode signal SM2 is an OR circuit of 45.51°55.58.
61.65, and in this regard, the tone generator section 20 operates in exactly the same manner as in the normal sampling mode described above. The difference is that the signal SM
2 is applied to the control input of gate 57. As a result, the waveform sample data read from the data memory 21 is input to the adder 28 and added to new waveform sample data provided from the analog/digital converter 27.

That is, as mentioned above, from the OR circuit 45 to the NAND circuit 4
4, a signal obtained by inverting the note clock pulse φ2 is applied to the read/write control input R/W of the data memory 21, and the data memory 21 enters the read mode in the first half of one address time, and in the second half. The write mode is entered.The waveform sample data of the previously sampled sound read from the data memory 21 in the first half of one address time passes through the gate 57, which is opened by the signal SM2 being "1", and is added to the adder 28. and added to the newly sampled external sound waveform sample data.The added waveform sample data is added to the timing of the second half of one address time (φ2 is 11
117 timing) in the latch circuit 29,
The data is input to the data memory 21 via the gate 30 and written to the corresponding address.

In this way, data obtained by adding the waveform sample data of the newly sampled sound to the waveform sample data of the already sampled sound is written into the memory 21. Similarly to the above, when the write address reaches the final address, the sampling end signal SMP is output from the AND circuit 64.
END is generated. Further, as described above, the last zero-crossing address of the newly sampled waveform sample data is finally latched by the latch circuit 33.

Crossover of Sampling Rates The writing rate of waveform sample data in the normal sampling mode and the override sampling mode is not limited to the standard pitch (A4 tone), but can be changed as appropriate by pressing keys on the keyboard 14.

When a key of a desired pitch desired to be set as the sampling rate is pressed on the keyboard 14, the microcomputer section detects the new pressed key and executes the key-on event routine shown in FIG. 12. In step 110, the key code related to the new key press is stored in the new key code register NKE.
Store in Y.

In the next step 111, the normal sampling flag S
MPFLG or override sampling flag 0
Check whether VWFLG is "1". If YES, that is, either sampling mode, step 112
and input the contents of the second key code register NKEY to the tone generator section 20 as the new key code NKC.
Send to. Based on this, the tone generator section 20
The node clock pulse φ generated from the note clock generation circuit 34 of. (that is, φ8.φ2) corresponds to the pitch specified on the keyboard 14.

In this way, the desired external sound may be sampled after changing the sampling rate to one corresponding to the desired pitch.

Example of Use of Override Sampling Various overwriting modes are possible depending on the wishes of the performer, but as an example, the following harmony sampling will be explained.

For example, in the case of a C major chord, the sampling rate is first set to the C4 note, and a sound signal of the C4 note of a desired tone is sampled externally. Next, the sampling rate is set to E4 sound, and the same C4 sound signal as above is input from the outside to perform override 1-sampling. Next, set the sampling rate to C4 sound and input the same C4 sound signal as above from the outside to override.
sample. In this way, C4, E4. The sum of the waveform sample data of the three tones of pitch G4 is stored in the data memory 21. In this case, by reading out the waveform sample data from the data memory 21 at a desired pitch rate corresponding to the pressed key, a musical tone signal of a major chord having the pressed key as the root note can be generated.

In this way, for example, override sampling is useful when attempting to play chords with simple key press operations. For example, if you want to divide the R keyboard 14 into key ranges and play chords in some of the key ranges, the data memory 21 can be read in response to key presses in the chord performance key range. You can play simple chords like this.

SAMPLING END A・NO As described above, when the sampling end signal SMPEND is generated at the end of writing the external sound waveform sample data, the sampling end event routine shown in FIG. 14 is executed.

Here, first, the zero-crossing address data ZCRAD latched in the zero-crossing address latch circuit 33 of the tone generator section 20 is taken into the zero-crossing address buffer ZCRADB in the microcomputer section (step 113).

As described above, this data ZCRAD indicates the address where the last sample data of the sampled sound is stored in the memory 21.

In the next step 114, it is checked whether the override sampling flag 0VWFLG is 1", and if No, that is, normal sampling mode, the process proceeds to step 115, and the zero cross address buffer Z CRA D B
The contents of are stored in the end address buffer LPADB. In this way, the last zero cross address data of the waveform sample data is stored in the buffer L as the end address data.
Stored in PADB.

Next, the sampling flag SMPFLG and 0VWFL
Reset G to 110'' (step 116),
The content of the signal sent to the tone generator section 20 is
SMI and 8M2 are both “O”, Ml is “1”, M2~M
8 to “□ II” and the buffer LPADH
The content of is sent as end address data LPAD (step 117).

And key-on pulse 0KONP for parrot sound.
is sent to the tone generator section 20 (step 11
．． 8) This key-on pulse 0KONP is used to immediately generate a musical tone corresponding to the sampled waveform sample data immediately after sampling, and to confirm its contents.

Override Sampling 7 o'clock Ring When override sampling is completed, step 114 in FIG. (indicating the final zero-crossing address of) is smaller than the contents of the zero-crossing address buffer ZCRADB (which indicates the final zero-crossing address of the waveform sample data sampled this time). If YES, the process advances to step 115 and the contents of the buffer LPADH are rewritten to the current final zero-crossing address data. If NO, the process goes to step 116 via step 120 without performing step 115.

In this manner, in the case of overwriting, the final zero-crossing address of the data with the longest address length among the plurality of overwritten external sound sampling data is stored as end address data in the buffer LPADB.

Note that in step 120, the end address buffer,
Set the contents of LPADB to zero-cross address buffer ZCRADB. This is the final zero-sill address of the data sampled this time among the overwritten external sound sampling data (this is the address of the previous step 1).
(stored in buffers ZCR and ADB at step 19) is smaller than the final zero-crossing address of the previously sampled data, so from the perspective of the entire overwritten data, it does not specify the final zero-crossing address. The buffer LPADB identifies the true final zero-crossing address from the entire overwritten waveform sample data.
This is to store the contents of the buffer ZCRADB in the buffer ZCRADB. As will be described later, during all cancel processing, the contents of the zero-cross address buffer ZCRADB are returned to the end address buffer LPADB, and the contents of the zero-cross address buffer ZCRADB are returned to the end address buffer LPADB.
Since it is necessary to return the contents of B to the true final zero-crossing address, it is necessary to store the true final zero-crossing address in the overwritten waveform in the buffer ZCRADB. For this purpose, the process of step 120 is inserted.

When the writing of the waveform sample data sampled from the outside of the sampling device is completed, step 11 in FIG.
Key-on pulse 0KONP for parrot sound by 8
is generated automatically.

Referring to FIG. 6, in the tone generator section 20,
This parrot sounding key-on pulse 0KONP is input to the envelope generator 47 via the OR circuit 66, and is also input to the OR circuits 52, 53, 54 and the set manual S of the flip-flop 67.

Furthermore, the performance mode signal M1 is set to "1" by the processing in step 117 of the sampling end event routine (FIG. 14) described above, and this signal M1 is sent to the OR circuits 55, 61, and 68 of the tone generator section 20. is input.

The condition of the AND circuit 56 is established by the key-on pulse 0KONP and the signal M1 being "1", and the T-flip-flop 4
1 is set, and the direction indication signal DIR becomes "1".
Also, in response to the key-on pulse OKONP, the OR circuit 53
The P1 no set pulse PRP is output from. As a result, the selector 42 selects the initial address data (all “0”).
) is selected and preset in the address counter 37, and end address data LPAD is selected by the selector 39 and loaded into the register 40. Also.

Flip-flop 4 according to key-on pulse 0KONP
3 is set, and the address counter 37 starts counting. In this case, since the new key code NKC has not been changed, the note clock pulse φ1 at the same rate as when writing is counted, and the address counter 37 counts up, starting from the initial address and reaching the end address LPAD. The address signal changes in the forward direction from the end point.

In the data memory 21, both signals SMI and SM2 are ``0''
By being in the constant read mode.

In this way, the waveform sample data that was just written is read from the beginning.

On the other hand, the envelope generator 47 generates a key-on pulse of 0K.
Envelope waveform data is generated according to ONP.

In this case, each data AT, D for envelope waveform setting
As mentioned above, T, SL, and RT are initially set to the contents that set the direct keying type envelope waveform in step 106 of the timer beep end event routine (Figure 11), so they are set at a constant level from key-on to key-off. Envelope waveform data is generated. As a result, the sampled waveform sample data is produced at the same volume level. In this way, the state of the sampled external sound signal can be immediately confirmed. When the read address reaches a value corresponding to the end address data LPAD, the comparator 38 generates an end pulse END, which is applied to the AND circuit 69. Since the other input of this AND circuit 69 is given the output "1" of the flip-flop 67 set by the key-on pulse 0KONP, the output of the AND circuit 69 becomes "1" in response to the end pulse END, and this It is applied to the envelope generator 47 via the OR circuit 70 as a key-off pulse OK○FP for parroting sound. Due to the key-off pulse ○KOFF automatically created in this way, the direct keying type envelope waveform data generated from the envelope generator 47 falls to level 0. In this way, the automatic pronunciation of parrots ends. In addition,
The flip-flop 67 is reset by a signal obtained by delaying the key-off pulse ○KOFF by a delay flip-flop 88.

Determination of performance mode The aforementioned eight performance modes M1 to M8 (see FIG. 3) are determined according to the operation of each switch RVRS, UTRN, and LOOP.

When the reverse switch RVR5 is turned on, the reverse on event routine shown in FIG. 15 is executed, and the reverse flag RVFLG is changed from "0" to "1" or 111 I
It is inverted from T to 71011 (step 121). Next, go to step 124.

When the U-turn switch UTRN is turned on, the U-turn event routine shown in FIG. 15 is executed, and the U-turn flag UTFLG is changed from 0 to 1 or from 1 to 0.
(step 122). Next, go to step 124.

When the loop switch LOOP is turned on, the loop event routine shown in FIG. 15 is executed, and the loop flag LPF is
LG from 0” to “1” or Ll I IT to “0”
” (step 123).

Next, go to step 124 (.

In step 124, each of the above flags RVFLG.

Based on the contents of UTFLG and LPFLG, performance modes M1 to M8 are determined according to the table below.

Table 1 Next, in step 125, mode signals M1 to M8 having contents corresponding to the determined performance mode are sent to the tone generator section.
Send to 0. That is, only one mode signal determined according to Table 1 above is 1"1", and the other mode signals are set to '0'.

Key-on/off processing in mode To read out the waveform sample data stored in the data memory 21 and generate sound, press a desired key on the keyboard 14.

When a key is pressed, the key-on event routine shown in FIG. 12 is executed, and the key code of the pressed key is taken into the new key code register NKEY (step 110). In the next step 111, the sampling flag SMPFLG is set in the performance mode. , 0VWFLG are "0", the determination is No, and the process goes to step 126. Step 1
In step 26, a predetermined pronunciation assignment process is performed, which is a single note priority process since the single note priority pronunciation method is adopted in this embodiment.In the 0th order step 127, a new key press is performed according to the result of the single note priority process in the previous step. It is judged whether or not it is necessary to produce the musical tone related to the note, and if there is no need to produce it, the process goes to return, but if it is necessary, it goes to step 128. In step 128, the register NK is used to allocate the new key code.
Store the second key code of EY in the register KCODE.0 In the next step 12 white, the tone generator uses the key code of the register KCODE (that is, the key code related to the new pressed key that has been newly assigned to generate the sound) as the new key code NKC. 20. Further step 13
At 0, the key-on pulse KONP is sent to the tone generator section 20.

When the pressed key is released, the key-off event routine shown in FIG. 13 is executed. The key code of the newly amned key is taken into the second key code register NKEY (step 131), and the sampling flag SMPFL is set.
Check whether G, 0VWFLG is “1” (step 1
32) If the answer is NO, that is, the performance mode is set, the process proceeds to step 133, and it is checked whether the released key is the key currently being sounded (NKEY=KCODE). If so, a key-off pulse KOFF is sent to the tone generator section 20.

The operation of the tone gelator section 20 in each of the performance modes M1 to M8 will be explained by Sumiji Homono U1.

(Common explanation for each mode) In response to a key press, the key code of the pressed key is given as the new key code NKC as described above, and based on this, the note clock generation circuit 34 generates the note clock pulse φ of the pressed key. is generated. Further, the flip-flop 43 is set by the key-on pulse KONP via the OR circuit 52, and the note clock pulse φ□ is inputted to the count input CLK of the address counter 37, and counting of address signals is started.

The contents of the direction indicating signal DIR generated from the T-flip-flop 41 differ depending on the states of the signals M1 to M8 corresponding to each performance mode, as will be described later. In response to this, the counting direction of the address counter 37 is determined, the address signal changes in response to the node clock pulse φ1, and waveform sample data is read out from the data memory 21.

Furthermore, the key-on pulse KONP and key-off pulse KOF generated in response to key presses and key releases as described above are also used.
P passes through OR circuit 66.70 to envelope generator 4
7, and envelope waveform data is generated accordingly. The volume envelope of the waveform sample data read from the data memory 21 is controlled in accordance with this envelope waveform data, and the sound is generated. Note that the envelope waveform setting data AT, DT, SL, and RT are set by the envelope operator group 17, and the waveform sample data is controlled by the envelope waveform of an appropriate shape set accordingly. The volume envelope is controlled.

Note that the processing performed when the end pulse END is generated from the comparator 38 differs depending on the state of the signals M1 to M8 corresponding to each performance mode, as will be described later.

(Mode M1: Normal performance) When mode signal M1 is "1", OR circuit 54.55
key-on pulse KONP and signal M1 given via
is “1”, the condition of the AND circuit 56 is established, and T-
Flip-flop 41 is set and direction indication signal DI
R becomes It I II.

Further, a preset pulse PRP is generated from the OR circuit 53 in response to the key-on pulse KONP.

As a result, the waveform sample data is read out only once in the forward direction from the data memory 21, starting from the initial address (all it OII) and ending at the end address LPAD, as in the case of the above-mentioned parrot sound generation.

When the read address reaches the end address LPAD, the comparator 38 generates an end pulse E N D. This end pulse END is generated by AND circuits 60, 71,
Join 72 and 73. A signal M1 of "1" is applied to the other inputs of the AND circuit 60 via an OR circuit 61, and in response to the end pulse END, the AND circuit 60. OR circuit 62. “1” is applied to the reset input R of the flip-flop 43 via the delay flip-flop 63.

This allows the read address to be changed to Entonadres LPAD.
When the address counter 37 reaches , the address counter 37 stops counting. The other AND circuits 71, 72, 73 receive the signal M1
It does not work when is 1".

In this manner, in the performance mode M1, that is, the normal memory read mode, the data memory 21 is read out only once in the forward direction to generate sound.

(Mode M2: Reverse) When mode signal M2 is '1'', OR circuit 54.74
key-on pulse KONP and signal M2 given via
“1” satisfies the condition of the AND circuit 75, and T-
Resetting flip-flop 41 manually R to 141 II
is given. Due to this.

The T-flip-prop 41 is reset and the direction indication signal DIR becomes ri O''.
110 II, the selector 42 selects the end address data LPAD, and the selector 39 selects the initial address data (all 1'0'').
A preset pulse PRP is generated from the OR circuit 53 in response to the key-on pulse KONP. As a result, contrary to the mode M1 described above, data memory 21 starts from the end address LPAD and ends from the initial address.
The waveform sample data is read only once in the reverse direction.

When the read address reaches the initial address, comparator 3
An end pulse END is generated from 8.

This end pulse END is generated by the AND circuits 60 and 71.
．． Join 72 and 73. The other inputs of the AND circuit 60 are given II II II of the signal M2 via the OR circuit 61, and the AND circuit 60 receives the signal M2 in response to the end pulse END.
0. OR circuit 62. “1” is applied to the reset input R of the flip-flop 43 via the delay flip-flop 63. Thereby, when the read address reaches the initial address, the address counter 37 stops counting. The other AND circuits 71, 72, and 73 do not operate when the signal M2 is "1".

In this way, in the performance mode M2, that is, the "reverse" mode, the data memory 21 is read out only once in the reverse direction to generate sound.

(Mode M3: Loop) When mode signal M3 is “1”, OR circuit 54.55
key-on pulse KONP and signal M3 given via
is “1”, the condition of the AND circuit 56 is established, and T-
Flip-flop 41 is set and direction indication signal DI
R becomes Pa1''.

Further, a preset pulse PRP is generated from the OR circuit 53 in response to the key-on pulse KONP.

As a result, as in mode M1, waveform sample data is read out from the data memory 21 in the forward direction starting from the initial address and ending at the end address LPAD.

When the read address reaches the end address LPAD, the comparator 38 generates an end pulse END. This end pulse END is applied to the AND circuit 60, but
Since the mode signals M3 to M8 are not applied to the OR circuit 61, the end pulse END does not reset the flip-flop 43 and the address counter 37 does not stop counting.

On the other hand, OR circuit 6 is activated by It O$1 of signals ML and M2.
The output of the inverter 8 becomes "0", the inverter output of the inverter 76 becomes "1", and the output of the AND circuit 72 becomes "1" in response to the end pulse E N D.

The output “1” of the AND circuit 72 is applied to the AND circuit 77. The output signal of inverter 83, which is the other input of AND circuit 77, is signal M4. When M7 is “0”, it is always “1”, so the AND circuit 77
The following conditions are satisfied, and a preset pulse PRP is generated via the delay flip-flop 78 and the OR circuit 53 in response to the output signal "1" of the AND circuit 77.

On the other hand, the end pulse END is also applied to the AND circuit 71, but since the output of the OR circuit 79 is II_Olj, the condition of the AND circuit 71 is not satisfied and the state of the T-flip-flop 41 does not change. Therefore, direction signal DIR
remains "1" and does not change, and in response to the preset pulse PRP generated as described above when the read address reaches the end address LPAD, the initial address data (all "0") is stored in the address counter 37 again. is preset, and end address data LPAD is loaded into register 40. Also, address counter 3
7 remains in up count mode. In this way, the waveform sample data is read out from the data memory 21 again in the forward direction starting from the initial address and ending at the end address LPAD.

In this way, in the case of "loop", the waveform sample data in the data memory 21 is repeatedly read out in the forward direction, and a musical tone based on the sampled external sound is repeatedly produced many times. The sound generation can be ended by releasing the pressed key and attenuating the volume control envelope.

(Mode M4: U turn) When mode signal M4 is “1”, OR circuit 54.55
key-on pulse KONP and signal M4 given via
is “1”, the condition of the AND circuit 56 is established, and T-
Flip-flop 41 is set and direction indication signal DI
R becomes "1".

Further, a preset pulse PRP is generated from the OR circuit 53 in response to the key-on pulse KONP.

As a result, similarly to mode M1, waveform sample data is read out from the data memory 21 in the forward direction starting from the initial address and ending at the end address LPAD.

When the read address reaches the end address LPAD, the comparator 38 generates an end pulse END. This end pulse END is applied to the AND circuit 60, but
Since mode signals M3 to M8 are not applied to the OR circuit 61, the output of the AND circuit 60 remains at "0". Further, the end pulse END is applied to the AND circuit 73, but this output is also "0", that is, the signal M4 is "
If the direction instruction signal DIR is "1" (that is, the address is changing in the forward direction), the AND circuit 85 inputs the signal M4 and an inverted signal of the direction instruction signal DIR.
The output of the AND circuit 86 to which the signal M7 and the signal DIR are input is also "O++", the signal applied from the OR circuit 87 to the AND circuit 73 is "0", and the conditions of the AND circuit 73 are Does not hold. Therefore, the AND circuit 60
, 73, the output of the OR circuit 62 is "0", and the flip-flop 43 is not reset by the end pulse END generated during forward counting operation, and the address counter 37 does not stop counting. .

On the other hand, OR circuit 6
The output of the inverter 76 becomes "1", and the output of the AND circuit 72 becomes "1" in response to the end pulse END.

The output “1” of the AND circuit 72 is applied to the AND circuit 77. When signal M4 is '1', direction indication signal DIR is '1'
(that is, the address is changing in the forward direction), the output of the AND circuit 8o inputting the signal M4 and the inverted signal of the direction instruction signal DIR is IQ 71, the signal M7 and the signal D
The output of the AND circuit 81 to which the IR is input is also "0", and the OR circuit 8 to which the output of the AND circuit 80 and 81 is input is also "0".
The output of 2 is lQIT, which is inverted by inverter 8.
The output of 3 is "1", and this is input to the AND circuit 7.
The output of 7 becomes "1". Therefore, depending on the output signal 111 PF of the AND circuit 77, the delay flip-flop 78
, a preset pulse PRP is generated via an OR circuit 53.

On the other hand, the end pulse END is also applied to the AND circuit 71, and since the output of the OR circuit 79 is "1" due to the signal M4 being "1", the condition of the AND circuit 71 is satisfied, and the T- "1" is added to the count C of the flip-flop 41, and the state of the T-flip-flop 41 is reversed from "1" to 1'0. Therefore, the direction indication signal DIR becomes "0". As a result, the selector 42 selects the end address data LPAD, and the selector 39 selects the initial address data (all "
Orp) and are preset into the counter 37 and loaded into the register 40 by the preset pulse PRP generated as described above. In this way, contrary to the previous time, starting from the end address LPAD,
Waveform sample data is read out from the data memory 21 in the reverse direction with the initial address as the end point.

When the read address reaches the initial address, comparator 3
An end pulse END is generated from 8.

This time, the direction instruction signal DIR is "0" and its inverted signal is "1", and the conditions of AND circuits 80 and 85 are satisfied.As a result, the output of AND circuit 73 becomes "1", and the flip-flop 43 is reset.This causes the read address to become the initial address (all ``0'').
When the address counter 37 reaches , the address counter 37 stops counting. Further, the output of the AND circuit 77 becomes "0" due to the output "I It" of the AND circuit 80, and the preset pulse PRP is no longer generated.

In this manner, in the case of a "U turn", the waveform sample data in the data memory 21 is read out once in the forward direction, and then the waveform sample data in the data memory 21 is turned around in the reverse direction and read out once.

(Mode M5: Reverse loop) When mode signal M5 is “1”, OR circuit 54.74
○NP and signal M5 to the key-on pulse given through
“1” satisfies the condition of the AND circuit 75, and T-
111" is applied to the reset human power R of the flip-flop 41. As a result, the T-flip-flop 41 is reset, and the direction indication signal DIR becomes 110++. By turning on the direction indication signal DIR, the above-mentioned mode M2 is set. As in the case of , waveform sample data is read out from the data memory 21 in the reverse direction starting from the end address LPAD and ending at the initial address.

When the read address reaches the initial address, comparator 3
An end pulse END is generated from 8.

As in mode M3 (loop), the flip-flop 43 is not reset by the end pulse END, and the address counter 37 does not stop counting. Further, the condition of the AND circuit 77 is satisfied in response to the end pulse END, and the preset pulse PRP is generated. Further, even if the end pulse END occurs, the condition of the AND circuit 71 is not satisfied, and the state of the T-flip-flop 41 does not change. Therefore, the direction instruction signal DIR remains at "0" and does not change, and the end address data LPAD is again sent to the address counter 37 in response to the preset pulse PRP generated as described above when the read address reaches the initial address. is preset, and initial address data (all "0") is loaded into the register 40.

Further, the address counter 37 remains in the down count mode. In this way, the waveform sample data is read out again from the data memory 21 in the reverse direction starting from the end address LPAD and ending at the initial address.

In this way, in the case of "reverse loop", the waveform sample data in the data memory 21 is repeatedly read out in the reverse direction, and musical tones obtained by rearranging the sampled external sounds in the reverse direction in time are repeatedly produced. . This sound generation can be ended by releasing the pressed key and attenuating the volume control envelope.

(Mode M6: U-turn loop) When mode signal M6 is "'1", OR circuit 54.5
key-on pulse KONP and signal M given via 5
6 is “1”, the condition of the AND circuit 56 is established, and T
- Flip-flop 41 is set and direction indicating signal D
IR becomes Pa1'''.

Further, a preset pulse PRP is generated from the OR circuit 53 in response to the key-on pulse KONP.

As a result, similarly to mode M1, waveform sample data is read out from the data memory 21 in the forward direction starting from the initial address and ending at the end address LPAD.

When the read address reaches the end address LPAD, the comparator 38 generates an end pulse END. When the signal M6 is "1", the conditions of the AND circuit 73 are not satisfied, the flip-flop 43 is not reset by the end pulse END, and the count of the address counter 37 is not stopped. Condition 77 is satisfied and the preset pulse PRP
is generated. Also, since the output of the OR circuit 79 is '1' due to the signal M6 being '1', the end pulse END
As a result, the condition of the AND circuit 71 is satisfied, and "1" is added to the count input C of the T-flip-flop 41 via the delay flip-flop 84, and the state of the T-flip-flop 41 is reversed from "1" to "0". Therefore, the direction instruction signal DIR becomes "0".As a result, the counting direction of the address counter 37 is reversed from the previous one, starting from the end address LPAD and ending at the initial address from the data memory 21 in the opposite direction. The waveform sample data is read out.

When the read address reaches the initial address, an end pulse END is generated, and as described above, the AND circuit 71
and 77 are satisfied, the preset pulse PRP is generated, and the state of the T-flip-flop 41 becomes "0".
The direction indication signal DIR is inverted from "1" to "1". As a result, the counting direction of the address counter 37 returns to the forward direction, and the waveform sample data is read out from the data memory 21 in the forward direction starting from the initial address and ending at the end address LPAD. Then, an end pulse END is generated. Then, the counting direction of the address counter 37 is reversed.

Thereafter, similarly, every time the end pulse END is generated,
Repeat U-turn reading.

In this way, in the case of "U-turn loop", after reading the waveform sample data in the data memory 21 in the forward direction,
A U-turn reading operation in which the waveform sample data in the data memory 21 is read out by turning it in the opposite direction is repeated many times.

(Mode M7: U-turn/reverse) When mode signal M7 is “1”, OR circuit 54.74
key-on pulse KONP and signal M7 given via
1'', the condition of the AND circuit 75 is satisfied, the T-flip-flop 41 is reset, and the direction indication signal DI
R becomes 410".

By "O" of this direction instruction signal DIR, the end address L
Waveform sample data is read from the data memory 21 in the reverse direction starting from PAD and ending at the initial address.

When the read address reaches the initial address, comparator 3
An end pulse END is generated from 8.

This end pulse END is applied to the AND circuit 73, and its output is "0". In other words, the signal M7 is '1''
If the direction instruction signal DIR is "0" (that is, the address is changing in the opposite direction), the output of the AND circuit 86 inputting the signal M7 and the direction instruction signal DIR is "0".
The output of the AND circuit 85 is also "0", the signal applied from the OR circuit 87 to the AND circuit 73 is "0", and the condition of the AND circuit 73 is not satisfied. Therefore, in mode M7, the count operation is performed in the opposite direction. The flip-flop 43 is not reset by the end pulse END generated during this period, and the address counter 37 does not stop counting.

Moreover, “1” of the signal M7 and “OP” of the direction instruction signal DIR
j, the output of the AND circuit 81 and the OR circuit 82 becomes 0"
In response to the end pulse END, the output of the AND circuit 77 becomes "1", and the delay flip-flop 78 . A preset pulse PRP is generated via an OR circuit 53.

On the other hand, the end pulse END is also applied to the AND circuit 71, and the output of the OR circuit 79 is "1" due to it 1 ty of the signal M7, so the conditions of the AND circuit 71 are satisfied.
"1" is added to the count C of the T-flip-flop 41 via the delay flip-flop 84, and the state of the T-flip-flop 41 is reversed from "0" to "1".

Therefore, the direction instruction signal DIR becomes "1". As a result, the selector 42 selects the initial address data (all “
0''), the selector 39 selects the end address data LPAD, and these are preset in the counter 37 and loaded into the register 40 by the preset pulse PRP generated as described above. On the contrary, waveform sample data is read out from the data memory 21 in the forward direction starting from the initial address and ending at the end address LPAD.

When the read address reaches the end address LPAD, the comparator 38 generates an end pulse END. This time, the direction instruction signal DIR is "1" and the conditions of AND circuits 81 and 86 are satisfied.

As a result, the output of the AND circuit 73 becomes 1'', and the flip-flop 43 is reset.As a result, when the read address reaches the end address LPAD,
The address counter 37 stops counting. Furthermore, the output It ill of the AND circuit 81 causes the AND circuit 77
The output of P is O''', and the preset pulse PRP is no longer generated.

In this way, in the case of "U-turn reverse", the waveform sample data in the data memory 21 is read out once in the reverse direction, and then the waveform sample data in the data memory 21 is turned around in the forward direction and read out once.

As a result, a new performance effect is realized in which a musical tone in which the sampled external sounds are rearranged temporally backward is produced once, and then the sampled tone is rearranged temporally in the forward direction and produced once again. be able to.

(Mode M8: U-turn reverse loop) When the mode signal M8 is "1", the key-on pulse KONP given via the OR circuit 54.74 and the "1" of the signal M8
As a result, the condition of the AND circuit 75 is satisfied, the T-flip-flop 41 is reset, and the direction indication signal DIR becomes “
It becomes 071.

With this direction instruction signal DIR being "0", the waveform sample data is sent from the data memory 21 in the reverse direction starting from the end address LPAD and ending at the initial address, as in the above-mentioned mode M7 (U-turn/reverse). Read out.

When the read address reaches the initial address, comparator 3
An end pulse END is generated from 8.

When the signal M8 is "1", the condition of the AND circuit 73 is not satisfied, the flip-flop 43 is not reset by the end pulse END, and the address counter 37 does not stop counting. Furthermore, the condition of the AND circuit 77 is satisfied by the end pulse END, and the preset pulse PR
P is generated.

Furthermore, the output of the OR circuit 79 is set to 1 due to the signal M8 being “1”.
1111, the condition of the AND circuit 71 is satisfied by the end pulse END, and the delay flip-flop 84
"1" is added to the count input C of the T-flip-flop 41 via the T-flip-flop 41, and the state of the T-flip-flop 41 is inverted from 0" to "1". Therefore, the direction indication signal DI
R becomes '1''. As a result, the address counter 37
The counting direction is reversed from the previous time, and the waveform sample data is read out from the data memory 21 in the forward direction starting from the initial address (all "O") and ending at the end address LPAD.

When the read address reaches the end address LPAD, the end pulse END is generated, and the conditions of the AND circuits 71 and 77 are satisfied as described above, and the preset pulse P is generated.
RP is generated, and the state of the T-flip-flop 41 is inverted from "P1" to "ON" and the direction indicating signal DIR is generated.
becomes “0”.

As a result, the counting direction of the address counter 37 returns to the opposite direction, and the waveform sample data is read out from the data memory 21 in the reverse direction starting from the end address LPAD and ending at the initial address. Next, when the end pulse END is generated, the counting direction of the address counter 37 is set to the forward direction.

Thereafter, similarly, every time the end pulse END is generated,
Repeat the "U-turn/reverse" reading.

In this way, in the case of "U-turn reverse loop",
After reading out the waveform sample data in the data memory 21 in the reverse direction, "U-turn reverse" reading is repeated many times, in which the waveform sample data in the data memory 21 is turned around and read out in the forward direction.

As a result, after a musical tone in which the sampled external sounds are rearranged temporally backward is generated once, the sampled tone is rearranged temporally forward and generated once again. "
You can create new performance effects by repeating ``U-Turn Reverse'' many times. This sound generation can be ended by pressing the pressed key @II and attenuating the volume control envelope.

8 Processing of the end address By the process of step 115 in FIG. 14 described above, the end address buffer LPAD in the microcomputer section is
The end address data stored in B is the address that stores the data of the final zero cross portion of the sampled original waveform, that is, the final zero cross address (-
For example, an address in block units) is initially set.

End address data LPAD used by the tone generator section 20 in each of the above-mentioned performance modes M1 to M8
is the data stored in this end address buffer LPADB. Assuming that the initial settings remain as described above, the aforementioned end address data LPAD is the last zero-crossing address itself in the sampled original waveform (that is, the zero-crossing address buffer ZCRAD).
data stored in B).

In this way, when the final zero cross address data itself in the sampled original waveform is used as the end address data LPAD, musical tones corresponding to all the original waveforms sampled from the outside are produced in the performance mode. However, if the end address data LPAD used by the tone generator section 20 in each of the above-mentioned performance modes M1 to M8 is not limited to the final zero cross address data itself in the sampled original waveform, but can be changed as appropriate, the performance effect can be improved. can be further increased.

To that end, changing this end address data LPAD requires an increment switch INC and a decrement switch DE
This can be done by operating C. In this embodiment, the mode is a mode in which sampled waveform data is repeatedly read out and produced, that is, a "loop" or "reverse loop."

Such change processing is possible in the case of a "U-turn loop" or "U-turn reverse loop." This is because during such repeated performances, it is quite effective to control the length of one repetition cycle by adjusting the end address. However, the end address data L p n is not limited to this, and can also be used in other performance modes.
It may also be possible to increase or decrease D.

When the increment switch INC is turned on, the increment event routine shown in FIG. 17 is executed. Here, step 13
5, it is checked whether the loop flag LPFLG is It I It, and if YES, the process goes to step 136, but N
If o, go to return. This is the above-mentioned “loop” related performance mode M3. M5, M6. This is to perform this control at M8. In step 136, the contents of the end address buffer LPADB are incremented by one. Note that if the contents of the buffer LPADB reach the maximum value in this increment operation, the maximum value is held.

Since the data stored in the above-described passing buffer LPADH is in units of blocks, this increase is also performed in units of blocks. In this case, the maximum value is "15". In the next step 137, the contents of the end address buffer LPADB are sent to the tone generator section 20 as end address data LPAD.

When the decrease switch DEC is turned on, the decrease event routine shown in FIG. 18 is executed. Step 135a here
, 136a, and 137a are each step 1 in FIG.
The process is almost the same as that of steps 35, 136, and 137, and the difference is that in step 136, the end address buffer LP
While the contents of ADB were increased by 1, step 136
The only point in a is that the contents of this buffer LPADB are decreased by 1.

Thus, the end address buffer LPA, DB
By increasing or decreasing the contents of , the value of the end address data LPAD used by the tone generator section 20 can be increased or decreased.

By increasing/decreasing the value of the end address data LPAD in this way, it is possible to change and adjust the end point address in forward reading and the starting point address in backward reading, and the starting point of repetition in loop performance. You can change the address freely. Therefore, the mode of repeated reading can be freely changed by adjusting the increase/decrease change of the end address data LPAD.

For example, if noise is included in the waveform sample data stored at an address before the final address of the waveform sample data, the end address data LPA
By decreasing the value of D and adjusting the address closer to the front, it is possible to prevent addresses containing noise from falling within the range of addresses to be read from the data memory 21 during performance. You can cut the pronunciation of the sample data part.

Alternatively, by increasing the value of the end address data LPAD and adjusting it to an address beyond the final address of the waveform sample data, the data memory
The range of addresses to be read from 1 can be expanded to addresses where waveform sample data is not actually stored, and by repeatedly reading in this expanded address range, you can consciously read out data at the joints of repeated reading. It is also possible to create a special performance effect in which the sound is repeated intermittently by creating a silent section of an appropriate length.

Note that the end address buffer LPADB is changed by the increase switch INC and decrease switch DEC.
is the contents of the zero-crossing address buffer ZCRAD
The original final zero-crossing address in the original waveform stored in B is not changed.

This is used to return the contents of the end address buffer LPADB to the original final zero-crossing address in the original waveform during all cancel processing to be described later.

When the echo switch ECHO is turned on, the echo event routine shown in FIG. 16 is executed. In step 138, the echo flag ECFLG is changed from "110" to "1".
Or invert from "1n to 110". Step 139
Then, check whether the echo flag ECFLG is "1", and if it is 1, go to step 140 and save the contents of the loop flag LPFLG to the loop flag buffer LPFLGB.
, and then sets the loop flag LP"FLG to "1". In this way, the performance mode can be set to a mode related to "loop", that is, "loop" or "reverse loop".
, “U-turn loop” or “U-turn reverse
Loop” automatically.

In the next steps 124a and L25a, the same processing as steps 124 and 125 in FIG. 15 is performed, and the performance mode is set to M.
Decide on one from 1 to M8. However, in this case, the loop flag LPFLG is set to "1", so "
Loop” related performance mode M3. M5. M6. It is always determined to be one of M8.

Next, in step 141, the release time buffer RT
The contents of B are stored in the release time storage buffer RTBUF, and in step 142, the contents of the release time buffer RTBUF are stored in the release time storage buffer RTBUF.
Set the contents of B to the maximum value MAX. Then, in step 143, the contents of the release time buffer RTB are sent to the tone generator section 20 as release time data R.
Send as T.

As a result, the release time of the envelope waveform data generated by the envelope generator 47 is set to be the longest, and the first generated musical tone attenuates extremely slowly after the key is released. Moreover, the performance mode is “loop” related mode M
3. M5. M6. M8, the waveform sample data stored in the data memory 21 is repeatedly read out in the forward or reverse direction, or alternately switching between the forward and reverse directions, and the corresponding musical tone becomes gradually smaller. It is repeatedly sounded at the volume level.Since the waveform sample data that is repeatedly read out is a sample of an external sound, it generally has its own amplitude envelope extending from the rise to the fall of the sound.Therefore, It is possible to achieve an echo-like effect in which a sound with an amplitude envelope ranging from the rise to the fall of the sound is repeated many times, and the volume gradually attenuates.Moreover, it is different from a simple conventional echo. The point is "loop" related performance mode M3. As a result of the sound generation control by MS, M6 and M8, sounds may be pronounced in the opposite direction to their original chronological order, may be pronounced according to their original chronological order, or may be pronounced alternately in a combination thereof. Furthermore, by combining this with the above-mentioned end address increase/decrease adjustment control, it is possible to realize a free echo effect that was completely absent in the past.

When the echo flag ECFLG becomes “0”, step 1
By returning the contents of the loop flag buffer LPFLGB to the loop flag LPFLG through the process of 44, the contents of the loop flag LPFLG are returned to the state before applying the echo effect. In the next steps 124b and 125b,
Perform the same processing as steps 124 and 125 in FIG.
The performance mode is determined to be one of M1 to M8. In the next step 145, the release time storage buffer RTBU
By returning the contents of F to the release time buffer RTB, the contents of the release time buffer RTB are returned to the state before the echo effect was applied.

All cancel processing Cancels all or predetermined data set, selected, changed, or adjusted on the operation panel section 15 in relation to the sampled waveform sample data, and cancels the contents of the data in 29 first. If you want to return to the state when you sampled, operate the all cancel switch CANSEL. Then, the all cancel event routine shown in FIG. 19 is executed.

First, in step 146, each flag S M P F
LG, 0VWFLG, LPF, LG, UTFLG, RV
FLG, ECFLGti-reset to “O”. This corresponds to each switch SMPL, 0 on the operation panel section 15.
VRWR, LO, ○P, UTRN, RVR8, ECHO
This is to cancel the sampling mode and performance modes M2 to M8 that were set according to the operation, and to initialize the performance mode M1.

In the next step 147, the original final zero cross address data in the original waveform stored in the zero cross address buffer ZCRADB is transferred to the end address buffer L.
Store in PADB. This is because, as mentioned above, the contents of the end address buffer LPADB may be changed depending on the operation of the increase switch INC and the decrease switch DEC, so such changes can be canceled and the contents of the end address buffer LPADB can be changed. This is to return to the original final zero cross address in the original waveform.

In step 148, the attack time buffer ATB,
The contents of the decay time buffer DTB, sustain level buffer SLB, and release time buffer RTB are initialized to the contents for setting the above-mentioned direct keying type envelope waveform.

This corresponds to each buffer ATB, DTB, SLB, RTB changed according to the operation of the envelope control operator group 17.
This is to cancel the contents of , and initialize the contents of the direct keying type envelope waveform.

In step 149, data to be given to the tone generator section 20 is initialized as follows and sent to the tone generator section 20. Sampling mode signal S M
1 and SM2 to "0".

Set the performance mode signal M1 to 111 IT and set the remaining performance mode signals M2 to M8 to 0''.Set the end address data LPAD to the final zero-cross address data stored in the end address buffer LPADB.Attack time data AT, Decay time data DT,
Sustain level data SL, release time data R
As T, the above buffers ATB, DTB, SLB,
Set the contents of RTB. In the next step 150, data for various musical sound effects are also initialized to predetermined contents.

In this way, when the all cancel switch CANSEL is operated, all or predetermined data set, selected, changed, or adjusted on the operation panel section 15 in relation to the waveform sample data are canceled. The data contents are returned to the state they were in when they were first sampled. In other words, the edited contents of the various data collected in relation to the sampled waveform sample data are canceled and returned to the initial state before editing. By being able to cancel the JEm content and return it to its initial state before editing, it becomes possible to freely edit without fear of failure, and editing functions related to sampled waveform sample data are now available. can be improved.

In addition, in the above embodiment, it is assumed that the waveform sample data stored in the data memory is expressed using the PCM (Pulse Code Modulation) method, but the present invention is not limited to this.
The data may be expressed using an appropriate data compression method, such as adaptive differential PCM, delta modulation (DM), or adaptive delta modulation (ADM). Alternatively, the sampled waveform sample data may be written into the data memory after being subjected to appropriate data correction processing (for example, normalization processing so that the amplitude level is approximately constant over the entire interval). In this case, the data correction process (level standardization process, etc.) may be performed on an analog sound signal picked up by a microphone.

The processes shown in FIGS. 8 to 19 executed by software processing in the microcomputer section may be executed by a dedicated hardware circuit.

On the other hand, although the data memory read/write control circuit in the tone generator section is constituted by a dedicated hardware circuit in FIG. 6, it can also be executed by software processing in the microcomputer section. Further, in FIG. 6, some common circuits (such as an address counter) are used for read/write control, but write control and read control may be performed by separate circuits.

In the above embodiment, a single tone pronunciation method is used, but it goes without saying that a multiple tone pronunciation method may also be used. In that case, a well-known technique for processing sound generation assignment for multiple channels may be used.

Further, in the above embodiment, the musical tone generating device of the present invention is applied to an electronic musical instrument equipped with a keyboard, but the present invention is not limited to this, but it is applicable to other electric or electronic musical instruments, a modular keyboard, or an appropriate input device. The musical sound generating device of the present invention may be applied to a sound source device module that is used by selectively connecting to equipment, a sound system, an effect device, a general-purpose computer, etc. as appropriate.

Although not specifically shown in the above embodiment, the operation panel section also displays the currently selected performance mode, the contents of the currently set end address data LPAD, the contents of various envelope setting data, and other various settings. It is preferable to provide a display device such as an LED that displays the contents of the data.

Further, in the above embodiment, three switches RVR3, UT
8 performance modes M1~ depending on the operation of RN and LOOP
M8 is determined, but each mode M1 to M8
A separate switch may be provided for individually selecting the .

Although the tone generator section in Figure 6 uses only externally sampled sounds as its sound source, it is not limited to this, and may have other appropriate sound sources, and can select desired tones from among a plurality of ready-made tones and externally sampled tones. The configuration may be such that the tone color can be selected as appropriate.

In the above embodiment, a key-on pulse 0KONP is generated by software processing (step 118 in FIG. 14) as a trigger for automatically reproducing the sampled sound immediately after sampling the external sound. may be generated by a dedicated hardware circuit in the tone generator section. For that purpose, for example, the sampling end signal SMPE
When ND is output, that is, when the end pulse END is output, the address counter 37 does not stop counting, but continues to count up from the initial address by allowing the overflow, and the sampling end signal SMP
It is preferable to input END to the envelope generator 47 as the key-on pulse 0KONP for parrot return, turn on the sampling mode signals SMI and SM2, and set the mode signal M1 to 1.

Furthermore, in the embodiment described above, the read rate of the data memory in the parrot pronunciation immediately after sampling the external sound is the same as the write rate, but this may be different.

The method of detecting zero cross is not limited to the one shown in the above embodiment, and any method may be used.6 For example, instead of adopting a zero judgment range with a certain width as in the above embodiment, It may also be possible to detect that the value actually changes from plus to minus or from minus to plus. Alternatively, zero crossings may be detected in an analog sound signal picked up by a microphone.

Further, in the above embodiment, the addresses corresponding to the detected zero crosses are stored as data in block units, but this may be stored as data in address units.

Similarly, the end address data (LPAD) corresponding to the final zero-crossing address is not limited to data in units of blocks, but may be stored in data in units of addresses. In that case, it is preferable that the amount of increase and decrease when adjusting the increase/decrease of the end address data can also be finely adjusted for each address, and the reference address to which the increase/decrease is adjusted should be the end address as in the above example. Not limited to addresses,
It may be the initial address or both.

In addition, if the actual final zero-crossing address is stored for each block and the end address data is increased or decreased in block units, the actual final zero-crossing address in the block defined as the end address is stored as the end address (12-bit (end address in address units).

Furthermore, in the above embodiment, the increase/decrease adjustment of the end address data is possible when the loop flag is set, that is, when the musical tone corresponding to the sampled external sound is repeatedly sounded, but this is not limited to this, and in other cases. It may also be possible to increase/decrease/adjust end address data (!! quasi-address data).

Furthermore, in the above embodiment, in the all-cancel process, all data set and controlled by the operation panel are canceled and returned to a predetermined initial state, but this is based on data closely related to the sampled external sound. It is also possible to cancel only this and return to a predetermined initial state.

For example, it is not necessary to cancel data for various musical tone effects.

〔Effect of the invention〕

As described above, according to the present invention, the reference address serving as the starting point or ending point when reading out the waveform sample data stored in the storage means in the forward or reverse direction can be arbitrarily adjusted. The range of input addresses read from the storage means is changed, and the range of generated sounds can be changed freely, which has the excellent effect of improving performance performance as a sampling-based musical sound generation device. play.

For example, if the original reference address is set to the final address of the waveform sample data, and the waveform sample data stored at an address before this final address contains noise, the reference address By appropriately adjusting the address toward the front, it is possible to prevent addresses containing noise from falling within the range of addresses to be read from the storage means, thereby cutting off the sound of the part of the waveform sample data containing noise. be able to. Or, if the original reference address is set to the final address of the waveform sample data,
By appropriately adjusting the reference address to an address beyond this final address, the range of addresses to be read from the storage means can be expanded to addresses where no waveform sample data is actually stored. By repeatedly reading in the specified address range, it is also possible to consciously create a silent section of an appropriate length at the joint between repeated reads, creating a special performance effect in which the sound is repeated intermittently. Furthermore, the mode of repeated reading can be freely changed by other adjustment methods.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram showing an overview of a musical tone generating device according to the present invention, and FIG. 2 is a hardware configuration diagram showing an embodiment of an electronic musical instrument to which the musical tone generating device according to the present invention is applied. 3 is a diagram schematically showing the data memory readout format in various performance modes realized in the embodiment of FIG. 2, and FIG. 4 is a diagram showing the address structure of the data memory included in the tone generator section of FIG. 2. A diagram showing an example. 5 is a diagram showing an example of a memory map of data and working memory in the microcomputer section of FIG. 2, FIG. 6 is a block diagram showing a detailed example of the tone generator section of FIG. 2, and FIG. 7 is a diagram showing a detailed example of the tone generator section of FIG. FIGS. 8 to 19 are flowcharts showing examples of programs executed in the microcomputer section of FIG. 2; FIG. 8 is a main routine; Figure 10 shows the sampling event routine, Figure 10 shows the override event routine, Figure 11 shows the timer beep end event routine, Figure 12 shows the key-on event routine,
Figure 13 shows the key-off event routine, Figure 14 shows the sampling end event routine, Figure 15 shows the reverse event routine, U-turn event I-routine and loop event routine, Figure 16 shows the echo event routine, and Figure 17 shows the increase event routine. FIG. 18 shows a decrease event routine, and FIG. 19 shows an all cancel event routine. 1...External sound sampling means, 2...Storage means,
3...Write control means, 4...Read control means, 1
4...Keyboard, 15...Operation panel section, 16...Sampling control operator group, 17...Envelope control repeater group, 18...Effect control pendulum group, 2Q...Tone Generator section, 21... data memory, 22.
...Microphone, 24...Timer beep circuit, 2
7... Analog/digital converter, 28... Adder for overwriting, 32... Zero cross detection circuit, 33
. . . Zero cross address latch circuit, 34 . . Note clock generation circuit, 37 . . . Address counter, 3
8... Comparator, 40... End point address register, 4
7...Envelope generator. Patent applicant Nippon Musical Instruments Manufacturing Co., Ltd. Representative Patent attorney Iizuka 2'1"',"l; of the drawing with the lid! (2) Figure 1 Figure 18 Procedural Amendment (Archive) April 14, 1985 Commissioner of the Patent Office Kuro 1) Akio Yu 1, Indication of the case 1988 Patent Application No. 1211 2, Invention Name Musical Sound Generator 3, Relationship with the Amendment Person Case Patent Applicant (Name) (407) Nippon Gakki Mfg. Co., Ltd. 4, Agent March 4, 1985 (Shipped March 31) As shown in the attached sheet (
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Claims (5)

[Claims] (1) External sound sampling means for sampling a sound signal input from the outside; readable/writable storage means for storing waveform sample data; and said storage for storing the waveform sample data of the sound signal sampled by said external sound sampling means. write control means for writing into the means; read control means for reading waveform sample data from the storage means in the forward or reverse direction using a predetermined reference address as a starting point or end point; and reference address adjustment for increasing or decreasing the value of the reference address. and generating a musical tone signal corresponding to the waveform sample data read from the storage means. (2) The readout control means can select whether or not to repeatedly read out the waveform sample data, and the reference address adjustment means can select whether or not to repeatedly read out the waveform sample data by the readout control means. 2. The musical tone generating device according to claim 1, wherein the reference address can be increased or decreased when the reference address is present. (3) The write control means writes the waveform sample data from a predetermined starting address, and the reference address is the final address of the waveform sample data written in the storage means. The musical tone generator according to item 1. (4) The reference address is the first address or the last address of the waveform sample data written in the storage means, and the reference address adjustment means changes at least one of the first address or the last address. A musical tone generating device according to claim 1. (5) The musical tone generating device according to claim 1, wherein the reference address adjustment means increases or decreases the reference address in units of blocks each consisting of a plurality of addresses.