JP2853805B2 - Waveform data storage device for sound generator - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform data storage device for a sound generator, and more particularly to a waveform data storage device for a sound generator that stores predetermined waveform data. 2. Description of the Related Art As a conventional sound generating apparatus, there is a conventional sound generating apparatus which is used for synthesizing harmonic musical sounds generated by frequency modulation. Among these frequency modulation methods, there is a feedback FM method. In this feedback FM method, a sine wave generated from a sine table is fed back at a predetermined feedback rate, a predetermined phase shift is given to the sine wave, a sine wave having a phase difference is synthesized, and a predetermined sine wave is synthesized by the synthesized sine wave. This is a method for obtaining a waveform. The synthesized wave is given a predetermined envelope curve by an envelope generator. [Problems to be Solved by the Invention] However, according to the conventional sound generating device, since a sound having a predetermined waveform is generated by synthesizing a sine wave, a sound having a predetermined waveform cannot be easily output. [Means for Solving the Problems] The present invention has been made in view of the above, and in order to easily create a sound having a predetermined waveform, a sound based on the waveform data is read out by reading stored waveform data. In the sound generating device, a storage means for storing the waveform data in a rewritable series of addresses, an input means for inputting the waveform data to the storage means, and a read frequency for reading the waveform data from the storage means. Reading frequency setting means for setting; mode setting means for setting a mode for directly generating a sound from the waveform data without storing the waveform data in the storage means; and when the mode is not set in the mode setting means. Determining the read frequency in accordance with the sound to be generated, setting the read frequency in the read frequency setting means, and setting the read frequency in accordance with the read frequency. Accessing said sequence of addresses of 憶 means to generate sound in response to said read frequency and the waveform data,
Control means for, when the mode is set in the mode setting means, passing the waveform data input from the input means to the storage means without storing the waveform data in the storage means to generate a sound based on the waveform data; The present invention provides a waveform data storage device for a sound generation device, characterized by having: [Embodiment] Hereinafter, a waveform data storage device of the sound generator of the present invention will be described in detail. FIG. 1 shows an embodiment of the present invention, in which six sound sources are constituted by six channels from channel 1 to channel 6. Each channel has a register array unit 1 _1, 1 ₂ ...... 1 ₆ to be described later. In addition to the register array unit 1 _1, 1 ₂ ...... 1 _6, channel select register (R0) 2, a main volume control register (R1) 3, a low frequency oscillator (LFO) frequency register (R8) 4, and the low-frequency An oscillator (LFO) control register (R9) 5 is provided. The register array sections 1 ₁ , 1 ₂ ... ₁₆ of each channel are frequency fine adjustment registers (R2) and frequency coarse adjustment registers (R
3), channel ON / volume register (R4), the left and right (LR) volume register (R5), and has five registers of the waveform register (R6), in particular, the register array unit 1 ₅ channel 5 and channel 6 And ₁₆ additionally have a noise enable noise frequency register (R7). Each channel has a waveform generator 6 _and 62 ...... 6 ₆ that generates an output sound waveform register (R6) as an address, waveform generator 6
₁ , 6 ₂ …… 6 _{6 The} output sound is attenuator 7 ₁ , 7 ₂ …… 7 ₆
D / A conversion is performed and a predetermined volume adjustment is performed. However, the noise generators 8a and in parallel with the waveform generator 6 ₅ and 6 ₆ in channel 5 and channel 6
8b is provided, the output of the waveform generator 6 ₅ and 6 ₆ and noise generators 8a and 8b are adapted to be selected to the selector 9a and 9b are input to the attenuator 7 ₅ and 7 _6. Attenuator 7 _1, 7 ₂ output ...... 7 ₆ of the left and right attenuators 10a ₁ and 10b _1, 10
a ₂ and 10b ₂ ... 10a ₇ and 10b ₇ are branched and input, where they are subjected to a predetermined attenuation and then mixed (mixed). The left mix signal is subjected to volume adjustment by the left main attenuator 11a, and the right mix signal is subjected to volume adjustment by the right main attenuator 11b. And output from ROUT. Register array unit 1 _1, 1 ₂ ...... 1 _6, channel select register (R0) 2, a main volume control register (R1) 3, a low frequency oscillator (LFO) frequency register (R8) 4, and a low frequency oscillator (LFO) The control register (R9) 5 is a CPU inside the IC.
Data input and address designation are received from a data bus 13 connected to the data bus and an address bus 14 also connected to an address bus inside the IC. The data bus 13 is composed of an 8-bit bus of D0 to D7, and the address bus 14 is composed of a 4-bit bus of A0 to A3. Each of the registers described above is connected to the register control circuit 15, and the chip select signal ▲
The data transferred from the data bus 13 is written to the register selected based on ▼ and the write command signal ▲ ▼. FIG. 2 shows the registers (R0 to R9) described above, each of which is an 8-bit register. Hereinafter, each register will be described with reference to FIG. 2 and related drawings (FIGS. 3 to 11). (1) Channel select register (R0) The lower three bits contain channel select data (chSEL). FIG. 3A shows channel selection data 0-5.
The relationship between (hexadecimal) and the selected channels ch1 to ch6 is shown. For example, if the channel selection data chSEL is 011 = 3, channel 4 (ch4) is selected. On the other hand, the register array sections 11 ₁ , 1 ₂ ... _{16 of} each channel
(R2 to R7) and the other registers R0, R1, R8 and R9 are addressed by address signals A0 to A3 on the address bus 14, respectively. This relationship is as shown in FIG. The address signals A0 to A3 take values of 0 to 9 (hexadecimal number). If the address signals A0 to A3 are, for example, 0010 = 2, the frequency fine adjustment register R2 is addressed. Therefore, after setting the "3" in the channel select register R0, Given an address signal A0~A3 of the address bus 14 2 ", that 4-channel register array unit 1 ₄ frequency fine adjustment register R2 is addressed Become. (2) Main volume adjustment register (R1) The main volume adjustment register (R1) controls the attenuation of the left and right attenuators 11a and 11b to attenuate the mixed sound of each channel to a predetermined volume. The upper 4 bits LMAL is the lower 4 bits RMA of the left attenuator 11a.
L determines the amount of attenuation of the right attenuator 11b. The maximum volume is reached when the 4-bit data is "F", and decreases by about 3 dB each time the set value decreases by "1". (3) Frequency fine adjustment register (R2) 8-bit frequency fine adjustment data FRQ LOW is set. (4) Frequency coarse adjustment register (R3) The frequency coarse adjustment data FRQ HIGH is set in the lower 4 bits. Here, 12-bit data is obtained by using the 8-bit data of the register (R2) as lower data and the 4-bit data of the register (R3) as upper data. When the data of the 12-bit and the F (10 decimal), the frequency f ₁ of the waveform output of each channel is determined as follows. 7.16 MHz in the above equation is a master frequency supplied from the CPU side. (5) Channel ON / volume register (R4) The sound output of each channel and the writing of the waveform register (R6) described later are controlled by the most significant bit chON, and the direct D / A described later is controlled by the second bit DDA. Control the mode. Further, to control the attenuation amount of the attenuator 7 _1, 7 ₂ ...... 7 ₆ of each channel by the lower 5 bits AL. FIG. 4 shows the control by the upper two bits of the most significant and the second most significant. As is apparent from the figure, the most significant bit is “1”.
In the case of (1), the sound of the channel is output, and in the case of "0", the output sound is turned off, and data (transferred from the data bus 13) can be written to the waveform register (R6). When the second bit is "1", the address counter of the waveform register (R6) is reset, and the direct D / A mode is enabled. The direct D / A mode, is passed through a register array unit 1 _1, 1 ₂ ...... 1 ₆ corresponding data transferred via the data bus 13 from the CPU, passes through the waveform generator ₆₁ through ₆ enter through the non route to the attenuator 7 _1, 7 ₂ ...... 7 ₆ corresponding, where after converting D / a, is a mode in which the output from the output terminal LOUT and ROUT. Lower 5 bits AL maximum output is obtained by setting "1F" (16 hex) in which controls the attenuation amount of the attenuator 7 _1, 7 ₂ ...... 7 _6, each time the set value is decreased "1" The amplitude of the output signal decreases by about 1.5 dB. (6) determining the right and left distribution to the left and right outputs (LR) attenuation 10a ₁ and 10b ₁ of the left and right volume register (R5) for each channel, 10a ₂ and 10b ₂ ...... 10a ₆ and 10b ₆ in a predetermined volume I do. The LAL of the upper 4 bits determines the volume of the left output, and the RAL of the lower 4 bits determines the volume of the right output. LAL and RAL have the maximum volume when "F" (hexadecimal), and the amplitude of the output signal decreases by about 3 dB each time the set value decreases by "1". (7) Waveform register (R6) FIG. 5 shows the waveform register (R6). One word is formed by the lower 5 bits, and the waveform data is set by this. 32 addresses 0,1,2 ... 1E, 1F (hexadecimal) inside
And 32 waveform data (32 words) corresponding thereto. One cycle of the waveform is constituted by 32 waveform data. 32 a predetermined number of times the address, to expand the sound signal of a predetermined frequency to the waveform generator ₆₁ through ₆ by accessing the address order at a predetermined frequency. FIG. 6 shows the relationship between the address (horizontal axis) and the amplitude level of the waveform data (vertical axis). The amplitude is increased from "0" to "31" each time the address is incremented by +1 in the direction from "0" to "1F". Level up one at a time. When the waveform register (R6) having this data is accessed at a predetermined frequency in the order of addresses, a sawtooth sound is output. FIG. 7 shows an example of data conversion for registering a sine waveform in the waveform register (R6). One cycle of the waveform is equally divided by 32 addresses (horizontal axis), and the amplitude level corresponding to each address is 5. Expressed as a word of bits. Further, by addressing the waveform register (R6), a waveform pattern as shown in FIG. 7 it is developed in the waveform generator ₆₁ through _6. As with the sine waveform, if there is another sound to be output, the waveform may be observed with a waveform observation device such as a synchroscope, and the data may be converted in the same manner as in FIG. To register the data converted as shown in FIG. 7 in the waveform register (R6), the following procedure may be followed. That is, in FIG. 4, the channel ON / volume register (R4)
As described above, the upper 2 bits of the register (R4)
When the bits are set to chON = 0 and DDA = 0, the waveform register (R
A mode is set in which the address is incremented by +1 each time data is written in 6). Like this
Write 32 words (waveform data) to 32 addresses.
At this time, as described above, the channel is selected by the channel select register (R0) 2 and the address data A0 to A3 of the address bus 14 is set to 6, and the waveform data is transferred from the CPU via the data bus 13. When the writing of the waveform data to the waveform register (R6) is completed, the upper two bits of the register (R4) are set to chON = 1 and DDA = 0.
To set the output mode. When writing the waveform data to the waveform register (R6), if the start address is to be set to "0", the upper two bits of the register (R4) may be set to "01" once and then set to "00". When set in this manner, the address counter of the waveform register (R6) is reset to "0" by software. On the other hand, in the direct D / A mode described above, the upper two bits of the register (R4) are set to “00”, “00” is written to the waveform register (R6), and then the register (R
When the upper 2 bits of 4) are set to "11", the preparation for sound generation is completed. Here, the repeated write the waveform register (R6), data to the attenuator 7 ₁ ~7 ₆ (D / A converter) for each write is output sound is transferred. In this case, the data is transferred to the waveform register (R6), but it is better to simply consider the mode of passing the data. That is, the contents of the waveform register (R6) are held without being destroyed. By employing this mode, the CPU can output sound instead of the artificial sound output from the waveform register (R6). (8) Noise enable noise frequency register (R7) Switching between noise sound and musical sound is performed by the most significant bit NE. When NE = 1, a noise sound is enabled, and no musical sound is output. The noise frequency is controlled by the lower 5 bits. Noise generators 8a and 8b are provided for channels 5 and 6. Therefore, this register (R7) is also provided only for channel 5 and channel 6. In controlling the noise frequency, the clock signals input to the noise generators 8a and 8b are controlled. When the contents of the lower 5 bits change from "0" to "1F", the sound shifts from low to high. Noise frequency f ₂ is determined by the following equation. Here, NF is the contents of the lower 5 bits of the register (R7). The noise sound is a pseudo random waveform, and the output waveform is a rectangular wave, which can be applied to the generation of a rhythm sound effect sound. (9) Low frequency oscillator (LFO) frequency register (R8) 4 The low frequency oscillator (LFO) is used for frequency modulation control, and the low frequency oscillator (LFO) is controlled by this register (R8) 4 and the tone frequency counter of channel 2. Is configured. Here, the frequency modulation refers to performing frequency modulation of the sound of channel 1 using the waveform data of channel 2. Frequency f ₃ of the low frequency oscillator (LFO), as described later, is controlled by the register (R8) 4 and the channel 2 frequency fine adjustment register (R2) and frequency coarse register (R3). Sound effect vibrato can be generated by frequency modulation. (10) Low frequency oscillator (LFO) control register (R
9) When "1" is written to the 5 most significant bits LF TRG and the lower 2 bits LF TRG, the low frequency oscillator (LFO) is reset and returns to the initial state. At this time, the content of address 0 of the waveform register (R6) of channel 2 is output as frequency modulation data, and the modulation stops there. LF T
When RG = 0, frequency modulation starts. That is, the sound of channel 1 is frequency-modulated by the waveform data of the waveform register (R6) of channel 2 to generate a sound effect vibrato. The lower two bits LF CTL are bits for controlling the modulation degree of frequency modulation. FIG. 8 shows the relationship between a low-frequency oscillator (LFO) and frequency modulation. Low frequency oscillator (LFO) frequency f
_3, i.e., the address frequency f ₃ to address the waveform register of Channel 2 (R6) is determined by the following equation. Here, F 'is a 12-bit data value (decimal number) with 8-bit data of the register (R2) of channel 2 as lower data and 4-bit data of register (R3) as upper data. "is a low frequency oscillator (LFO) register (R8) 8-bit data value 4 (decimal). the address frequency f ₃ in the channel 2 waveform register (R
6) is addressed, and the data is used to perform frequency modulation of channel 1. That is, the data of the waveform register (R6) of channel 2 is added to or subtracted from the frequency fine adjustment register (R2) of channel 1. FIG. 9 shows frequency modulation data (LFO data) corresponding to the waveform data (0 to 1F) of the waveform register (R6) of the channel 2 to be addressed, and the most significant bit of the waveform data is "1". When adding (10-1F waveform)
If it is "0", the value is subtracted (0 to F). Addition shifts the frequency of the sound of channel 1 to a lower frequency, and subtraction shifts it to a higher frequency. For example, to access the waveform register of Channel 2 at the address frequency f ₃ (R6), when the corresponding waveform data "11100" of the address, as described below,
Corresponding 4 in the frequency fine-tuning register (R2) of channel 1
The lower 4 bits of “11100”, that is, “1100” =
C is added. FIGS. 10 (a), (b) and (c) show which 4 bits of the frequency fine adjustment register (R2) of channel 1 are to be added or subtracted with the lower 4 bits of the waveform data described above. That is, 4 bits to be added are selected according to the contents of the lower 2 bits LFCTL of the low frequency oscillator (LFO) controller (R9) 5. (B) When LF CTL = 0 The low-frequency oscillator (LFO) is turned off, and a normal tone is output. (B) When LF CTL = 1 As shown in FIG. 10 (a), channel 2 is assigned to the lower 4 bits of the channel 1 frequency fine adjustment register (R2).
The lower 4 bits of the waveform data of the waveform register (R6) are added and subtracted, and the result determines the frequency of the sound of channel 1. (C) When LF CTL = 2 As shown in FIG. 10 (b), the channel 1 register (R
It is added to or subtracted from the intermediate 4 bits in 2). (D) When LF CTL = 3 As shown in FIG. 10 (c), the register (R
The upper 4 bits of 2) are added or subtracted. FIG. 11 shows the timing when data is set in each of the registers R0 to R9 described above. First, register
When setting data to R0, R1, R8 and R9,
▼ The chip is enabled by setting the signal to “0”, the register is selected by the address A0 to A3 of the address bus 14, and the data D0 to D7 set on the data bus 13 are written by the write signal ▲ ▼ “0”. . When setting data in the registers R2 to R7, set the channel to be selected in the channel select register R0,
Thereafter, data is written to the corresponding register of the channel selected in the above-described procedure. From the above description, the configuration of the entire system has been clarified. Hereinafter, the operation of the present invention will be described. Channel ON / volume register (R
4) Set the upper 2 bits chON and DDA to "10" to set the mixing mode. In this mode, the waveform register (R6) is addressed at the address frequency determined by the fine frequency adjustment register (R2) and the coarse frequency adjustment register (R3). As shown in FIG. 5, the waveform register (R6) stores waveform data in 32 addresses from address 0 to address 1F, so that the address counter for counting the address frequency increments by +1 each time the address counter counts up. The data is expanded and the corresponding channel waveform generator 6 ₁
Waveform is generated from 6 _6. In the corresponding channel, an output sound is generated by repeatedly addressing this waveform as one cycle. Waveform of each channel in the attenuator 7 _{1-7 6}
The D / A conversion is performed, the volume is adjusted to a predetermined level, and the left and right attenuators 10a ₁ and 10b ₁ , 10a ₂ and 10b _2.
After the volume is separately adjusted in 10a ₆ and 10b ₆ , mixing is performed. The left and right output sounds that have been mixed are volume-adjusted by the left and right main attenuators 11a and 11b.
After passing through a and 12b, they are output from output terminals LOUT and ROUT. The volume of each attenuator is adjusted by the main volume adjustment register (R
1), based on the contents of the channel ON / volume register (R4) and the left / right (LR) volume register (R5). As described above, the output volume of the registers (R1 and R5) changes by 3 dB for each "1", and the output volume changes by 1.5 dB for each "1" of the register (R4). Now, assume that the value of each volume register is as follows. (1) Main volume adjustment register (R1) LMAL = C (hexadecimal) RMAL = 8 (hexadecimal) (2) Channel ON / volume register (R4) Upper 4 bits of AL = E (hexadecimal) Lower 1 of AL (3) Left and right (LR) volume register (R5) LAL = F (hexadecimal) RAL = 8 (hexadecimal) Here, the attenuation value of the output sound on the left is the maximum volume "F "
Therefore, (FC) + (FE) + (FF) = 4, and the level is reduced by 4 × 3 dB = 12 dB. The attenuation value of the output sound on the right side is (F −8) + (FE) + (F−8) = 15, and the level is reduced by 15 × 3 dB = 45 dB. In the above embodiment, the dynamic range is set to 45 dB
Then, there is no output sound from the right side. The main volume adjustment register (R1) can be used for fade-in and fade-out of the whole sound, and for moving the whole sound left and right, etc.
4) can be used to adjust the output level of the channel sound or control the envelope, etc.
The left and right (LR) volume register (R5) can be used for right and left distribution of the channel sound or adjustment of the output level of the channel sound. [Effects of the Invention] As described above, according to the waveform data storage device of the sound generation device of the present invention, the mode of converting the waveform data of the waveform register into the output sound, and the input waveform data directly without storing the waveform data in the waveform register The mode for converting to the output sound can be selected according to the situation.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is an explanatory view showing a register group. FIGS. 3A and 3B are explanatory diagrams showing the relationship between a channel select register and a channel and the relationship between an address and a register. FIG. 4 is an explanatory diagram showing the mode and operation of the upper two bits of the channel ON / volume register. FIG. 5 is an explanatory diagram showing a waveform register. Sixth
The figure is an explanatory view in which the relationship between the address of the waveform register and the waveform data is patterned. FIG. 7 is an explanatory view showing an example of data conversion of a waveform generator and output sound. FIG. 8 is an explanatory diagram showing a frequency modulation mode of an output sound. FIG. 9 is an explanatory diagram showing addition / subtraction data in frequency modulation. FIG. 10 (a), (b),
FIG. 3C is an explanatory diagram showing a mode in which frequency modulation data is added to or subtracted from frequency data of an output sound. FIG. 11 is a timing chart showing the timing of writing data to a register. Description of reference numerals 1 ₁ to ₁₆ Register array section 2 Channel select register 3 Main volume adjustment register 4 Low frequency oscillator (LFO) frequency register 5 Low frequency oscillator (LFO) control register 6 ₁ 6 ₆ ...... waveform generator 7 _{1-7 6} ...... channel attenuator (D / A converter) 8a, 8b ...... noise generator 9a, 9b ...... selector _{10a, 10b 1 ~10a 6, 10b} 6 ... ... left and right channel attenuators 11a, 11b ... main attenuators 12a, 12b ... buffer amplifiers

   ────────────────────────────────────────────────── ─── Continuation of front page       (56) References JP-A-62-161197 (JP, A)                 JP-A-58-143391 (JP, A)                 JP-A-48-89714 (JP, A)                 JP-A-58-18693 (JP, A)                 JP-A-56-97395 (JP, A)                 JP-A-58-103244 (JP, A)                 JP-A-58-83894 (JP, A)                 Shokai Sho 59-166294 (JP, U)                 Shokai Sho 59-147197 (JP, U)

Claims (1)

(57) [Claims] A sound generator that generates a sound based on the waveform data by reading out the stored waveform data; a storage unit that stores the waveform data in a rewritable series of addresses; and inputs the waveform data to the storage unit. Input means; read frequency setting means for setting a read frequency for reading the waveform data from the storage means; and mode setting for setting a mode for directly generating a sound from the waveform data without storing the waveform data in the storage means. Means, when the mode is not set in the mode setting means, sets the read frequency in accordance with a sound to be generated, sets the read frequency in the read frequency setting means, and sets the read frequency in the storage means based on the read frequency. To generate a sound in accordance with the waveform data and the read frequency, and When the mode is set in the means, the apparatus has control means for passing the waveform data input from the input means to the storage means without storing the waveform data in the storage means to generate a sound based on the waveform data. A waveform data storage device for a sound generator, comprising: