JPS639240B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a sound effect generating device, and more particularly to a sound effect generating device capable of producing a delay effect or a reverberation effect. For example, when generating pre-delayed reverberation, a device as shown in FIG. 1 has conventionally been used. That is, a reverberation device 1 and a delay device 2 are prepared separately and connected in series, and the original sound and the output signal of the delay device 2 are synthesized to produce pre-delayed reverberation as shown in FIG. I was trying to let him do it. However, in such a configuration, if it is desired to cancel only the reverberation and extract only the delayed signal, it is impossible to do so without changing the wiring. In other words, regardless of whether the reverberation device is mechanical (for example, spring type) or purely electronic (BBD or uses digital memory), it usually adjusts the level of the input signal to produce reverberation. Since the degree of the effect is changing, if you want to cancel the reverb, set this level to zero (reduce the volume)
Accordingly, the input level to the delay device naturally became zero, and the delay device 2 could not be used with the current configuration. others,
When it is desired to produce a variety of effects by connecting delay lines to each other or a delay line and a reverb device, it is necessary to reconnect the devices depending on each case. This invention was made in view of the above points,
Day-laying by combining multiple day-lay devices.
It is an object of the present invention to provide a sound effect device capable of separately producing reverberation and delay effects. In this invention, a first delay device inputs an original sound signal and outputs the delayed signal, and a second delay device inputs an original sound signal, delays the signal, and applies the delayed signal to the first delay device together with the original sound signal. Two delay devices are provided, and when delay reverberation is to be produced, both of these delay devices are operated, and when only the delay effect is to be produced, only the first delay device is operated. The present invention will be described in detail below based on an embodiment of the accompanying drawings. In one embodiment of the invention shown in FIG.
The delay device is configured to have 8 channels in parallel and operate in time division, and various effects such as delay effect, reverberation, pre-delay reverberation, etc. can be produced by simple operation using the volume. In FIG. 3, the original sound signal S ₀ is input from the input terminal 10. This signal S ₀ goes from the volume VR 1 to the bypass line l ₀ and the bypass volume
Direct output terminal 1 via VR2 and summing point 11
2-1. This signal is used as a signal with zero delay time (hereinafter referred to as direct signal Sd). The volume VR1 is a volume that adjusts the volume of the entire output (output 0 ₁ +output 0 ₂ +output 0 ₃ ), and the volume VR2 is a volume that adjusts the volume of the direct signal Sd. On the other hand, the original sound signal _S0 is applied from the volume VR1 to the delay device 14 via the addition point 13. This delay device 14 is composed of eight channels of delay lines A, B, R ₁ , R ₂ . . . , R ₆ . Each of these delay lines A to _R6 has a delay time set individually, and is time-divisionally operated by a clock signal output from a master clock generator 15. That is, day line A
~ _R6 is commonly input with the output signal of addition point 13,
The signals are delayed by each set time and output. Here, the delay times of delay lines A and B can be preset externally, and the delay times of delay lines _R1 to _R6 can be preset internally, and their mixing outputs can be taken out. There is. Among the outputs of the delay device 14, the outputs of the delay lines A and B are level-controlled by the volumes VR3 and VR4, and then the output terminals 12-
2 and 12-3, respectively. Further, the mixing outputs of the delay lines R ₁ to _{R 6} are level-controlled by a volume VR5. Furthermore, the output of the delay line A, the output of the delay line B,
The mixing outputs of the delay lines R ₁ to _{R 6} are level-controlled by volumes VR6, VR7, and VR8, and are added at an addition point 16, and further added to the original sound signal _S0 at an addition point 13, and returned to the delay device 14. It is becoming more and more common. Furthermore, the output of the delay line A, the output of the delay line B, and the mixing output of the delay lines R ₁ to R ₆ are level-adjusted with volumes VR3, VR4, and VR5, and are added to the direct signal Sd at the addition point 11 and output. It is output from terminal 12-1. In the above configuration, the output terminals 12-1 to 1
The waveform obtained in 2-3 is the volume VR1~
Various settings can be made by adjusting VR8. In other words, the level of the entire output is adjusted using volume VR1, and the distribution of each component of output 0 _{to 1} is adjusted using
This is done with VR2 to VR5, and the level adjustment of outputs 0 ₂ and 0 ₃ is done with volumes VR3 and VR4, respectively. In addition, the amount by which the outputs of the delay lines A, B, R ₁ to R ₆ are fed back to the input of the delay device 14 is determined by the volume.
Adjust with VR6, VR7, and VR8 respectively. When these volumes VR1 to VR8 are turned all the way down, they are turned off. Therefore, Volume VR
3. If VR4 and VR5 are tightened as much as possible, only the direct signal Sd will appear at the output terminal 12-1, and if VR6, VR7 and VR8 are tightened as much as possible, the amount of feedback will be zero. In addition, in FIG. 3, the modulator 18 has a frequency of 0.1Hz, for example.
Clock generator 1 by ~10Hz triangle wave
This modulates the output clock of 5 and changes the RAM read timing. As a result, various effects such as a vibrato effect and an ensemble effect can be obtained by appropriately setting the feedback amount and mixing ratio. In Figure 3 above, the volume VR1 to VR
8 or the delay time of each delay line A to A6, various effects can be obtained. Table 1 shows the types of effects and the settings for volumes VR1 to VR7, delay times, etc. for obtaining those effects.

[Table] In Table 1, the ○ mark indicates the state set to a finite value other than zero (on state for volume,
An x mark indicates a state where it is set to zero (an off state for volume, a state where it is cut off for output), and an asterisk indicates a state where it is set to an arbitrary value. (1) Delay Effect As shown in Table 1, the normal delay effect is obtained from the output terminal 12-1 when the volumes VR1, VR2, and VR3 are turned on and the delay time of the delay line A is set to a finite value. At this time, since the volume VR2 is on, the original sound (direct signal Sd) and the delayed signal from the delay line A appear at the output terminal 12-1. Also, volume VR1, VR3
Even when the delay line A is turned on and the delay time of the delay line A is set to a finite value, a delay effect can be obtained from the output terminal 12-2. At this time, Volume VR2
is not involved, so only the delayed signal from delay line A appears. The above delay effect can be used to create stereo localization using the delayed PA Haas effect in halls, churches, etc., and to obtain doubling and echo of vocals and instrumental sounds in stage recording. (2) Repeat delay effect The repeat delay effect can be obtained by appropriately setting the feedback volumes VR6 and VR7 as shown in Table 1. Various repetition delay effects obtained when each value is set as shown in Table 4 are shown in FIGS. 4a to 4d, respectively.
As is clear from FIG. 4, this effect can produce a variety of echo effects. (3) Reverberation effect Of the 8 channels in the delay device 14, delay times for delay lines R ₁ to R ₆ are internally preset, and the appropriately mixed delay outputs are level-set with the volume VR 8 and sent to the input. Feedback will be provided. This feedback causes the output terminal 12-1 (or 12
-2, 12-3), a signal containing a so-called reverb effect is obtained (see FIG. 5a). For the reverb effect, the more delay times there are, the more complex the pattern (for example, reverberation that is closer to nature can be achieved _.
The six delay lines ~ _R6 have their delay times preset internally. Similarly, each channel of the delay lines A and B can be fed back with the volumes VR6 and VR7, so it is possible to produce a reverb effect. Therefore, Volume VR6
~By setting VR8 to a finite value and performing appropriate feedback, and by appropriately mixing with volumes VR2 to VR5, up to 8 channels of delay lines A, B, VR1, ..., a signal with a reverb effect by VR6 is obtained (if the direct signal Sd is not needed, turn off the volume VR2). Also, if the volumes VR2, VR4 to VR6 are turned off, the volumes VR8 and VR3 are turned on, and the delay time of the delay line is set to 0 ms, the reverb effect due to the delay time of the delay lines _R1 to _R6 can be obtained from the output terminal 12-1. It will be done. In this way, according to the configuration shown in Fig. 3, it is possible to set separate delay times for each channel using multi-channel delay lines, so it is possible to create a variety of acoustic effects compared to reverb effects caused by a single channel delay time. You can easily create natural and natural effects. (4) Day-laid reverberation effect The day-laid reverberation effect is the fifth
As shown in Figure b, a space is provided between the direct sound and the reverb effect. With conventional reverberation effects, the direct sound and reverberation sound are in close contact with each other, causing the sound to become blurry, but the delayed reverberation effect can prevent this. In the configuration shown in Figure 3, the time lag between the direct sound and the reverberation sound is set to the delay line A.
(or B) can be set using the preset value. In other words, if you turn on volumes 2, 3, and 8 and make use of output terminal 12-1, the reverb sound on delay lines R ₁ to R ₆ will be further delayed by Ams on delay line A, and then mixed with the direct sound. and is taken out from the output terminal 12-1. FIG. 6 shows a configuration diagram in which delay line A in FIG. 3 is designated as delay line 1, and delay lines R ₁ to _{R 6} are designated as delay lines 2 to realize the delayed reverberation effect. Next, details of the delay device 14 will be explained based on FIGS. 7, 8, and 9. In FIG. 7, the delay device 14 is composed of a digital circuit, and each delay line A, B, R ₁ ,
..., _R6 is time-divisionally driven. In FIG. 7, a timing clock generator 30 is used to generate various signals used within the delay device 14 based on the master clock 0 outputted from the master clock generator 15. The generation timings of various signals generated from the timing clock generator 30 are shown in FIG. 8, and among these, AS1, AS2, AS3, AC0, MUX,
REF,, is used within the address controller 31, LCK, is used within the random access memory (hereinafter referred to as RAM) 32, and LH1, LH2, LH3, SH1, and CS convert the input analog signal S into a digital signal. Convert to RAM
SHA, SHB,
SHR1 and SHR2 are used to return the data read from the RAM 32 to an analog signal and output it. The analog signal (audio signal) S input from the terminal 33 has unnecessary high frequencies cut off by the low-pass filter 34, and is sent to the sample/hold circuit 3.
5 and level indicator 36.
Level indicator 36 displays the level of input signal S. Further, the sample and hold circuit 35 receives the input signal S by the sample pulse SH1 of a predetermined period.
Sample/hold sequentially. In this embodiment, a 1280KHz clock pulse is used as the master clock 0, and a sample pulse SH
1 is created by dividing this master clock 0 into a 40KHz signal. Therefore, as shown in FIG. 8b, sample pulse SH1 is generated every 32 bits of master clock 0. The sampled data above is transferred to a programmable gain amplifier (Programmable gain amplifier).
The level is compressed by a gain amplifier (hereinafter simply referred to as PGA) 37, and then quantized by an analog-to-digital converter (hereinafter simply referred to as A-D converter) 38.
Written to RAM32. Level compression in the PGA 37 is performed as follows. i.e. 1
This level compression is performed in two steps: in the first step, the level of the input data is detected, and in the second step, the level of the input data is compressed according to the detected value. A signal CS (shown in Figure 8c) is used to time the start of each step. That is, as shown in Figure 8c, the first step takes 7 to 8 μSec after the data is sampled, and the second step takes 7 to 8 μSec after the first step is completed. It takes time. In the first step, the gain of the PGA 37 is set to 1. Therefore, at this time, the input data passes through the PGA 37, is A-D converted by the A-D converter 38, and its level is detected by the level detector 39. The detected value in level detector 39 is taken out as 4-bit data and latched in latch circuit 41. The highest digit MSB of this data is the overload indicator 4.
0 is used for overload instruction, and the remaining 3 bits of data are used as gain data. That is, this gain data is applied to the gain control terminal of PGA37 and is used in the second step.
Determine the gain of PGA37. In the second step, the sampled and held data is level-compressed according to the determined gain, and the level-compressed data is quantized by the AD converter 38.
This quantized data is latched into a latch circuit 42. Furthermore, 3-bit gain data among the data latched in the latch circuit 41 is latched in the latch circuit 43. By the way, the latch timing in the latch circuits 41, 42, 43 is determined by the latch signals LH1 (Fig. 8 d), LH3 (Fig. 8 f),
taken respectively by LH2 (Fig. 8e). still,
Signal 3 shown in Figure 8g is the latch signal LH3.
This is an inverted signal of the PGA 37 and is used to reset the PGA 37 every time the sample/hold is completed. A total of 14 bits of data, including quantized data (11 bits) and gain data (3 bits), latched in the latch circuits 42 and 43 are processed at the sample-and-hold period (25 μs) by a signal (shown in Figure 8j).
It is written in RAM32. The RAM 32 used here has a capacity of 32 kilobits. That is, when the sampling period is 25 μs and the preset space is 1 ms, the delay time can be preset to a maximum of about 800 ms. (That is, 32 kilobits x 25 μs/1 ms = 800 ms) Writing to the RAM 32 is sequentially addressed according to the count value of the address counter 44. The address counter 44 is a 15-bit counter.
The count value is counted up every 25 μs, and the count value completes at about 32 kilobits. In the write mode, the count value of the address counter 44 passes through the address controller 31 and is added to the RAM 32,
Data added to the RAM 32 is sequentially written in a 25 μs cycle. Delay time preset circuits 45 to 52 preset the delay times of delay lines A, B, _R1 , . . . , _R6, respectively. These preset circuits 45 to 52 output the BCD of each preset value.
Code data is output. These data are taken out one by one by the multiplexer 53 in a time-division manner. This time division processing is performed by the signal AS1,
This is performed using 3-bit signals AS2 and AS3 (shown in FIG. 8 o, p, and q, respectively). That is, by these signals AS1, AS2, AS3, preset data transmission times for delay lines A, B, _R1 , ..., _R6 are allocated as shown in Fig. 8i, and all data is transmitted within a time of 25 μs. Sending is completed. The data sent out in a time-division manner from the multiplexer 53 is sent to the BCD code-binary code converter 5.
4, it is converted into binary code. In the read mode, the address controller 31 subtracts the output data of the code converter 54 from the count value of the address counter 44, and adds the subtracted value to the RAM 32 as an address command.
That is, by specifying an address that is a preset delay time from the address that is currently being written, input signal data written in the past by that delay time is read out. In this way, delaying of the input signal data is performed. The count value of address counter 44 is
It is counted up every 25μs, and the preset data is allocated as shown in Figure 8i.
Since all are sent out within 25 μs, the input signal data delayed by the preset time for all delay lines A, B, R ₁ , ..., R ₆ is obtained.
The data will be output from the RAM 32 in a time-division manner. Of the 14 bits of data read out with a delay from RAM32, 3 bits of gain data are as described above.
The 11-bit quantized data is input as compressed information to the ladder network 55, which is set to have a reciprocal relationship with the PGA 37, while the 11-bit quantized data is converted to an analog signal by the digital-to-analog converter 56 and sent to the ladder network 55. input and level expanded. This means that the level has been expanded to the same level as the original input signal S. In this way, by performing non-linear A-D conversion and returning to the original state by D-A conversion, the dynamic range can be expanded. Since the data outputted from the ladder network 55 (shown in FIG. 8, s) is still time-divided, it is converted into signals on the delay lines A, B, _R1 ,..., _R6 by the sample and hold circuits 57 to 60. Can be divided. That is, sample and hold circuits 57 to 6
0, the output of the ladder network 55 is added in common, and the sample signals SHA, SHA, shown in t to w in FIG.
The corresponding signals are sampled and held by SHB, SHR1, and SHR2, respectively. Here, sample-and-hold circuits 57 and 58 read a single signal regarding delay lines A and B, but sample-and-hold circuit 59 reads delay lines R ₂ , R ₄ , R ₆ ,
The sample hold circuit 60 has a delay line R ₁ ,
Read three signals each of R ₃ and R ₅ . The reason why the delay lines R ₁ to _{R 6} are not read one by one in this manner is that, as described above, these are combined and output. The signals sampled and held in the sample and hold circuits 57 and 58 are passed through the low pass filter 6.
1 and 62, respectively, and output from the delay device 14. Further, the signals sampled and held in the sample and hold circuits 59 and 60 are combined, smoothed by a low-pass filter 63, and then outputted from the delay device 14. In addition, in FIG. 7, the refresh counter 64
is for refreshing the data in the RAM 32, and is executed by the signal REF (shown in FIG. 8k) within the allocated time shown as "REF" in FIG. 8i.
The data in RAM32 is refreshed. The address controller 31 and RAM 3
A detailed example of No. 2 is shown in FIG. In the address controller 31 shown in FIG. 9, a constant multiplication circuit 70 converts the numerical value sent from the code converter 54 into a minimum preset space (
ms), perform constant multiplication (×40). That is, if the delay time preset circuits 45 to 52 set a delay of 100 ms, for example, and the circuit outputs a value of "100", the unit number of this value, "1", corresponds to 25 μs in the RAM 32. Therefore, in order to make this correspond to 1 ms, a constant of 40 (=1 ms/25 μs) is applied. Therefore, if 100ms is set in the above example, the constant multiplier circuit 7
From 0, the numerical value 4000 (=100×40) is output. The NAND gate 71 takes the NAND between the constant multiplier circuit 70 and the signal (shown in FIG. 8j). That is, in the read mode, the constant multiplier circuit 7
Each bit output of 0 is inverted and outputted, and in the write mode, a signal "1" is outputted to all bits. The adder circuit 72 adds the count value of the address counter (15 bit counter) 44 and the output data of the NAND gate 71. This addition circuit 7
The value 1 is added to 2 from the outside. Therefore, in the write mode, the NAND gate 71
The value 1 is added to the data to become 0, and the count value of the address counter 44 is outputted as is from the adder circuit 72. Further, in the read mode, the output of the constant multiplication circuit 70 is reciprocated by the NAND gate 71 and inputted to the addition circuit 72, where a numerical value 1 is added and added to the count value 44 of the address counter 44. In the end, the preset value output from the constant multiplication circuit 70 is complemented and added to the addition circuit 72.
The difference will be taken from the count value of the address counter 44. For example, the delay time is 100ms
The constant multiplier circuit 70 outputs a numerical value.
If 4000 is being output and the count value of counter 44 is currently 10000, then 6000 (=10000
-4000) is added to the adder circuit 72.
will be output. This means that the address will be reversed by the amount corresponding to 4000, and the address counter 44 will increase the count value every 25 μs, so in the end, specify the address that was written in the past for 100 ms (= 4000 × 25 μs). I will do it. The output (15 bits) of the adder circuit 72 is divided into two sets of 7 bits each starting from the lowest order. The remaining most significant bits are used for chip selection within RAM 32.
That is, in this embodiment, the RAM 32 is 16
It consists of two RAM chips 32a and 32b each having a capacity of kilobits, and the first half of all addresses is assigned to the RAM chip 32a, and the second half is assigned to the RAM chip 32b. I'm trying to choose one. Specifically, the most significant bit output of the adder circuit 72 is logically summed with the signal (n in FIG. 8) in an OR circuit 73 and sent to the RAM chip 32.
added to a. Further, the most significant bit output of the adder circuit 72 is inverted by an inverter 74, and logically summed with the signal in an OR circuit 75.
It is added to RAM chip 32b. The outputs of these OR circuits 73 and 75 select RAM chips 32a and 32b, respectively, at their falling edges. Therefore, when the most significant bit output is "0", the OR circuit 7
Since the output of 5 is always “1” and does not fall,
RAM chip 32b is not selected. At this time, since the signal is output as is from the OR circuit 73, the RAM chip 32a is selected every time the signal falls (that is, every time allocated to each delay line A, B, _R1 ,..., _R6 ). Ru. Furthermore, when the most significant bit output is "1", the output of the OR circuit 73 is always "1" and does not fall, so the RAM chip 32a is not selected. At this time, since the signal is output as is from the OR circuit 75, the RAM
Chip 32b is selected. In the address controller 31, the 1/2 selector 76 is a multiplexer, and the adder circuit 7
Two sets of data of 7 bits each output from No. 2 are alternately selected in accordance with the signal MUX (FIG. 8m). That is, the delay lines A, B, R ₁ ,...
. . , _R6 , for example, in the first half, the lower bit data is selected, and in the second half, the higher bit data is selected, and these are output as ROW/COL data of the RAM chips 32a and 32b. The 1/2 selector 77 is a multiplexer like the 1/2 selector 76, and combines the 7-bit data output from the 1/2 selector 76 and the count value of the refresh counter (consisting of 7 bits) 64. One is switched and output according to the signal REF (Fig. 8k). That is, the 1/2 selector 77 outputs the output of the 1/2 selector 76 when the signal REF is falling (when the delay lines A, B, R ₁ , ..., R ₆ are in the allocated time and in the write mode), that is, the write; Selectively output address information for reading. Therefore, at this time, the RAM chip 3 is
Data is written to or read from 2a and 32b. Further, when the signal REF is rising, the count value of the refresh counter 64 is selectively outputted from the 1/2 selector 77 and added to the RAM chips 32a and 32b, thereby refreshing the stored contents thereof. During this period, the signal
CAS remains on, so any RAM
No data is read from chips 32a, 32b either. By the way, the signals applied to the RAM chips 32a and 32b are as shown in FIG.
Figure n) and its falling edge
The timing for addressing the chips 32a and 32b is determined. That is, as shown in FIG. 8 l, m, and n, when the signal MUX selects "ROW", the signal falls and the RAM chips 32a, 32
When the signal MUX selects "COL", the signal falls and specifies the row of RAM chips 32a and 32b, and both of these specifications specify a single address. . The latch circuit 80 is connected to the RAM chips 32a and 32b.
The data output from the latching circuit is latched at the rising timing of the signal LCK (shown in FIG. 8, r). As a result, the latch circuit 80 outputs each delay line A, B, R ₁ , . . . in the allocated time shown in FIG.
The data of R ₆ is output in a time-division manner. As explained above, according to the present invention, a variety of acoustic effects (delay, repeat delay, reverberation, delayed reverberation, etc.) can be obtained with a simple configuration in which several delay circuits are combined. Moreover, such switching of effects can be performed simply by adjusting the volume.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing an example of a conventional device for obtaining pre-delayed reverberation, Fig. 2 is a graph showing pre-delayed reverberation obtained by the circuit of Fig. 1, and Fig. 3 is a graph showing the invention. A block diagram showing one embodiment, FIG. 4 is a graph showing an example of the repeated delay effect obtained in the embodiment of FIG. 3, and FIG. 5a is an example of reverberation obtained in the embodiment of FIG. 3. FIG. 5b is a graph showing an example of delayed reverberation obtained in the embodiment of FIG. 3. FIG. 6 is a graph showing an example of delayed reverberation obtained in the embodiment of _FIG. ~ _R6 is a block diagram that realizes a delayed reverberation effect by using delay line 2, Figure 7 is a block diagram showing a detailed example of the delay device in Figure 3, and Figure 8 shows the operation of the circuit in Figure 7. FIG. 9 is a timing chart showing an example, and a block diagram showing a detailed example of the address controller and RAM in FIG. 7. 14... Delay device, 15... Master clock generator, 18... Modulator, 30... Timing clock generator, 31... Address controller, 32... RAM, 37... Programmable gain amplifier (PGA),
38...Analog-digital converter, 39...Level detector, 45-52...Delay time preset circuit, 53...Multiplexer, 44...Address counter, 54...Code converter, 56...Ladder network , 64... Refresh counter, 70... Constant multiplication circuit, 72... Addition circuit.

Claims (1)

[Scope of Claims] 1. A first delay line and a second delay line to which input sound signals are commonly input, means for feeding back the delayed output of the second delay line onto the common input line, and adjusting the amount of feedback. and a means for extracting the delayed output of the first delay line as an acoustic sound effect. 2. A first delay line and a second delay line to which the input original sound signal is commonly input, means for feedbacking the delayed output of the second delay line onto the common input line, means for adjusting the amount of feedback, and the second delay line. 1. A sound effect device comprising a mixing means for synthesizing the output of one delay line and an original sound signal, and extracting an acoustic sound including the original sound signal from the mixing means.