JPS5839000A - Electronic musical instrument - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

The present invention relates to an electronic musical instrument, and more particularly to an electronic musical instrument that has a plurality of keys or a plurality of musical tone signal generation sequences, and that adds reverberation sound with different characteristics to each keyboard or each musical tone signal generation sequence to create a relaxing sound. It's about musical instruments. Conventionally, some electronic musical instruments have multiple keyboards such as an upper keyboard, a lower keyboard, a pedal keyboard, and a solo keyboard, so that each keyboard can produce performance sounds with different tones. Furthermore, there is a system in which a plurality of musical tone signal generation sequences are provided so that a plurality of musical tones having different musical tone elements such as pitch and timbre can be simultaneously generated in response to one pressed key. By the way, when adding reverberation to the musical tones that respond to the pressed keys of each keyboard or to the musical tones of each musical sound signal generation series in accordance with such electronic musical instruments, the sound collection elements such as the timbre of the musical tones may be different for each key or Since each musical sound signal generation sequence is different, it is better to vary the reverberation time, reverberation depth, etc. of the warning sound according to each musical sound element to achieve a better performance effect. . Therefore, in such an electronic musical instrument, a configuration is desired in which the reverberation characteristics can be freely varied for each keyboard or for each tone signal generation series. This invention was developed in view of the above points,
The purpose is to add reverberant sound with a desired reverberation characteristic to each keyboard or each musical tone signal generation sequence, thereby providing a V&V with a nine-electronic instrument. In this work, a plurality of reverberant sound adding devices for adding reverberant sound are provided for each of the multiple O keyboards or each of the plurality of musical tone signal generation sequences, and the reverberation characteristics of each reverberant sound adding device are adjusted. can be set arbitrarily. When configuring a reverberation sound adding device using an electronic circuit, conventionally 118BD (ll@kNBr1
ga4e Devles ) Ya CCD (Charge
There are good ones using analog delay elements such as C-d Gama 1c.). However, in devices using analog delay elements, as the reverberation time becomes longer, that is, as the number of series-connected analog delay elements increases, the output signal level decreases and the S/N ratio becomes more pronounced. However, the drawback was that it was difficult to obtain natural reverberation sound. Furthermore, since the reverberation time is uniquely determined by the number of series-connected analog delay elements, there is a drawback that once the reverberation time is set, it cannot be changed easily thereafter. Therefore, in this preferred example KTh, the reverberation time is increased to % [1] so that the ratio does not decrease and the reverberation time can be easily changed. A digital memory is used as a recording element in the additional device, and a predetermined musical tone signal (digital musical tone signal) is input to this digital memory.
The musical sound data sampled at each period is sequentially stored, and the musical sound data corresponding to a desired delay time is retrieved, converted into analog data, and then recorded as reverberant sound. Hereinafter, the present invention will be explained in detail using the drawings. FIG. 1 is a block diagram showing an example of an electronic musical instrument according to the present invention. Lower keyboard 2°Pedal keyboard 3.
Key press detection circuit 4. Spraying circuit 5, musical tone signal generation circuit 6. Plaster color setting circuit T, Qin sound data accumulator Lu, first series reverberation sound addition device-9 second series reverberation sound addition device 10
．． Adder 11°OA converter 12 and 14. It consists of Sawand system All and 15. Upper mirror 1111, lower keyboard 2. The pedal keyboard 3 has a plurality of keys and a plurality of key switches that are activated by pressing 1ifL of each duplicate key, and is detected by the key press detection circuit 4. 4 key press detection circuits, upper price ml, lower keyboard 2. pedal keyboard 3
The operation of each key switch is detected and a key code 'KC corresponding to the pressed key is generated and output. -In the case of Jin,
The key code station is composed of the lower keyboard code KIC which shows the type of keyboard, the key range which shows the range of the key; It is fed to circuit S using koji and warimushi. The slack tone division circuit S generates a musical tone corresponding to the depressed key indicated by the key code supplied from the key press detection circuit 4, for any one of the plurality of time/minute sound generation channels in the musical tone signal generation circuit. The pronunciation is interrupted, and the channel tie sender corresponding to this interrupted channel outputs the Imaichi code KC of the pressed key in a time-division manner. ms? , the time division-sound channel in ζζ is l! Let's say there are 4 channels. In this case, the sound tone control circuit S generates a musical tone signal by outputting a key-on signal KON that controls the sound generation of the musical tone assigned to each sound generation channel in synchronization with the time-division output timing of the key KC. circuit 6
supply to. As mentioned above, the musical tone signal generation circuit 6 has, for example, 120 time-division sound generation channels, and when the chord parrot is supplied from the sound generation division circuit 5 in synchronization with the timing of each channel, The code KC (octave code OC and note code NO.
) compatible pitch and tone information! Musical sound data GD (digital musical sound signal) of a tone corresponding to sO is formed for each sound generation channel and outputted in a time-division manner. This musical tone signal generation circuit 6 uses a waveform memory reading method, a harmonic synthesis method,
* Generate musical tone data Go by utilizing musical tone signal forming methods such as wave number modulation and amplitude modulation. It should be noted that the musical sound data GO of the tong sound channel is given a part width embeg that changes from attack to decay by the middle-on haiku WOH of the own channel. ζO venue, tone setting 1 path T, Kojo Kagamiban 1. Lower key 2. Pedal key l1lO For each key, you can get %/% tone punching in row 1,
Tone color information TlID is output in response to the duplicate key 111. Then, in each tone channel in the musical tone signal generation circuit 1, "timbre information! musical tone pre-GD" of a tone corresponding to IQ is generated for the key faK indicated by the keyboard of its own channel; . Due to fins, duplicate key 11mK
The tone of A makes the musical tone Deme ao look more powerful. In this way, Denon No. 1! l! Circuit 1 generates musical tone data GO regarding the pressed mirror suppressed in each tone channel.
It outputs the hour and minute w''CC type output and collects the collected sound data.
eclkll. The sound collection data processor is a musical tone signal generation circuit-0
4! The nine sound collection data Go formed by the r-sound channel are 1
2's closing sound channel tie construction completes one cycle and is synthesized at 11 (1 channel's timing Xi! 0 open period (turn)) and output as the synthesized musical tone data IXQD of the electric tube corresponding to the pressed mirrors of all keys 1i1 to 3. 9. Every time the low sound channel tie ender makes one round, the musical sound data Gg) is synthesized with the pressed mirror of the upper mirror ml and output as the upper mirror musical sound data zGD. I met with Ishi et al., and produced the musical tone data Go related to the pressing of the lower keyboard 2 and pedal key m3.
Each time the keys are combined, they are synthesized and output as lower pedal keyboard musical tone data J09. In the case of ``Jin'', the distribution of the maximum of 12 musical tone data GO formed in each sound generation channel to each keyboard is performed by the sound generation 11 and the keyboard code [80 supplied from the circuit 5]. Synthetic musical tone data
D is converted into an analog musical tone signal by the OA converter 12, and then produced as a musical tone from the naund system 1 field. On the other hand, the upper keyboard musical sound data ΣGDu is supplied to the jllEl series cormorant sound addition warning sound l, and a reverberation sound having a desired reverberation characteristic is added thereto. In addition, lower pedal keyboard musical sound data JGDLP
is supplied to the second series reverberation sound addition device 1o, and the reverberation characteristic 0III reverberation sound of *** is added. The first series reverberant sound adding device 1 and the second series reverberant sound adding device 1e use a digital memory as a delay element to add reverberation with desired reverberation characteristics to each musical tone data JGDv, JGDLde, as described later. The reverberation characteristics are configured so that they can be freely set by specifying the delay time of musical sound data and coefficients that control the delay time information and the amplitude level. By making the delay time information and amplitude control coefficients in , 1 and 1 equal to each other, it is possible to add reverberation sound because the p1 upper keyboard 1 and the lower mirror 10 and pedal keyboard 3 are different. . The reverberation amount addition device for each series, 11KsI, adds reverberation sound to the musical sound data Σ (iDu'k and JGO
The signals are combined in the LF' subtractor 1Ill and supplied to the LF converter 14. Then, by this Om converter 14, p
Converted to an analog musical tone signal 1 and converted to an analog ν stem 1s
It is pronounced as the musical sound of a bell with an alarm bell. , the reverberation time is long as the reverberation sound for the musical sound of the lower keyboard 2 and the pedal keyboard 3, and the reverberation deep field I! # If you add O for gender, upper keyboard 1
The melody playing sound is pushed to the front compared to the accompaniment sounds of the other keys 2 and 3, making it float and become louder.
Ik can be realized. FIG. 2 is a circuit diagram showing a different configuration of the musical tone data achiem arter 8, in which the synthesized musical tone data is handled by an adder 1m,
It is formed by a circuit consisting of a register (delay trigger block) IB, a latch 8C, and an ant gate go. In other words, nine musical tone data G formed by each sound generation channel.
D is supplied to addition power A of adder 8m. The adder 8I sequentially accumulates the musical tone data GD of the first to twelfth sound generation channels by working with the register 8I, and the addition input receives a timing signal! 1 is 1
1", the output value of register IB is AND gate 80.
Supply stone through fraud. As shown in the timing chart of FIG.
The timing signal T1 becomes 111 at the channel timing corresponding to the sound generation channel of Il (the signal obtained by inverting the signal shown in FIG. 3(d) (see FIG. 3(・)), and the 1L a/dog signal becomes 80.
This timing signal TI is supplied to the circuit as a gate control signal. Therefore, add! 5IIA's addition input B has other channel timings K> except for the channel timing corresponding to the first sound generation channel, and register 8
The output value of B is input continuously. Therefore, the adder 8M outputs the tone data GD of the fxlo sound generation channel as is and supplies it to the register 8B. Then, the register aB takes in the musical tone take of the jllOQ sound channel GD t-ji B at the generation timing of the clock pulse φ shown in FIG. Output on time. That is, when the input data in the register is input to one channel, it is output after a long time. Then, at the channel timing corresponding to the third pronunciation channel, Ii Denda Haigo! When the machine becomes 11", the and dart O is open ■K, the ninth, register 1B
Musical tone data G of the 1st o tone channel held in
o is input 1 to the addition power B of the adder-A via this ant gate ID. At this time, addition input cam K of adder 1A
When the tone data GO of the second sound generation channel is inputted, the adder 8A outputs the sum of the tone data of the first and first sound generation channels. The ζ0jidIX value is stored in register $B. This kind of action is number 11! By repeating p until the channel timing corresponding to the sound generation channel of 120 channels is reached, the total addition value ΣGO of the 120 sound generation channel sound data GD is obtained at the 9th point in time when the 12th channel timing ends. This combined value JGD is a timing signal! 10 starts 9 ties Ry
It is taken in by Latte $C in the
Damn you, the acid-containing musical tone Day IXQ comes from the output of Armpit Tetsutero C.
The output can be increased as D. @swa<t>tc Synthesized musical tone data JGO (*) of time and electric +1. JGD(t+1) is shown. On the other hand, the musical tone data ΣGDW and JGDLF for the keyboard are also formed using a similar circuit. However, here, adder I performs O addition with the new musical tone data and the already systematic nine musical tone data.
Since key E is shared by key II II (D J@arithmetic@chopstick series), SELEG
At the same time as IJ is hit, a selector F is added to the input stage of register 0゜@L, which holds each total value of musical tone data for each keyboard.
, 8 electric trains are installed there. In addition, adder 1g, select! ri8J e IF I L/
The circuit consisting of the register G, Latte Hatake M, and the AND gate -x constitutes an accumulation path sequence that uses the upper shell board musical tone data ΣGDv ky#, 1 & adder Iz, and selector pzL.
y, 8, register Hatake, latch IM and ant game
)-N and the path is the bottom/bell key m electric sound day IJG
The cumulative path sequence forming the OLP is $1lIJ1! It's happening. Musical sound data for male and jil pronunciation channels. When D is added, this collected sound data Go is supplied to the addition λ cam of the adder I, so that the 7nd gate I of the summation-path series at ζ0 time is added.
I, @xq-4 tying redemption code? l K: Therefore, it becomes a closed state and t(/% Rueme, two selections of selector 1J, I becomes 1o1 and lkp% addition * sgo addition addition addition λ value 1o". This rounding , addition 5sie
The 11th output of the 1st low sound channel 〇musical sound data Or# is supplied to the addition input ^, and each accumulation is common to the selection type cam of the 8th section. supply Ryuushita/IF, 1 [Hiro, the adder 81 or the musical tone data GO that can be killed is m1lJR<selection is also □. In other words, the dragon and Tata self-F-shaped key koji code XaC is decoded and the upper keyboard signal υC indicating the upper value Ill is 11'', addition 1) 1'1m to ll selection input A
Since the musical tone data 160 containing K input is related to the pressing mirror of the upper keyboard 1, select this musical tone data i0 as t and register A.
Due to the conflict of supplying IaGK, selector sK is 5lai code l[lc ffs -/・R by f:! Lower keyboard signal LC or Bemel Ken 11 indicating the lower keyboard 2 that has been entered
Pedal keyboard signal pc ovh deviation tP indicating 3 is %1'
In the case of 0, since ◆l'1 is supplied from the OR gate 8p to the Seredato controller cam, the musical tone data GD input gtt to the selection λ cam from addition 11III is lower #I.
12 Jumitorori Pedal keyboard 3's press mirror t) Select the m tone data paD and supply it to the register L - Therefore, each tone tone data 00 outputted from the adder $ window. is divided into two series, the upper keyboard 1 series and the lower keyboard 2 and pedal Rinjo Sv series, depending on the key '@y-doku sc, and the registers aG, IL
K each distributes and supplies livestock. This ζT, the musical tone data GO of the jllOmli channel is pressed by the pedal key 111s.
If it is related to, eO Qin music--Go provides register LK through selector x, and register IN and K of Jin are held. Next, when the channel timing corresponding to the 11120Th sound channel comes and the timing signal T1 becomes 119, the AND gate 8I, IN of each accumulated 1-path series
becomes open. Therefore, the values held in the registers 8G and SL of each accumulator circuit series are stored in each AND gate 111. Through the IIN, the selection inputs of the selectors F and @ of the own series are returned, and the selection inputs A and IK of the selector 8J are respectively supplied. The selector 8J selects and outputs the musical tone data GOVt14 related to the masonry keyboard 1, which is supplied to the selection type cam via the control gate 81 when the upper keyboard signal UC is '1' o, and outputs the lower keyboard signal LCTo select the musical tone data GOVt14 related to the masonry keyboard 1. When any of the signals PC is s1#, the 11# compensation input is leaked from the OR gate -q to the Ryuta F control input 8B, so the AND gate 8
Musical tone data GO related to the lower keyboard 2 and pedal 113, which are supplied to the selector 11 via the selector 11, are selectively outputted to the IR, and the selected output data of H is supplied to the adder 10110 - the user I. Therefore, since the musical tone data pan of the gto 抛音 channel is pressed aKII"jt of the upper value a1, the number 9 is met, and the addition aS
The musical tone data GO held in the register (iK) is supplied to the addition λ power of S, and the third pronunciation chunk kill 0 Qin tone data GO relating to all the sounds is supplied to the adder cam. , in this example, as mentioned above, the sound channel of Kgl is 4 with respect to the pedal key ms.
Since the musical tone data GO is not stored in the memory of IOK, the adder 8 outputs the musical tone data GO of the 20th tone channel related to the upper value l111 as it is. This musical tone data Go is held and stored in register G via selector -r. Next, if the tsso tone chi middle tone channel data GO Amakami keyboard 1 is 2%, the upper keyboard I is stored in register H.
Since the musical tone data GO of the second tone tone channel to be KII has already been stored, the adder 81 outputs the sound generation channel of the adder 81 1111 and the third tone tone data Goot II calculated value. The addition value of these 2 Odenon days-GD is sent to the register G via the -redata r.
Ka is fed and stored in this register 8G. In this case, the data in the registers of the accumulation circuit series related to the lower keyboard 2 and the pedal keyboard 34C are held by the output of the regimen/IL being fed back to its own input via the AND gate 8N and the select I@KO selection manual B. It is done by By performing such operations on the same machine for each of the musical tone data CDs of the 12 sound generation channels,
The channel timing has gone through a cycle and the 9th tuning has been completed.
Total value ΣGDv of O and lower keyboard 2. pedal keyboard 3
The total value ΣGDLt of the musical tone data GO related to each of these is stored and held as 1, respectively. The keyboard-side musical tone data IΣGOυ and JGOLP obtained in this way are latte sir.
and the reverberant sound adding device S in Figure 1 via the
> and 10. Figure 4 shows how to add reverberant sound with a desired reverberation characteristic to each musical tone signal generating device series [No. 2! It is a printer diagram showing an example of an accident related to At the opening of the park, the upper keyboard 1. lower price 11
2. Pedal keyboard 3. Key detection storage path 4, pronunciation assignment path 1 S
, first series reverberation sound adding device S, second series reverberation plaster adding device 10. D Mu defect @12 and 14. Nawand ν stem 1
3 and 1! S is the same as the example shown in FIG. Series sound collection data A middle emulator 1.mu, 2nd series Hata 111 life M raw circuit 68. A second series of musical tone data 1111 is provided. The first and second series musical tone signal generating circuit ROMs 66S have, for example, 12 time-division sounding channels, and are assigned to each sounding channel by the sounding assignment circuit 5, similar to the musical sound signal generation port 6 in FIG. The musical tone data Go related to the pressed mirror is generated, and this musical tone data GO is generated in time and minutes in synchronization with the timing of each channel. The electric tone data GD which is shaped and the musical tone data COW which is shaped in each sound channel of -2 series Hata tone signal generation giig@s are designed so that O electric tube elements such as mid-pitch tone are different. So, there are two series of Dong Yinfu Goya like this! llj! lm, @l When the musical tone pronunciation assignment for the pressed mirror for K is t@, 1') Collect the tone for the 0 pressed mirror 11! OA becomes 2 O sound collection data GD
A film and a gel are formed at the same time. In this way, each series O is formed by each sound channel, and the nine sound collection data GDA and Gl) are supplied to the data generators 11 and 1, respectively, and the channel tie 2R completes one cycle. are synthesized each time, and are output as the first series Kanasei musical tone data JGD^ and the happy z series synthesized eastern tone data X (jDm).The first series synthesized musical tone data JGD4 and the second series synthesized musical tone data ΣGD
m shape, #E1 series reverberation sound addition device 9 and second series reverberation sound addition device 10 are respectively supplied, and these devices 9
and 10, reverberant sounds with different reverberation characteristics are added. The first and second series reverberant sound adding devices 9.10, like the first ml example, can freely adjust the reverberation characteristics using delay time information that determines the duration of musical sound data and coefficients that control the amplitude level. This can be set to The musical sound data X"ODA', ΣGel to which reverberant sounds with different reverberation characteristics are added for each series in this way is DA
After conversion into analog musical tone signals in converters 12 and 14, respectively, the Nakundo system 1s and 14 are converted into analog musical tone signals.
It is pronounced as a musical tone with reverberation. Komude, 1st series musical tone data GDmuga l・fee)
* If the pitch is low i such as 32 feet, 69, if the second series musical tone data GDs is high pitch such as 4 feet or 2 feet, JIl series musical tone data GDA
A reverberation sound with a long Hiro reverberation time and IIO loss characteristics is added to fC, and a reverberation sound with a short reverberation time and a reverberation rate of 11%/h is added to the second series Hata sound data GOK. Add the reverberation sound of
The electric sound from the rows is pushed out into the air, creating a performance effect similar to playing in a concert hall. Note that the musical tone data achiemulator 1 in this embodiment
6 and 16B also have a structural depth of O, similar to the circuit forming the synthesized tone data IΣGD in the gz diagram. 5llN is a reverberation sound adding device $ used in this invention. Block diagram showing one embodiment of No. 10, No. 6! ll is a functional block diagram functionally representing the configuration of this embodiment, #I7
Figures and Figure 318 use digital memory to record the reverberant sound of the associated delay time *! 1.1 Seta J60 extended delay 0I
M book sJi! This is a diagram showing the diagram. Theory@O For convenience, first, the basic configuration and operation of the delay circuit shown in FIG. 711 and FIG. 8 will be explained below. Akishi, then explain the p reverberation amount O chinei process by the function pron l @ of the first @kaku, and then the third! The structure and operation of a crystalline S will be explained with an example shown in IIIK. Digital memo 9r pair predetermined t>ty Gusonda synchronization!
・Input tube No. 1 O Qin sound data G which is in its original state
If D(s) is made to be stored in primary memory as time passes, the collected sound data GO(@-) stored at time (t-1)
1) To read the time when 1 hour has passed... 1, the sampling time is 0 and to address information oiL(t), and the 9 address distance 4 MU D1 is calculated within 1 hour. Addition t or subtraction is performed as shown in the (1) gjc stage or (2) equation to obtain the address information table 0m1 (t-1) at time (1-1) tcTh, and ζO address information m0R ( 1
-1) to the digital address input. ADI(t-1)mADl(t)+jADB --
-----(1) Mu O Tomi (t-1) m Mu 0 * t) -j Mu o
x----1) As a result, the musical tone date-GO(t-1) that was memorized at time (*-1) is written as
--- It is possible that the page will be read out one hour later than the one shown in 00. In other words, between the desired o*ig time IK corresponding address and @
Give JMUD凰 as transillumination time information, 111, time (t
- B to memorize the great musical sound data Go (t-1) for a long time, ya, m is "cm, Hi O, the above part α)
Address information ADH at time (t-1) by the formula
The method for determining (1-1) is applicable when musical tone data GD(t) is sequentially stored from high-order addresses to low-order addresses as time passes. 9%s0)2 is applied when musical tone data GQt) is stored sequentially from a low address to a high address. Therefore, delay a in the embodiment: circuit welfare, musical tone data GO
(4); and an address information generating circuit AC that forms β the address information mode on(t-t) for successive output shown by the above-mentioned equation α) or equation 1IK(2). , the delay length data 41700M generated as the address interval DR1 delay time information entry LD are basically provided. 7th. @ is a block diagram showing an example of a delay circuit based on such a concept, which includes a digital memory DH, an address information koji circuit Q, a delay schedule I and a memory I.
Equipped with JODM and multiplication 6 rei. As shown in the time chart of the digital memory DM Hiro and Tsuyoshi, the collected sound data GO(t) sampled at a predetermined synchronization ↑・ is set to “0”.
~"9"O The data is stored at each address from the high address "9" to the low address rOJ, for example, in a RAM (random access memory) or shift register. Musical sound data G o in this digital memory DM
(t) Designation of the write address and read address is performed by the address and information generation circuit AG. In other words, the address information a step G is provided with an address quantity C and an adder D, and the value is updated as the sampling time is updated.
, Mu01k(t+1)* MuOR(@+2), ・
... M1) B(t+1) is formed together with the read address information table on(t
-i) and outputs them as address information DM-DM of the digital memory DM, that is,
Address J * Wantam C line synchronization!・ot71 ring pulse! - is the value of musical tone data G in Jilt at the current sampling time.
O(t) is output as a write address information table DI(t), and this information ton(t) is supplied to an adder D. On the other hand, the delay length data memorandum DDM has time information DI, D(j DR=
1/? ) is supplied to the other addition input of adder D, and adder AO outputs
First, perform the calculation shown in the above-mentioned part ←) E, and output the calculated value to the musical tone data Go(t-t)oW1 from one hour ago, to the address information table on(t-t)-h, and then Then, the address quantity Ct) output information DI(1) is output as the musical tone data eo6)cs write address information table 0R(t) at the current time t. As a result, the digital memo DM can record the time IK.
At Th, the musical tone data co(t-i) stored at the time (t-i) one hour ago is read out, and at the same time
The musical tone data GOθ) is address information table 1) Jt
) is stored at the specified address. The musical tone data GD ('*-1) read out from the digital memory DM with a delay of 1 time in this way is transferred to the multiplier M.
K is multiplied by a coefficient section for amplitude level control and output after level control. Such operations are performed at each sampling time. As a result, a reverberant sound delayed by 11 hours is generated compared to the input musical sound, and the original sound is heard. In this case, if multiple pieces of delay time information OLD, which differ in one ring time, are given sequentially in a time-sharing manner, it is possible to extract information regarding multiple reverberant sounds with different delay times within the same sampling time. . Therefore, the delay circuit shown in section TIIK is used to form early reflections with complex reverberation characteristics that randomly vary in amplitude level and delay time due to the difference in Q to a reflector such as a WJWI wall. Ru. Figure 8 is a block diagram showing another example of a delay circuit.
This delay circuit is a 1-reset type Dakun Kawanta for the address quantum C of the address information relaxation circuit 5G.
I do. And for the address IMC
By presetting the delay time information OLD corresponding to the delay time value and performing the downstream operation from this one read value (OLD), the address information tables OR(*) and MUDR(t+1) output from the address quantity C are
), ...K so that the repetition period of MU0R(z+1) matches the delay time specified from the delay time information port LD 4C, and the current time! Musical tone data GO in 111
(t) from the address where it should be memorized, the musical tone data co(t-i) which was memorized some time ago, is taken out of the body and is bought with good quality. In other words, digital mail%, 9 DM is shown in Figure 1. like <
When configured with LOML, the maximum value of extended address reference * is r'lOJ, and the maximum is 10.! - It is possible to output the time-delayed mourning tone data GO (1-10), but if the desired O delay time 1 is set to, for example, 6·T@,
Address meeting 9 Quantum C output information DM・MUOR Se4
*3*t-1*O, S, ... O is repeated, and the address 01EII is used for digital mail.
is reduced correspondingly to the desired delay time 1 (giant I-To)K,
Musical sound data G O sampled in the current Kijigo 1
Make the address where you want to write (*) match the address where you wrote musical tone data G()(t-1) exactly one hour ago, and start from the address where musical tone data GDQ) at the current time 141 should be written. Sound collection data G written 1 hour ago
This is a struggle in which O(t-1) is read out. For this reason, in this agsrtaostiuit path, the output information DM・mu()R of the address force Kunta AC is changed from rOJ to “
A maximum value detection circuit MXD''bX is provided which detects that the value has changed to 9'' and uses this detection signal to preset the input time information OLD to the address capacitor AC. On the other hand, the delay circuit of this joy sW1 does not directly write the musical tone data GO(t) sampled at the current time mt#C to the digital memo IJOM, but instead writes the musical tone data o(t-i) from one hour ago. is returned at a predetermined premium, and the added value of -GO(t-1) and the electric sound data pGl)(t) which is 19 times in the current time dragon is written in the returned value. Ami.In this round, musical tone data GD (t
-1) is multiplied by a coefficient
Ryu) and -Go(
An adder AD is provided for supplying data to the data input of the dragon-1) Jff4') 18-meter DM. Therefore, in the delay &1 structure configured in this way, if the desired delay time is 6.te, the address column kC contains the output information @OM.MUD.
At the time when R changes from "0" to the maximum value ("9" in this example), the delay time information OLD, which is 0LD-6-1-5, is preset to 1. From this K, as the address kakuntam c t-zt sampling time progresses (sang view da synchronization?, every K)
5, 4, 3, 2, 1.0, 5. ---I will repeatedly output the changing address information 11DM/MUD in the meeting called O. Then, if the 4kt signal time K>, the previous musical tone data oo(t-t) stored at the address specified by the address information DM/MUOR is first read out, and then this read address For the same address, add the collected sound data Go(*-1) from 1 hour ago and the musical sound data 00(1) sampled at the current time at a predetermined ratio to obtain 9 data r GD(t) + K-GO( E-1) J is written. Therefore, in the 9-delay circuit configured in this way, the write address of the musical tone data GO (0) at the current sampling time and the read address of the collected sound data G (t-1) of 1 hour ago are Since the same musical sound data go (meeting-1) from one hour ago is fed back, it is possible to extract data related to reverberant sound whose amplitude level and delay time regularly change. Therefore, the delay circuit shown in No. 8m is used to generate a regular reverberant 4$-like reverberant sound. Furthermore, when the musical tone data is multiplied by a coefficient X and multiplied by i, the final result is 41 The data regarding the leaking reverberation sound is the original musical sound data)
Since the level is approximately < 1 & 2, the data regarding this reverberant sound is actually the reverberant sound output 5tc through an attenuator.
s1% will be given. In the case of ζO, an attenuator is not required if the coefficient X is made to satisfy r-1<K<OJ. Next, the process of forming reverberant sound will be explained using the function plot fE shown in sew. The formation process of reverberant sound First, the 611th! The formation process of the reverberant sound in the example of 3. The process of forming the early reflected sound that randomly moves to the northeast in terms of amplitude level and delay time, and the process in which the amplitude level and delay time of this early reflected sound regularly change. The process of forming reverberant sound is very important. Here, these early reflected sounds and reverberant sounds are configured to be formed in mutually independent weekly miw+ path sequences. In Figure 6, the input sound collection data (Ji. ΣGltr, JODA, JGDs) are synchronized!・The tenampudang nine musical tone data CD (t) is the first
ejllill step series 6J1 initial emission sound formation part 1 O
I'll give you a spear. The early reflected sound forming unit 11m00 can utilize the delay circuit shown in FIG. 10 types of musical tone data GO from the previous hour (l-1 to 10)
(t-11), GO(t-1,),...GO(
An arbitrary amplitude level control coefficient gB for t-Is・)
(1t=zl~l) Multiplier Ml#MIO that multiplies
and the multiplication value output Ks ・G of these multipliers Ml-MfO
O(t -11)t *5-co(electron-1sL...
Sum of K poem/GO(t-110) Σ to 1/GD(-
1), and the sum 'I Km-GD(den-1,)
I? W+1 Instantaneous value act(t) of early reflection sound at current time
It consists of the addition 911UM1 which is output as . Note that addition a) IIUM 1 c, a built-in register RO for temporarily storing the above 11N0 J lc+*GD(t-1n) at the next sampler time creation (t+1)t.
” h m Early reflection shape with a structure like Jin 11!1110@0eC
Then, the musical tone data /QD(@) which has been sampled 11t' at the current time is written to the 9th address corresponding to the current time division type among the memory addresses of M*qDOeD204B@(D). l11a1 at the sampling time (1-1) in the area in front of the register IOK in IU1[
- Since ΣX-.ao (t-i-port) is not stored, the contents of this register RO are cleared. Next, 10 types of amplitude data GO (electronic -1
Heavy) ~ GO (1-1to), delay time lx 6
In order to retrieve the collected sound data (10 (t-11)) from the message voo, the address of the menu IDO corresponding to the delay time 1 is specified, and it is sampled 11 hours ago from the address and the nine musical tone data ao ( In this case, the musical tone data GD (t-11) from 11 hours ago is read out.
The rounding address to be output is determined by -kJIIα)2 as described above. Musical sound day #0 of Kanen time 11 read out in this way
D(t −1t ) d, multiplier 1lIl#c input 11
11ζO multiplication II) j of Ml and delay time 11
The coefficient for amplitude level control corresponding to llJ [shot sound fltcHIK is multiplied by 1, and the multiplied value is 1.
GD (1-11) is the addition 11gUMI K input, the current value of register 110 and the adder, and the added value is REGIS/ROK? ! and memorized. In this case, register 110
Since the contents of the current type musical tone data (10 (s) are reset immediately after writing, register 1 is
9 K write 1! fL content is 1・GO (electronic-1) in the data.
1) becomes O In this way, the musical tone data GO(t-
1t), ii* and level control l&un are completed, that is, the first reflected sound 1eCHIK Kanchoi processing is completed, then the musical sound data go(t- 1m) monument collapse processing and level control processing are the first reflected sound 10 vote 1 formation processing and Oka 11
It is done with K. As a result, the register RO in the adder IUMI contains the first reflected sound flCHlfC function fJs day/l:tGD<1-11) and the $11 reflected sound IC.
HsK-related day I Km Added value with GO (S-1m)
” is memorized. This kind of processing is performed when the third reflected sound tcH, - the tenth reflected sound l
The same thing is done during the first part of the summer. ? , as a result, Vjis-10 has the 1st K plaster-〇end #10th reflected sound 1CHt
1・aO(t-tortoise 1) −)C for the musical tone data related to the number
nGD(t-1s*) t) 11111 sum Jl:,,G
OIk"1 ct-in) is stored. Then, this 11 sum 21 =
Heavy KB-GO (t-In) is! s1 reflected sound 1eeH1#
The instantaneous value εCM (0) of the initial reflected sound consisting of the 10th reflected sound IC111 is output via the switch circuit W. At the reflected sound formation processing time T&, the output of the register is selected and output, and at the time ?btc after the initial reflection sound formation processing, the output of the second delay circuit series O is selected and output. 1 f − / selectively output by this switch circuit ffK
iic'H(t) d, 1KIE (after being converted to an analog signal in the DDM converter or the DMU converter 12.14 in Figure 4, the sound system C15, IS) is added to the early reflections for the input musical tone. Pronounced as a sound. Therefore, the first reflected sound ICHi to the tenth reflected sound ICCH,
By setting the delay time t1 and the coefficient section for amplitude level control to f'Lih, it is possible to obtain an early reflection sound whose Kil@ level and delay time vary randomly as shown in the figure. can. Here, the sampling stamp of the input musical tone is added (
25KHz), the current time 10 prefecture sound data aO
(t) Write address irregularity R(t) If IIQI/L is 1626m11113, when reading the electronic sound data GO (1-10!8) stored at the address, the delay time is 1626m. 0.04 Shin65-I Tonasan, about 65gm5 sharper early reflection sound than the input musical sound■
It is possible to kill C wealth. On the other hand, musical sound data Go(s) obtained by sampling the input sound collection at a predetermined synchronization T is also supplied to a second delay circuit series that forms reverberant sound after the initial reflected sound occurs. This second delay circuit series converts musical tone data GO(1) into j
A delay memo 9D10 which is supplied with a time delay to a band pass filter 8m'F E, and a low-pass filter that allows only a predetermined same wave number band component of musical tone data GD (s-j) with a delay time j supplied from this memo 9D10 to pass through. A digital byte bus filter BPF consisting of a filter LPt and a bypass filter HPP, and the band pass filter B.
A first reverberant sound forming section 200 with a comb-shaped fin configuration forms reverberant sound data RvD with a coarse transmission time interval based on the musical sound data G[)(t-j) that has passed through the PIF; The *g reverberation warning sound formation part of the oil pass filter configuration that forms reverberation sound data RVI) with close delay time intervals based on the reverberation sound data RVD' is distinguished from $0@O. Composition K, lK Mourning Time Snowy Musical Day/G
D(t) is in Me-vlJ010! 048111
Address A corresponding to the current time signal among the 0 memory addresses
DII(t) K write trench. Next, Memine'jD1OK
In order to read the data GO (t-j) of one hour ago among the stored nine-tone data GO (t), the memory 0100 atsis corresponding to the delay time JK is specified, and 1 from the Mukuro address
-1-ampling before time and nine music sounds! Go(t-j
) is 1! I can be released. In this case, the electrical tube data G from 1 hour ago
The mourning address for reading O(1-J) is the first α)! as in the case of the initial summer sound formation. It is determined by IcK. Then, the delay time 1#i 10th return sound tCH, here. The delay time for is slightly thicker than one poem (j
> Ito) is set. The musical tone data GO(t-J) of delay time j read out from the memory DIG in this way is passed through the low-pass filter LP.
F t) Multiplication 1) is input to Mll and is multiplied with a predetermined coefficient ICII in the multiplier. Then, the multiplication value 1cII・GO(t-j) is temporarily placed in the register ⇒l.
'gtL 0 Next, memo 9 with l Akebono's memory address
The musical tone data GO (t-j-1) written from soo to lty trinda time (l・!・) ago appears, and a predetermined coefficient 1cIm is added to this data Go (t-j-1). Multiplier M12 is multiplied by s%A and multiplier Ml!
C) Multiplication I [Output J[1l-GO(t-J-1) 11・Go(t-J) is added to the musical tone data of 1 hour ago temporarily stored in the trellis/11, and the warpage Calculated value r KlB -GO(1-j-1) + [11・co
(t-J)J is temporarily stored in register R1 again, and is also temporarily stored in register R2. Next, the current time type is 91971971 hours (l・te・)-9 musical notes f-/GO (t-j-1) written before) 4r 910
0 Th and others should show up again, this data GO(*-j-1
)K predetermined coefficient is multiplied by 1s in multiplier M13. And this multiplication value 1cts・GO(t-J-1)
is the value r temporarily stored in register 凰2.
O(@-J-1) + Kn ・OD(t-j)
J and addition IIrL1 sot) tlA calculated value 4g -GO(t -j-1) + JCII -GO
13 to (t −j )+ ・GO (electronic −1−1) is temporarily stored in the register introduction 0, then register 1
1 K temporary memory 1%/%2 value “4 snow・GD(t-j
-1) Very heavy!・GO (electronic-1)'' is used for the next t'+ in dump/synchronization (t+1), this value ``!heavy key・
oo(1-J-i) 11th ward GO(den-j)J is written to Mesori 800. ξ-like behavior synchronizes each Nangling!・By performing 11K, - register l of one-pass filter LPF
! After removing high-wave components in a predetermined band, the musical tone data GO (1-1) is output, and this musical tone data GO (1-J) is sent to a bypass filter. Then, in the same way as in the case of high A/I [PF with Hiro, 1-pass filter LPF O], from the low sound data GO (@-j), obtain the low sound component of the predetermined band! !
is done. In other words, low-pass filter IJt O register 11 output data Go(t-j) multiplication - M14 is λ, ζO multiplication - 14 K, predetermined coefficient In and multiplication value tL! , and add 14・(16(1−j) to + and the multiplication value
is temporarily stored in the register 18, and then the musical tone data GO(t-j
-1) is read out, and this data GO(t -j -
1) with a predetermined coefficient] Kts is multiplied by the multiplier M15. Next, the multiplier value K15 obtained from the multiplier M15 is
-GO (den-j-1) Musical tone data from one hour ago temporarily stored in the a register 13 Xta・GO (t-j)
is added, and the added value is ``K!4・GO (豐-j)
+K's・G()(Electric-j-1)J is register R3
At the same time, the 0th order is temporarily stored in the register R4, and the 1 sampling time (l.
〒0) Previously written data GO(t-j-1) is read again from memory l)8[)1, this read data/G
D(t-j-1) with a predetermined coefficient X!・is multiplier M1
Multiplier in g. Then, add 1@-G to this multiplication value.
O(t-j-1)aizjiyclThe value temporarily stored in B4 is ``-4・GO(1-j)Juen Osamu・GD(den-j-
1) Add 1 to J, and add 1.- to the added value KIs” GO (bit-1-1) + ]cIa ・GO (1-j)
GO(t-j-1) is temporarily stored in register 14K. Next, register 1
3 K14・GD (heavy-j)
+x1s-Go (electronic-j-1)J is used in the next sampling synchronization (*+1), so this value "No. 4 QD
(t-j) 1i GO (1-j-1)J is written to memory 8DIK. By performing such an operation at every sampling synchronization T, the resistor of the bypass filter ■P receives the tube data 0D(t-j) from one hour ago, from which the inter-image wave components in the predetermined band have been removed. As you can see, the register 1 of the low-pass filter LPF is not used in the next number print rseat after the contents of the register are written to the memo IJsoo, so it can be shared with the register R3 of the bypass filter HPI. In this way, the musical sound data oo(s-J) of the predetermined frequency range and the high frequency range of the predetermined band with the Pand Passph (Le/IPPK) is obtained from the illumination sound. The reverberation sound alarm part HaO has a comb filter configuration with different delay times.
000C are provided in parallel. 3 best delay circuits 20
The reason why 0OA, IO@OE, and TAOOOC are provided in parallel is that when the frequency characteristic of the comb-type filter configuration O delay circuit is independent, it becomes wavy as shown by the 1111th symbols M, a, and C. The purpose of this is to flatten the surface area. In other words, by providing three polarized delay circuits 2◎00m, 20@0@, and 2 old IB with different delay times O in parallel, the -wave number characteristic as a whole is as shown by the symbol O in Fig. 111. It can be flattened to In this case, the degree of flattening increases as the number of parallel connections of delay circuits is increased. In this practical example, the delay time of delay circuit 200040 is the longest, followed by the delay time of delay circuit 200080, and the delay time of delay circuit zoooc is the most troublesome. O・Omu, 2-as 2
The only difference in 0ooc is the W/aO acid constant during uniform grinding, but the composition is all the same. Therefore, IIK is the circuit 2ooo* spxbi! For 0OOC, only the numbers of the concealer, register, and memo are shown, and the delay circuit 2011 (
The fist of 1 mu is illustrated in detail. The 1st JI with this kind of structure! 4-sound forming section 200
, the musical tone data Go(*-j) of one hour before passing through the band pass filter IFF is first multiplied by 1γ by a coefficient for amplitude level control in a multiplier M1γ. And the multiplication value [1?・GO(t-j) is multiplier M
It is temporarily stored in register 5 in lγ. Next, goose 0
Memo 17 Di pc with storage address of 4811
Musical tone day written before xB time/GO (ju-tomi 1
), the address of memory 01 corresponding to the delay time xIK'llj is m'ssn. As a result of this fraud, the memo IJD1$ was also transferred to the musical tone data GO (wo-Iris 1) from 1 hour ago.
) is II network "I5". Then, this musical tone data GO (
Den-tomi 1) Hiro adder MUM Scratch the goose, CO1gI
Calculation@IUMZ K&Tei memo 110g. D8 output data and delay circuit 2・oom, too. c oi peak v 04-as, oy-on ots
Force data addition 1fL% register 1 in the scissors combination calculator iIz
Temporary memory 13 is stored in 11. In this case, memo IJ O1~0
The read operation of memory 09 is performed in time-sharing order from memory 1701' to memory 091, and when the memory 01 is read, the data from other memories 02 to 09 is output 1.
! I haven't done it. Therefore, the content written to the register ILll in the adder SUM2 becomes the data GD (t-R1) read from the memory Dlfi. On the other hand, musical tone data GO(t
-xl) is multiplier M18 K&h
It is multiplied by Kll for control and sent to the input side of postmortem memory 01 fI#R@. Then, this multiplication value K11・Go(t
-xH) is temporarily stored in the register ■ in the current timetable type, and added to the skin data xty・GO(2j), and the added value t
-Tomi 1) The court register R6 temporarily becomes a billion. Next, the musical tone data ll, -GO(
1@-Go (electron-xl) to t-j)+ is written to the same address where the musical tone data GD(t-1!l) of one hour ago was stored. After this, register I
The contents of n will be reset. This is a rounding process in which the contents of register i6 are reset, and register R6 is also used for the processing of memory 02 in the next stage. When the processing of the memory 61 system is completed like Jin,
Next, processing for the memory 020 system is performed in the same manner. That is, a memory lJ'D with an address of 2048 words
Written 2 hours ago on Nine Music Day 1@D (t-xs
), memory 02 corresponding to the delay time x wetness is read out.
The address of memory 02 is specified.
Musical sound data 00 (1) sampled 1 hour ago from
-B) reads 1 incorrectly. Then, JinO plaster data aO(t
-Illusion) is registered in the adder 4 Hei 3 - 111t) contents (contents of ll! output from memory Di) Go (t-gai)
and the addition range is the addition value r GO'(t −xH)+'
GO (1-xH) J a register R11K temporary memory''
113 Ru. On the other hand, the multiplier Mll from 0D (t-x Zeng) Inc., which has ugly musical tone data such as Me4 豐o3''!!%
After being multiplied by a coefficient XtS for amplitude level control in , it is fed back to the input 11 of the memory D. Then, the multiplication value is 1 book G. (Electric-xM) is the register wing SK temporary memory @retained value X
4・GO(t-J) and the added value ``Kl
y・GO (electron-j) + KH・GO (t' -xs)
J is temporarily stored in register R6. This register B
The five data "-1,・GO(*-1)+niichiken・Go(t -shun')" stored in 6 is the data GO(
-Mio) is stored at the same address as the address he remembered. After this, the contents of register 60 will be reset. Next, system e of Me4vD3; IIkL is 46 of the system of memory 02! I and #I! It is done in the same way. Therefore, at the stage when processing of system 417 D 1 #D 3 is completed, the delay time t of system 03 is memorized, and the content to be written in 11 K is written as Hiroshi, GO (
den-xl) + GO (t x 禦) + GO (wo-kansatsu)
Tona 1, the content is 47 G.
D(t-j) +Ka*噸GD(1-ICI)
And for 1. Such processing is similarly performed in delay circuits 20008 and 2000C. Therefore, memo QO4,05 in delay circuit zoooi
, 06 each system's Henshima time! 4*XIs
” and the memo IJ in the delay circuit 2000C.
f)7. D8,090 each Qin tradition's duration time! Ma, Tomi 1s IC meeting, Dingi, and delay circuit 20001~
2000C! The contents of register R11, which is cleared when all the processes have been completed, are as follows: =GO(Ryu-tl)+GD(t-xM)+GD(t
-ms) - 10Go(t-x4)+GO(t-xH)+
GO (t1@) + Go (dragon-xy) + GO (t-Xm)
+GID(t-Th). As a result, following the initial reflection sound, a silent warning sound is obtained, as shown in FIG. 12, in which the delay time interval is coarse and the amplitude level and delay time are regularly increasing. 1k or Rattan 12 @ Shite Mori, the time relationship will be complicated, so it's a bit of a bit of a bit of a bit of a bit! Illustrate the reverberant sound only when you zoom in and out. As described above, the WaS reverberant sound data RVO with an extended time interval of O@ is input to the second reverberant sound forming section 5oon. The second reverberant formation unit 5ooo has a delay circuit 3.OOA, 3000, which has an all-pass filter configuration with flat wavenumber characteristics.
8,3000C are provided in series. 3 pieces 0 slow iia road 5 oonmu, 5oooa, 5ea-o
C is installed in series for the dew 1fi acoustic sound formation-〇II
This is because the reverberant sound data RV obtained in n forms the reverberant sound data RVD with a closer delay time interval. Therefore, each sso path 5aue, 5ooos, 5tate in this 11112 reverberant sound forming unit S @ OOIC The delay threshold value for each delay circuit (2000mm, 2000B, 2000C) in the Tate 1fi Warning Type Ibu 2000 is also set short.Then, each delay circuit $00OA,
30001, 3HOCti delay jlflf101R are different only in that they are the same. Therefore, I.C.
IK) h is the week iaimms*oa gallery, 3...CK
O%A is a multiplier, register 1. Show me the second part of the ringing
It shows the structure of Haruka 1gFIMM8 sea < ph-rom. First, the reverberant sound data RVDI output from the first reverberant sound forming section 2000 is transferred to the register R12 of the delay circuit 3000.
This data ivom is supplied to register R1.
2, data R written y time ago to memory MDO having a storage address of 5111■ is first stored.
In order to request VD'(t - yt), the address of the memo IJMDO corresponding to the delay time of 11 hours is specified.
and 3, 1 from memory M00! The data RVDI written before time (t-1O1lEIM comes out tL&, then the data IVD'' (t-yI) is multiplied by 11M8
0, the coefficient 4 for amplitude level control is multiplied by 1, and the multiplied value 4...IVDI(t-ys) is
It returns to the input side of the DO. Then, the ζaS data Kl...RVDI(@-)l) and the first reverberation sound forming section 2
1HO maybe current time IK. Add up the data 111 (I) that will be recited, so;gi
Calculated value r IYD'Q) +f4@ No. IVD" (t-y
t) J d ey jL/temporarily stored in group 1 0 Next, the address of MDO, which corresponds to delay time FIK, is stored again, and 1 from memo IJMDO! Write ahead of time★
The data RVD"(t-ys) is read out again,
The read data RVD'(t - yt) is the register
The 0th order temporarily stored in I 113, the register wing l! The data rRVD' (tJ+Kse・RV
D"(t-Fs)J, a constant for amplitude level control, and the stem are multiplied in a multiplier M!9.Then, the multiplied value KH・(RVD"(t)+Ks*RVD"(t- F
l )) is added to the value RVDI(lys) temporarily stored in the register 3113, and the added value BY
D"(t-Fl)+Kmr(RVD"(Q+Ks*
・RV(P(t-79) is the data temporarily stored in register R13 and goes to the 0th order, and the data temporarily stored in register R11l is ``1×)+ICm5・RVD''(t
Fl ) Use J at the current time t4t and jlys time variation 9 sampling time 1g (t + 21).
fF)b, scissors day 1 r RVDI(t) 10'@@
The @lma P(t-ys) J is written to the same address where the O data zgvo1(t-yt) was stored 1L hours ago. In this way, when the h-sensitive layer ends due to the delay path sO..., the data RVD'' (
t-yl) +Kn ・(IIVD'(t) + lh
a・IVI)(ty)) is sent to the delay circuit 5ooos, and the delay circuit 3000 with
11, the same processing as in the case of circuit 3000A is performed. Here, the delay circuit 30tOm, 3(lag)B, 3
0011C output data * mvo”, ivo”, RYD
"Fllll, circuit 5oots O delay time yl
, @path Son@C, the delay time is 1 s, the circuit 30oaA, sso. s, 5oooc f)-jista] 113,115. :1
1? The output data is determined by the following #I@)2~Equation (6) IVD"ax RVD" (1-71) + Kt* (
RVD (t) + 1@・RingYD”(t-Ft))”
"'・" (4) IVD"m IYD" (t-Fs)+
l5P (t to RVD) + Tomi-yuki・1maD''” (*-y
寥))−・−θ0itvo″'x mvo”(t-y
,)+x,-(mvoRokuryu)+1Esa・IYD”(t
-ys)) -・-1(2) And the prolongation■aSS・
・CO output data 1ma v': is outputted via a switch circuit as data for reverberating the reverberant sound following the initial reflected sound. Here, each delay circuit is 3000m, Se@01,30
When the delay time of 0gIC is established in the relationship 1M>y>ys, it is possible to form reverberant sound with dense delay time intervals as shown in FIG. That is, the delay circuit 5ooot generates the coarse reverberation sound data of the delay time interval formed by the 111i-th reverberation sound forming section 2000.
RVDJC@zuki, 111th Hibiki Sound Formation Department zoo. The 10th reverberant sound data RVD is formed at a time interval y1 that is shorter than the delay time interval of The reverberation sound 11MaD'' is formed. As this rounding and reverberation sound formation processing in the delay circuits 5oom to 5oooc progresses thK, reverberation sounds with dense delay time intervals are formed. &Th, allll180eljk, 3@III
, Register R1$ in Q Be! , 114. R
1g is not used until the next sampling synchronization after the processing related to its own circuit is completed, so it can be shared in a time-division manner. Next, the detailed structure and operation of the embodiment shown in FIG. 5 will be explained in detail. In the following description, it will be assumed that the apparatus shown in FIG. 5 forms reverberation sound according to the function shown in FIG. 7 described above. lI! shown in Figure 5! The reverberation sound adding device in the example of the tower is roughly divided into a storage section 1-1, a time information generation section 2'O, an address information generation section 1 (1), and a calculation section 40. , which corresponds to the delay digital memory DM in Fig. 8, is composed of a data memory 19 and a data memory 111 each having a plurality of memory boot storages. Using multiple memory books f, as shown in Figure 1115, 7%9800-IDI!
I, a memory MDO#MD15 of 5lzWI (I@ is 16 bits), and a memory MDO#MD15 of 2048 words (lit is 16 bits) are provided. And this Mesori SDO #8015, MDO ~ MD15
．． The data to be stored in Do to D15 is given from the arithmetic unit 40, and the storage address and read address of the data are provided by the address information O output from the address information generation unit 30.
M. Mu OR to designation 1 and each memo 17800~D
The data read from bS is supplied to the arithmetic unit 40 via the ratte 191. The time information generating section 20 corresponds to the delay length data memory DDM in Fig. 8, and includes a parameter designation circuit 20G and a delay length data memory 201. According to the instructions from , delay time information OLD"(m)( fi: DO-015, MDO#
The configuration is such that any one of the types of memo ν of MDl1 is specified and m: types of 1 to 8 are selectively output. In other words, as shown by Delay Length Data Memory 201 and IBIIK, data delay memory DO~015. Mf)0~MDIS corresponds to 757% reply ff2 Ml (Do)~Ml(
[)15"), Ml (MDO) to Ml (MOlB), and each memo IJ function fMB (Do) - MIS
(The MOIB has eight memory addresses "0" to "7" corresponding to the eight types of reverberation described above, and each memory plotter M1 (Do) to M1 (MD15) has eight memory addresses [0]. ~ “γ” has different time information OLD supervisor

[00]~DLD”(1)O), 0L
DI [Dl) ~ OLD@(01), ......D
I, DI (Dl5) ~ [) I, D” [Dl5), OL
CF(MDO) -DLD” [MDO], ------
OLDI (MD15) to DL(? (MOIISI) are stored in advance. Then, the parameter a constant information PIL consisting of 3 bits that indicates the reverberation characteristics of the light output** sound warning sound is sent to the parameter designation circuit as the lower address information. 2..., and further includes memory M()O~ME)Is, 4-bit memory number information DLH (a knee o~15) specifying the memory number re-, 15J of DQ~015, and the memory type. When the 2-bit memory type information DLI (k:D.
The memory capacity y (ms (oo) ~ MB
(one of (M[)13)), information FBI. 1 storage address (one from "O" to "7")
The delay time information pLD” [n] stored in the parameter finger 91i path 2 (specified by 10 and
! The information is supplied to the address information generating section 30 as information defining the delay time relationship of the reverberant sound of the reverberation characteristics. Note that 1. for memories SOO~801B. Fixed delay time (1
-'rs), so this memo! 71! f) O~50
Delay time information for 15 is not required. In addition, the parameter/event specification circuit 2@1m-6 includes parameter specification information FIL and a 3-bit program for selecting one of the desired control programs from among the eight types of control programs for forming reverberation sound. You can tell how the selection information PG8 appears. Next, the address information generation section 30 generates the time information generation section 20.
・Based on the delay time information OLD'[11] and program selection information PG8 output from the master clock pulse -〇 which determines the synchronization of one step of the control pump, the reverberation sound with the desired reverberation characteristics is generated. It generates address information DM/Mol for the data memory 1 to form the data memory 1, and also generates various controls (No. 1) for controlling the operation of each circuit. .Program decode memory 302
．． Control signal output register 303. Selector 304. Address Kawanta sos, latch SO6, subtraction l path 307,
Maximum value detection circuit 308. Address information output circuit 309
It is equipped with Grogramme 4: t4. ．． The soo has 8 types of control programs stored in advance to form reverberation sounds with 8 types of reverberation characteristics, and you can select which type of control program to output. 1 from He
It is specified by the current selection information PGI. -t and 1, the specified kudzu, the content of the nine control graphs is the block agram kakunta 3 (j
The output information PC is read out sequentially for each step. In this case, the early reflected sound forming section 1, the bandpass filter IIPF, and the first reverberant sound forming section 2000 explained in FIG.
．． Second reverberation sound forming unit 3000 (processing of p umbrella
Sampling synchronization (ends within T@n) Sampling! If the number of 1g is 2.5 KHz and the number of waves of 10 of the master data is 4.8M-, then 4800
゜The number of steps in one control program is □. , 192 or less nl The control program contents of these 192 steps are the same for each sampling XQT@4! lK is executed. And at each step, control progera ^
Tomite Mori! As shown in Table 82, the l step is 16.
Type 1 consists of pit information. ! Eve 2. type 1o
The contents of 31i@ are as follows: formation of early reflections,
Filter station, 1m, *Kyogyo 0! Weisha These three types 1Ill
! This is done by appropriately combining the output order of the D control program and the contents of each bit information. In this case, the l-step control program consisting of 16 bits contains the information 0F-AOIla, RGsx, OL@
. The signal input via the control signal output register 308, such as ADH (Kn), and the program memory 1J3, such as the memory write control signal WRI, etc.
After decoding @n by 02+'j, there is a way to output it via the control signal output register 303.
00 to the program decode memory 302. The details of the contents of Table 2 will be described later along with an explanation of the overall operation. On the other hand, the address counter 305, as shown in FIG.
AC(015), AC(MDO) ~ AC(Ml)Is)
I am prepared. This address is cute y/30! Each counter ac (oo) to mc (ox5), mc (mo
O)~AC! (MD15) a, Memo IJlt Information 11DL
. 7 and memory type information DLkK. Address counter C(”) (El:
QQ~[)15. The η wand output information of MDO to MD15) is supplied to the address information output port M3N via the Fi latte 30s, and the subtraction circuit 30
7. In this case, the address quantity C(n
) output information M0R(a) is the memory Do-Dis. Since the memories DO to DlB among MDO to MD15 have the address length of the ode, they are composed of 11 bits so that an address range of up to 2048 words can be specified. Note that the address counter sO5 is calculated from RmM by the constitutive formula n
Ru. Subtraction circuit 307 a, output content of address counter AC (11) input via ratte 306 0X (n)
Subtract rlJ from and get the subtracted value rADl(1)-1.”
is applied to the A11ll input of selector H4 for use in the next sampling synchronization (s+1). p! At the same time, it is supplied to the maximum value detection circuit s0 port. The maximum value detection circuit 30 corresponds to the detection circuit MXD of Hiro No. sm.
The information "AOR" is obtained by subtracting "l" from the address counter &C(n) output information M08 [ugly] specified by fap, memory book name information @0LIl, and memory type information DLk.
When it is detected that (n)-1J has reached the maximum value (all pits are %11), a select control signal 8LI1 is sent to the selector 304 to select B@large input. In the selector 304, the output information [ADH[a)-1J] of the subtraction circuit SOT is input to the input side, and the output information [ADH[a)-1J]
The output information of the delay length data memory 261 is
LOmC1l] is input, and its output is supplied to the data input of the address counter 305 to input the information -OL,, DL.
The address counter AC(a) specified by l is written (preset) by the write control signal WR3. Therefore, information OL1, D
When the address power one-tom C (II) specified by Lk is reached, the select control signal 8LB is generated from the maximum value detection circuit sa8. Reduce targets and prioritize rADR (
m)-1J will be written, and the output information m)
R(m) decreases in the direction of rOJ with the passage of time. When the value [mu0R(n)-1J] reaches its maximum value, the maximum value detection circuit 308 outputs a select control signal 5LI.
Natres counter AC (wl) because l is generated
The delay time information ox,of is provided via the selector 1104.
fi(a) is input and written. Therefore, the contents of address counter AC(n) are as follows: select control signal 8LI
After the value becomes ``I'', it changes sequentially toward ``0'' as the sampling time passes. That is, selector 304. address counter 305,
Latte 306. Subtraction enclosure 307. Maximum value detection circuit 308
In the part consisting of the address quantum C(n) specified by Mori, information OL, and DLk, the delay time information @OL
Address information AOR(n), which is equal to the delay time corresponding to D''(m) and goes around in bF14 period, is formed. This address information DR[a] is supplied to the address information output path $01. . Address information output 1 path sOI is memory 〇〇~801
B. Memory DO~015. Memory MOO~MDIS
It outputs address information for reading and writing information to and from. This address information output circuit 3
09 successively outputs information delayed by one hour from Memo 17 Do to form the early reflection sound @CH(t). In this case, the address information MDR [DO] and #! regarding the memory DO are generated.
Each delay time of 1 reflected sound gcg, ~1st-0 friend shooting sound EC horse, 1. 11-bit address information corresponding to 01-D
Bm (tm OF m ADII ~OF ・ADR
1@: Output from the control signal output register 303) is used as the lower address information, and the upper part is the memory file name information DL@ (-ru・) and the memory type information DLk.
(=DLn) and this set of information ADH[DO]
+OF” ADRoDL, 1Lk is output as address information DM・MUOR. Before, when writing the collected sound data GO(1) sampled at the current time to the memo DO, write the memo 17 DOK corresponding address column IM C( OO)
The output information module Di(DO) is taken as lower address information, and the memory O is placed above it. Information @DI, a (keDI, a ) and DI, which specify
k (Tomiguchi Lm) is added, and the information m (Do
). Output DLn and DLk as address information ()M-person OR. tm, when writing and reading data to and from memories 8DO to B015, all bits of lower address information are bound to 10#, and the upper bits of memory 800 to 8 are
Information specifying 015 @0LIC-0LO~0LII
) and DLk (=DL sD) are added and output as address information DM・muOR. Also, Reverberation iRV [)
', RVD'' when forming a memo IJ OX
~015. MOO~ Rei DI! S ノsonzonnK5
1'j Corresponding address information y/AC(01) to AC(0
15), each output information of AC(MDO) ~ AC(MD15) &0R(01:1~ADR[D15], AOR[
MDO]~ADR(MO13) is set as lower address information, information DLBTh and DLB are added to the upper part thereof,
These one set of information M01 (gr) and DLk are output as address information ON and MDR. In this case, love @
Information below DL and DLk @ADI(DO)+O
When the F-moan is added, a control pulse GPI is output from the control signal output register 30s. When the gold bit of the T1 lower address information added to the lower order of the information DL and OLlg is set to 101, the control pulse GP2 is output from the control signal output register 803. Note that the address information output circuit 32 is internally provided with a register for temporarily storing information DLm and DLk. Next, the arithmetic unit 40Fi, memory OO~015. MDQ
~MO15,! It controls the amplitude level of the data stored in the tDO-8015 and the data consecutively output from each memory, and the coefficient memory 400. Selector 401, arithmetic circuit 402. Tenbora 9 register 4/8. latch 404
It is equipped with Like the delay length data memory, the coefficient memory 400 has eight memory plotters corresponding to eight types of reverberant sounds with different reverberation characteristics, and each memory block has a memory plotter for forming each type of reverberant sound. A set of coefficients 'Ik that is necessary for
(a: 1 to 64) are stored in advance in the memory section. Then, when the parameter specification information PIL is supplied from the parameter specification path 2 @@ $, and the address information module D 凰 [Summer Yin] specifying the coefficient In outputs the control number 1 and the supply @ from the psostp et al. Out of the memory block specified by the information PAL, a coefficient is generated from the address specified by the information MOR[Ka), and the calculation input of the calculation circuit 402 (
A). The selector 401 inputs musical tone data Go(t) to the input side.
is input, and the indulgence data MRD from the storage unit 10 is input to the B*J input.The output data RGI of the temporary register 403 is input to the C side input via the latch 404, and these input data Gl) (electronic L)
One of MRD and RGD is selected by the select control signal 5Ll (i-bit configuration) output from the control signal output register 303 and is supplied to the calculation input of the calculation circuit 402. The calculation circuit 4112 has a coefficient memo IJ at the calculation input.
The coefficient KI& read out from 400 is inputted to the tempo register/40 via the latte 404.
3 output data RGD is input, and the selected output data (gPo(t), MR
O. RGD) is input, and the arithmetic control signal CTL (3-bit configuration) is output from the control signal output register SO3, so that (a) = = prison · (a) + (B) ...
... (7-1) (A) = ■ + (B)
・・・・・・・・・ (7-2) (Y) = - evil
・・・・・・・・・ (7-3)(Y)
=(B) ・・・・・・・・・−・ (
7-4)(Y)=(0)...
... Executes the calculation (7-15) and stores the calculated value (a) in the temporary register 403. Storage section 19. The configuration is such that the signal is supplied to an output register 500. Temporary register 403ti, early reflection sound dew CQt)
, performance in the formation process of JA Hibiki Ware VD', RVD''
. The operation II (g) of the calculation circuit 402 is temporarily stored, and the stored contents are set as the register output data RGO, and the selection f1401
CII input and arithmetic operation circuit 402 -)I
C feedback, 5-bit register designation information R
GH (n: O~31) has 3 registers RO~R31 with p designation 1fL, and input data is written to the register (RO-R$1) specified by information 11 entry i. Write n under the control of signal WRI. Next, the output register 500 outputs the instantaneous value tcH (electronic) of the early reflected sound obtained as the calculation value (7) of the calculation circuit 4G2.
The instantaneous value RVO(t) of the reverberant sound following the initial reflected sound is captured by the write control signal WR2, and this captured data is outputted via the attenuator 51111. In addition, the select control signal 8L in selector 4@1
1 and the calculation control signal C in the calculation circuit 402
TL is included in the operation oPc that is also output from the control signal output register 303. Next, the operation of the above configuration will be explained. Operation explanation, early reflection sound formation operation (1) To write the musical sound data on(t) sampled at the current time to OO, 8L1:8εL
IeT(4) CTL : (A) = ni) The select control signal SLI and calculation control signal CTL having contents n are outputted from the control signal output register 1303 as the operation 717 code oPc. As a result, the selector 401 supplies musical tone data GO(t) to the calculation input of the calculation circuit 402. Further, the arithmetic circuit 402 outputs the musical tone data GO(t) inputted to the arithmetic input () as the arithmetic value (7). (2) Next, specify the address of the 9th memory DO corresponding to the current sampling time (electronic), and write the output data GO (0) of the arithmetic circuit 402 to this address, OL, ;DL. DLk: 0LD WB2: I 1” (WRITE) L3: sx
# (LmTCH) Memory type information OLk, write control (
111WR4, the latch control signal L3 is output as the operating code OPC, and the memory number information DLa is output from the control signal output register 308. As a result, the output information M0R (DO) of the address input terminal AC (OQ) corresponding to the memory DO is changed to the current time t.
It is latched into latch 361B as lower address information for writing musical tone data GO(*). Then, this latte 1f lower address information MOR [
OO] is added to the address information output circuit 309, and memory number information DLII (=OL(1)) and memory type information QLk (=OLD) are added to the upper part of the address information output circuit 309, and the memory type information QLk (=OLD) is added.
It is output as write address information DM-A I)R of musical tone data GO(t) for JDO. As a result, data memory 1100 memory 1
The current time t (D musical tone data GO(t) given to the data input of 700 is written to the address corresponding to the current time 1 by the write control signal 'W'R4. (3) Next, each 1 In order to clear the register RO that stores the composite value of early reflection sounds for each
: 10 CTL : (7)=O WRI; The arithmetic control signal CTL and write control signal WRI with the contents indicated by 'l' (WRITE) are the operation code OPC, and the register number information 1ta= is the control signal output register 303. is output from. As a result, rOJ is written to register RO. That is, register RO is cleared. (4) Next, in order to form the first reflected sound fcH1,
-AOR,: OF fist AOR. DLk: oL,. GPI: %1' L2: Memory 11 station information DI with contents indicated by %1' (LATCH), control pulse GPI,
Latch control signal L2 is operation code OPC
, and the delay time l, K of the first reflected sound ECHm.The corresponding address information OF.50IE1 is sent to the control signal output register 303 m! The output is 1%. In this case, the address information output circuit 30!1 holds the memory number information OL, (==-OI4) in step (3). As a result, the address information output circuit 309 outputs the address information 0R(DO") latched in the latch sO6.
l and delay time 1t K corresponds to 9 address information OF
・MOR, and the added value is used as the lower address information, memo number information DLa (=DLe) t memory type information DLk (-DLo) is used as the upper address information,
Amplitude data written 11 hours ago from memory 00・8P
Address information for reading O(t-1s) ON/
Output as a program OR. As a result, the musical tone data GO (t-It) of 11 hours ago is read from the memo IJ Do, and this read data GO (1-IJ) is launched into the launch flH by the latch control signal L2. (5) Next In order to transfer the current value of register NO to the latch 404, the latch control signal L1 with the contents indicated by RG,: RO Ll; %1'(Lk'reH) is transferred as an operation code.
Also, the register number information 19m is the control signal output register s.
OS p et al output stone. As a result, the current value is transferred and stored in the current value line latch 404 of the register RO. (6) Next, % 凰1 hour ago musical sound data GO (kai-11
) is multiplied by 1 by the coefficient for amplitude level control, and the temporary value for the first reflected sound 1lCHI is rounded to obtain 1・GO(t −11), Mu0R(KfI): AOR[Kl]! ILI
: 8gLSC? @) CTL: (＾)・
) + (8) M (A) indicates the control signal 8L.
1. Operation control signal CTL d (operation code opc, address information A for reading i9 constants)
OR(KI&) is output from the control signal output register 303. As a result, the first reflected sound is 1 from the coefficient memo 17400!
The weight is read out to the 1cHIK coefficient and the calculation circuit 402
calculation input (6t supplied to selector 401
is the musical tone data Go(*-1s) from 11 hours ago supplied to the 8gA selection input from the Latte 191, and calculates the data GD(t-b'') to the calculation path 4H.
is supplied to the calculation input (1) of. 9, the arithmetic circuit 402 calculates (nm(A)・(X)+(a)=Kt−GD(t
-tl)+(10) is performed. In this case, since the content of the resistor blade O is reflected at i in step (3) above, and at ζ, the first reflected sound εCH
1・Go(t-11) is the instantaneous value related to 1 in the calculation circuit 4.
n is obtained as the calculated value (7) of 02. (First order, the instantaneous value of the first reflected sound tcH1 is 1・Go(t
-1,) to be stored in the register RO, the write control signal WRI with the contents indicated by RG 0; , is output from the control signal output register 303 Th. As a result, the output data (7) of the arithmetic circuit 402 =
K,·co(t-tt) is written to the register RO. By completing the steps up to this point, the instantaneous value of the mineral 1 reflected sound εCH, is written to the register RO as 1·G. (Meeting -1 is obtained. (8) Next, the instantaneous value Kg GO (t -1m ) ~ Kl regarding the second reflected sound gc■2 ~ 10th reflected sound gc formula
@-QO(t-11@) is the step reconnaissance)~(7
), the formation field can be created in the same way. Therefore, the first O reflected sound εc
After the operation of step (7) regarding n, , is completed, in the ninth step, the write control signal WR is transmitted to the register RO to the register 500 of the first reflected sound gcH, to the first O-th opposite sound ECH1,
2 and forwarded to attenuator 101. j, Filter operation (1) First, to read out the musical tone data GO (t-j) of one hour ago from the memo IJDIO, OL: DLi. OLD", 0LD L3; %1" (LATCH) L2; 'l' (LATCH) In the memory type information 01. of the content itL, the latte control signals 1 and 8 are added.
, L2 is the operating code OPC, the memory number information OL 2 outputs the control notes, and the output is output from the JIS/303. As a result, address type 9 corresponding to memory 010K
Quantum C (DIG) output information table 01 (010) is 1
The previous musical tone data Go(t-j) is latched into the latch 306 as lower address information for reading out. Then, this latched lower address information table 0R(0
10), the address information output circuit 309 adds memory number information 0La (=OLl) and memory type information DLk (g=OLp) to the upper level, and outputs musical tone data oo(
t-J) is output as read address information OM-AOR. As a result, the musical tone data GO(s-j) of one hour ago is read from the memory 0.10, and this read data GO(@-j) is latched into the latch 1-1 by the wrap control signal L2. (2) Next, rounding to sample the current side type and write the Yugaku tone data GO(t) to the same address as the read address of data 00 (Ryu-j), 8L1: 1ilIJcT) CTL:
The left control signal ILIm- and the arithmetic control signal CAL are also outputted from the control signal output register 303 as the operation code rOPC to the contents O- indicated by (A) and (2). As a result, the selector 401 supplies the musical tone data GO(t) to the arithmetic circuit 4020 as an arithmetic input (ELK).The arithmetic circuit 402 also inputs the musical tone data 00 to the arithmetic operation input.
Output (1) as the calculated value (1)2°0) Next, 1.
Rounding to write musical tone data GO(t) to memory 010, DL@: OLs・OLk: 0LD WB2: %1'(WRITE)L3; ◆l
'(IJTeH) Memory with contents indicated by! Separate information DLk, write control signal WR4, latte control! The number L3 is output as the operation code OPC, and the memory number information DL- is output from the control signal output register 303. ζ, to deal with the ringing OIO, 9 address counter AC (01G) Q output information 71, mu OR (, I) 1
G,) is input to the latch 31 as lower address information for writing the current time t (D musical tone data GO(t)).
It will be done. Then, this latched lower address information AO
R(0101 is the memory number ff1lNDLa(, -DLt・
) and memory type information @ DLk (=D'L'n) are added, musical tone data GO (
The write address information of t) is output as OM/MUOR.
Ru. As a result, the collected sound data GO(t) at the current time *11t, which is given to the data input of the memory 010 of the data memory 180 via the arithmetic circuit 402, is changed to the address corresponding to the current time division type by the write control signal W1t4. Next, in the low-pass filter LPP, the contents of the register R1, the collected sound data GO(1-j) of the coefficient Ktxsj time before
Therefore, in order to calculate [R1) + Its・Go(voltage) and store this calculated value again in the register 11K, first, the control signal Lm is indicated by the contents of RGn: 11 as the operation code. As OPC, the register number information RG trajectory is output from the control 4]! number output register 303, and the contents of register R1 are transferred to the latch 404. Reference) Next, calculate Kll・co(t −3). To do, AOR [K difficult]; MU0R (Kll) 8L1: liiLgc'ding (8)C?
L: Select control signal 8L1 with the contents shown by (A) = (~・■ + (B). The calculation control signal CTL is used as the operating code OPC, and the address information 401 (Kn) for reading constants is used as the control signal. An output is output from the output register 303. As a result, the coefficient Kll is read out from the coefficient memory 40G and supplied to the calculation input (2) of the calculation circuit 402. In addition, the selector 401 is latched in the previous step b-α). tilt K latched musical tone data oo(t
-j) is selected and the arithmetic operation power QQK of the arithmetic circuit 402 is supplied. By ξ, the calculation (2) path 402 Fi, (1) ni)・■+−)=Ktl・Go(electron−j)+R1 is performed. In this case, the contents of register R1 are cleared at the stage when the filter processing at the previous sampling time (*-X) is completed.
Then Kg -of)(t-J) Calculation 1 [(1'),
! - I'll get it. 0) Next, this calculated value Kll ao (t-3)
mGn : RI WRI : II' (WRITE) f) The write control signal WRI shown in 12 is the operation code OPC, and the 9 register number information RG is output from the control signal output register 303. be done. As a result, the output data of the arithmetic circuit 402 is 11·g.
[)(t −j ) is stored in register R1. a) Next, rounding to read musical tone data co(t-j-1) of (J-1) hours ago from memory SDO, DLa g
DL@OLk: alas GP2: ◆l' L2: Memory type information DLk with contents indicated by '1'(LA'l'CH), latch control signal L2
．． The gate pulse signal a de 2 is the operating input voltage O.
As a PC, the memory number information OL can be output from the control signal circular register 303. Then, the address information output circuit 301 converts all bits of the lower address information to 1.
0# and the memory number information OL above it! I <
= o'xs ) and memory type information DLk (=
f) L IID ) is added and output as address information 0M40B for memory WOO. As a result, the musical tone data GO (1-j-1) from 800 tP (j-1) hours ago is brought to light and the latch 1$1K is latched.俤) Next, add 11・ao(kai-j) to the contents of register R1.
. Coefficient Its * Calculate Go (t-j-1) + ("R1) using the musical tone data/Go (electronic-3-t) ratted in ratte 191, and store this calculated value in register R1. A round that can be remembered again,
First, RG! 1', wing l Ll: The latch control signal Ll with the content indicated by l' (L whip cit) is the operation code OP.
As G, the register number information RG is output from the control signal output register 303 as 1fL% L'jiX1n1
f) Content 1[oGD(1-j) is transferred to latte 404. (9) Next, K1.・Go(t-$-1)+(R1)O
To perform the calculation, ADII (Km): MOR[K, snow]8L1
:l drunkenness, 1tCT(II)C'rL :
Cr)-"@)-C1O+<8) signal @'Ll, C"l'L is the operating code O
As a PC, the address information module [K,] also outputs the control write output register 5os-s.As a result, the coefficient KV is read from the coefficient memory 400 and is input to the calculation circuits 4 and 2. supplied to The bottle, selector 4111 is latte IIIK Tsukutete-
Select the electric pipe data zoo(t-j-t) and use the arithmetic circuit 4.
02 calculation input (1). As a result, the arithmetic circuit 402 calculates (7)=(~・(1)+(8)=1!・GF)(t −j−1)+Ktt・Go(t
-j) is output. Then, the calculated value (A) is stored in the registers R1 and R2 in the line method step. As a result, the contents of registers R1 and R2 are (111ζ(RL)-It snow ・Go(t-j-1)+
Niho! - Becomes GO (Government-j). (lO) Next, set the value and coefficient of register R2 to 13. Memo 1J80OK K13・GO(t-1
-1) + (R1), first register R
In order to transfer the contents of 2 to the latch 404, the aforementioned bl
), the contents of register R2 Kn and Q
D (t-j-1) 10th ward tsGo (1-j) is latte 4.
Transferred to 4. (11) Next, read the coefficient Ill and Ktsl)0(t
−j−1)+[凰2], the above b−
ψ) In the same way as the 0 step, MOX (Ward a); MDB (Kts)8L1
:8εLgc'r(s)CTL : (g)=
(~・■+Signal 8L1.CTL with the content shown in (8)
is the operation code)'01'C, and the address information is OR[1[all] is the control signal output register 3.
Output from 03. As a result, coefficients Ill are successively output from the coefficient memory 4007Dh and supplied to the calculation input (A) of the calculation circuit 402. Further, the selector 401 selects the musical tone data oo(t-J-1) latched in the ratte 1S11 and supplies it to the calculation input (3) of the calculation circuit 402. As a result, the arithmetic circuit 402 tel:(g)=■・■
10) -Kzs ・(10(t -j -1)+KII-GD
Output the calculated value (7) of Hoyu GO (t - J) to (D-J-1)+, and this calculated value (A) will be stored in the register 112 in the next step, and this register wing 2
A bypass filter HPF K is supplied via the bypass filter HPF K. (12) In the final step in the low-pass filter LPF, the contents of register R1 are loaded into memory 8DO and used at the next sampling time (t+1)+. ) + to ■・5PO(t-j)J is transferred to the ratte 404 in the same way as the step b-(8) described above, and then the arithmetic circuit 402 performs the calculation (1)=(8). Then, the calculated value r(i')=, -GO(Electron-J-1)+ is 11
Go(1-j)J is written to memo 1J800. Jin's write operation line, DLa: DL・DLk; DL Nishiki GP! : II' WB2 : Indicated by '1' (WIIITI)
The operation of the contents; -do OPC and memory number information OL is performed by outputting from the control signal output register 303 $. When the operation of the low-pass filter LPF is completed, the operation of the bypass filter H1''F is performed next, but the explanation of the operation of the bypass filter HPF will be omitted.Next, the operation of forming the reverberant sound RVDI with a coarse delay time interval is performed. C1 reverberation sound RVDM formation operation (1) tf, register R4 of bypass filter HPF'
In order to multiply the stored data oo(t-J) by π1 number Elf and store the multiplied value 1cu・GO(t-j) in the register Rs, RG: Wing 4 Ll: $1' (LATCH) Latch control signal LI Th and register number information R with the contents shown.
Gn is output from the control signal output register sO1, and the contents of the register co(t-j) are transferred to the latch 4g14. ■) Next, to calculate “I?・GO(t-j),
R(Ka): MU0R(11y)8L1:
811JCT((')CTL $(ri”4)
-00 Contents O select control No. 1 aX, t, arithmetic control signal CAL, address information for reading coefficients 0R (
Ha) is output from the control signal output register 303. As a result, the coefficient ``ma'' is read from the coefficient memory 400 and supplied to the arithmetic input 2 of the arithmetic circuit 402. Also,
The select 401 selects data ao(e-j) latched in the latch 404 and supplies it to the calculation input (6) of the calculation circuit 402. As a result, the arithmetic circuit 402 (A)・OO=Kty・GO(t−J
) outputs the calculated value (a). This calculated value (7) is stored in the register section in the next step. (3) Next, read the musical tone data GO (txl) K1 hours ago from memory 01 of the data memory 190, add this data co (s-xI) and the current value of register R11, and add the added value again. To store register RIIK, first, DILa'', 0LI DLk: DL. L3: %1'(Lm?CI[)L2;
The latch control signal L3. has the content indicated by 1' (L whip C11). L2 and memory number information 0L2I
and memory type information DLk is the control signal output register 3
Output from 03. As a result, address counter A corresponding to memory 01
C(01) output information 0R(01) is musical tone data G
It is latted to the lattice 30@ as lower address information for reading O(t-K1). Then, this lower address information AOR (011 is the address information output circuit 30
, memory number information [)L and memory type information DLk are added to the upper part of the data memory lll0.
The address information of Maili 01 is outputted to K as 0N-kDB. As a result, musical tone data GO (t-xl) K1 hours ago is read from the memory 01 and latched to the latch 191. (4) Next, a rounding operation is performed to add this read data G() (a - town) and the current value of register R11, register 11!1
The contents of 1 are transferred to Latte 4.4, ILI
: Hatake II, glee (phrase C'rL: (
The select control signal SLI and the arithmetic control signal CTL having the contents shown by (a)=(3)+ side) are output from the control signal output register 303. Then, the selector 401 selects the musical tone data GD(t K1) that is comparable to the lattice 1s1 and supplies it to the arithmetic operation circuit 402 (X)K. As a result, the arithmetic circuit 402 calculates (7)=(3)+ω), (R11)+GD(1-Tomi
) Outputs the calculated value (a) indicated by In this case, the contents of register R11 are the previous sampling time (electronic-1).
The glial is dead when it finishes the slicing motion. Therefore, the calculated value (7) in this step G4)K is GD
(t-xs) After this, the calculated value (a) is transferred to the register R11 and stored. C5) Next, - musical tone DE! from memory D1! RiGD (Ryu-I
El), multiply the coefficient by 1-, and then add the value of the multiplication value 1s-QD(t-xl) and the contents of register 15 "-7・GD(t-j)J". Register Ill K Rounding to be stored again, as previously mentioned O--α)
The contents of register R5 [K! !・
GD(t-J)J is transferred to the latte 404. (6) Next, the musical tone data GD (Ryu-K1) latched in the latch 1111, the data [K17・GDCt-j)J latched in the latch 404, and the coefficient 1-, O times are obtained. ”Kll・GD (to - Tomi x) + Kxy・GD (t
−j), ADH[Ktsuru]; MuDR(Kts) sti: HatakeKLΣCT(B)8TL
The select control signal 8L1, the arithmetic control signal CTL, and the address information ADH (Km) for reading coefficients are outputted from the control signal register 803, the contents of which are indicated by lk')-■ and (a) 10). As a result, the coefficient XXS is read from the coefficient memo 'J4HI, and the calculation input (A) of the calculation circuit 402 is avoided.
Ru. Further, the selector 401 selects the resounding musical tone data GD (txl) and supplies it to the calculation input of the calculation circuit 4. With this, p, operation - path 4 [is (a) = (4) ・■ + 1)) =, - GD (t-xx) + 1y GD (1-J)
Output. Then, in the next step, this calculated value (A) is written to the address corresponding to the current side type of the memory DI via the register R6. After this, register R6
is cleared in order to process the memo IJD2 system. (7) Next, note 1 JD2 to D90, the geography of each lineage is the same as step 11 of e-(3) to c-(6) above.
K.I. It is done. Then, when the processing of each system from ME%IJDl to D9 is completed, the register, R11, and RVD"(t
)=ΣGD(electronic-xn)mouth=1 Information regarding the reverberant sound RVDI is obtained. Next, the operation of forming reverberant sound RV with dense delay time intervals will be explained. 4. Operation for forming reverberant sound RV (1) Rounding to read reverberant sound data I RVD' (t - Fl ) from memory MDO 11 hours ago, DLa
SDL. DLk: DLMD L3:l" (LATCH) L2: St' (LATCH) n,
The latte control signals L3, Ll with contents, memory number information DLm and memory type information DLk are output from the control signal output register s03. 19, address information 11DM-ADH for the memory MDO is formed in the address information output circuit 30I in the same way as in steps c-4) above.
Data from JMDO 71 hours ago RVD 1 (z-yt
) appears one after another. Then, this data 1vp1(t −
yt) crawl yf191 to jyfkudzu fLh. (2) Next, the data RV latched into the latch 191
D” (t=yl), vjiJ/R11 output data/
RVDI(1)? In order to calculate the coefficient 1.plKs, -RVDI(Ryu-Fl)+RVD"(t) and store the calculated value in the register 812, first, the output data/RVD" of the register 111 is latched. 404 After K transfer is canceled, MU Dl[l[@]: MUDI CIII@]!1L1: 8
BLEC'r(B)sty, : (7)=
)・■+ side) Select control signal +1
LI, arithmetic control signal CTL and address information ADR (Ka) for reading coefficients are sent to the control signal output register 303.
As a result, the arithmetic circuit 402 receives the above-mentioned e − (6)
In the same way as in the step , the coefficients . and .are supplied to the arithmetic operation input (2), and the data RVD' (f ys ) are supplied to the operation input (3). As a result, the arithmetic circuit 402 (
Output the calculated value (g) of 1@・RVD"(t-yt)+RVD"(t) to This calculated value (1) is then stored in the register R12 in the next step. (3) Next, the contents of the register xlR12 r K, e-RVD
I(t-〆+RVD'(rounding to multiply 0J by the coefficient, first the contents of register R12 are transferred to the latte 404, MuDB(Km,: MuDRY:Kn)!ILI
; lI] cLfficT's first CTL:
Select control signal 8L1 with the content shown in (g)=(4)・in). The arithmetic control signal CTL and the address information DR [Km] for reading coefficients are sent to the control signal output register 30.
Output from 3. As a result, the coefficient Kms is supplied to the calculation input (1) of the calculation circuit 402, and the data rKmo-RVD'(
1-Fl)+RVD'(t) J is calculation input (3)
It is supplied to As a result, the arithmetic circuit 402 calculates (a)=(4)・Flash=Kg@” (KH”RVD’(t-F+)×RV
The calculated value (a) indicated by D'(t) is output. This calculated value (7) is stored in register RIB in the next step.
is memorized. (4) Next, add the contents of register R13 and the data 71 hours ago RVD'(t-Fl) (latched in latch 111 at the X step of 0d-(1) mentioned above). In order to store the added value in the i-raster R13 again, the contents of the register 113 rKss(Ks*・RVD'(t-
ys)+RVD”(*))J is latte 404
Transferred to and after mourning, 8L1: 5lljllCCT
)CTL; (a) - (to) + (to) select control signal 8L1. The calculation control signal CTL is output from the control signal output register 303 IP. ? :, n), the arithmetic circuit 402 is (A) - (B
) + (2) = RVDl (dragon-yl) +Kn ・(Kn 4VD' (t-yl) +]lV
In the next step, this calculated value (1) is stored in the register R13 and output as **sound information 11VD''. Next, the contents of Register Tsubasa 12 "K Gen. RVD' (
t-Fs) +RVD'(t)'' is used at the 9th sampling time (t+yx) delayed by 11 hours, the contents of the register 112 correspond to the current timetable type of the memo IJMDO and are written to the 9th address t2. (6) After this, in the yt time interval, all the sound sounds R
VD'' and 1lVD'' are formed in the same manner. Incidentally, in the practical example shown in FIG. 5 (FIG. 6), a band pass filter BPF is provided, but this may be omitted if necessary. In addition, as shown in the functional block diagram in Figure 7, the output data of the memory DIG is passed through the bypass filter HPF, bandpass filters li'F and O.
- Divide into 3 series of same wave number bands using Hass filter LPF @1! The II reverberation sound forming section 2000 may form different reverberation sounds for each of the several bands. This can be easily achieved by simply changing the contents of the control program. In this way, the reverberation sound adding device of this practical example uses a gage digital memory as a delay element. ξ, which generates reverberant sound of the same quality. Another advantage is that the reverberation time can be freely changed by changing the address interval of the gage digital memory. Also, the first
8 [As shown in 1, one sample period T and two time periods! The first step to the 96th step of the control program in the time period T and 01 are rounded to form the first series of reverberant sound, and the 97th step of the control program in the time period T. If steps 192 to 192 are rounded t to form the second series of reverberant sounds, one reverberant sound adding device can form two series of reverberant sounds in a time-sharing manner, simplifying self-configuration. can. In this case, the musical tone data 1 b DB (J
G D v t JG D A ) > and the second series of musical tone data GDs (JGD 靜, XGDi)
9), each series of musical tone data GD1. G
The latch 11, 111 provided corresponding to D is latched by the latch control signals 1, 5, L6 outputted from the register SO1 (Fig. 5) as a control signal output, and this latch @fL Nine musical tone data GDI * GD
One side of I is selected in time-division by the select control signal 1iL5 outputted from the control signal output register sOs in the controller DC. On the other hand, 92
Regarding the reverberant sound f-1 (mcH(t)*RVD'') of the series, as shown in Fig. The reverberant sound data is latched by latch control signals L7 and L8 in latches 17 and 17F, respectively, and the latched data is output as reverberant sound data of each series. , 8m is used to form musical tone signals for each sound generation channel at a high sampling frequency, but in the reverberation sound addition device 9 and 10, reverberant sound signals are formed at a sampling frequency equal to that for forming musical tone data ■, GDa, and GDm. There is no need to perform the formation.For example, if the musical sound data is formed by sampling at the same wave number of 50KHz, the number of samplings of about 25KHm is sufficient for the formation of the reverberant sound.Therefore, as shown in Fig. 20, Musical sound data achiemulator (11A, 11iB) and reverberation sound addition device 1 (1
・) A sampling rate conversion circuit 1 is provided between the
Circuit・4rT11 formed by (1・mu,111)K
'J11f -I JGD+o (JGDLp, zG
DAIΣGDI) may be set to a low rate, that is, the !ing signal T's (Fig. 3(d)) of 591:IIs is output from the frequency dividing circuit 111AK for 172 minutes to 25 sections Hs. The sampling pulse Ts of musical tone data ΣGDtr (ΣGD
LplΣGDA. ΣGDI) is sampled and held by the latte 18C, and the sampled and held output of the jin is supplied to the reverberation sound adding device 5C10). By doing so, it is possible to reduce the memory capacity when forming reverberant sound in the 9% reverberant sound adding device 8 (10). The purpose of the digital filter is to remove aliasing noise components when converting the sampling rate, and it may not be necessary depending on the same wave number band of the musical tone signal. By the way, when adding multiple channels of reverberant sound with different characteristics, if a dedicated reverberant sound forming circuit or reverberant sound forming parameters are prepared for each channel, the scale will become large. If the circuits or parameters common to the reverberant sound are shared by each channel, a small-scale configuration can be achieved. As explained above, the electronic musical instrument according to the present invention is provided with a plurality of reverberation sound addition channels corresponding to each of the plurality of keyboards or musical sound signal generation devices, and the reverberation characteristics of each reverberation sound addition channel can be arbitrarily set. This makes it possible to add a different reverberation sound to each keyboard or to each series of musical tone signal generators, thereby further enhancing the performance effect. In this case, if a digital memory is used as the reverberation sound adding device, 8/
Reverberation sound with a good N ratio and whose reverberation characteristics can be easily changed can be added.

[Brief explanation of drawings]

Figure 1 is a block diagram showing an example of the electronic musical instrument invented by Jin, Figure 2 is a circuit diagram showing a specific example of the musical tone data accumulator in Figure 1, and Figure 3 is a rounded time chart explaining its operation. , Figure 4 is a plotter diagram showing another example of the electronic musical instrument according to the present invention, Figure 6 is a block diagram showing an example of the reverberation sound adding device used in this invention, and Figure 6rlA is a plotter diagram showing another example of the electronic musical instrument according to the present invention. Functional KN horizontal plotter diagram, Figures 7 and 8m are block diagrams showing the basic configuration of the delay circuit, and Figure 9 shows the delay n of Figure 7.
10 is a characteristic diagram of the early reflected sound generated in the embodiment of FIG. 5, and FIG. 11 is a diagram showing the same wave number characteristics of a delay circuit having a comb filter configuration. , FIG. 12 and FIG. 13 are characteristic diagrams of the reverberant sound that whispers in the embodiment of FIG. 5, FIG. 14 is a diagram showing the structure of the data memory in the actual example of FIG. 5, and FIG.
1. Figure 16 is a diagram showing the structure of the delay length data memory in the real power example of sw4. llC A functional block diagram showing another practical example of the reverberation sound adding device according to the present invention, FIG. 18 is a diagram showing time divisions when the reverberation sound adding device is used in a time division manner, and FIG. 19 is an input circuit in that case. FIG. 30 is a diagram showing an example of a sampling rate conversion circuit. 1...Upper keyboard, 2...Lower keyboard, 3...Pedal keyboard, -9.mu, 1...Tohyu No. 1 generation circuit,
8. Illum, 161... Musical sound data achiemulator, Mouth, 10... Reverberation sound addition device, 1000...
...Early reflected sound formation section, 2000...TSL reverberation sound formation section, aooo ...Second reverberation sound formation section, B
PF...Band pass filter, 19...Storage unit, 20...Time information generation unit, 30...Address information generation unit, 40...Arithmetic unit Patent applicant Nippon Musical Instruments Tenzo Co., Ltd. Agent Kazumi Yamakawa (and 1 other person) Section 9 Figure 10 Figure 11! il1Figure 12Figure 13Figure 14Figure 00

Claims (1)

[Scope of Claims] (1) A plurality of keyboards, a musical tone signal generation sequence that generates digital musical tone signals corresponding to the pressed keys of each of the keyboards, and a keyboard that generates digital musical tone signals corresponding to the pressed keys of each of the keyboards. This electronic musical instrument is equipped with two digital FFI reverberation sound addition channels that add reverberation sound with different characteristics. 6) - The digital reverberation sound addition channel includes a digital memory that sequentially stores digital musical sound signals with predetermined sampling synchronization, and a delay time information that generates delay time information that determines the delay time of the reverberation to be generated. raw means and the above-mentioned sample
! Based on the signal that determines the period and the delay time information, the address information for storing the digital musical tone signal sampled at the current time in the digital Ilume peak 9, and the time corresponding to the delay time information before the current time. and address information generation means for generating address information for reading out the digital musical tone signal stored in the digital memory, and converting the digital musical tone signal read out from the digital memory into an analog signal and then generating it as a reverberant sound. An electronic musical instrument according to claim 1, characterized in that: (3) Musical sounds for the keyboard and the pressed keys of this keyboard! ! A musical tone signal generation device that generates a plurality of series of digital musical tone signals with different base frequencies, and a plurality of digital reverberation sound addition channels that add and output reverberant sounds with different characteristics for each series to the digital musical tone signals of each series. Equipped with an electronic musical instrument.