JPS63169695A - Musical sound generator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention samples a sound signal input from the outside and stores it in a memory, and then samples the waveform sample data stored in this memory in response to a key operation, etc. Regarding a sampling-type musical tone generation device that generates musical tones by reading them at a desired pitch, in particular, the present invention immediately detects the final address of waveform sample data stored in a memory, and uses the final address as an end point or a starting point. The present invention relates to a musical tone generating device that can immediately respond to readout control.

[Conventional technology]

As a sampling type musical tone generating device, there is one disclosed in Japanese Patent Publication No. 33199/1983, for example.

In such a conventional sampling-type musical tone generator, a storage area for musical waveform sample data for one tone is determined in advance in the memory, and when reading data, all addresses in this fixed storage area are read out. It has become.

Furthermore, in Japanese Patent Publication No. 61-47435, in order to prevent noise from appearing at the beginning of repeated reading when repeatedly reading out sampled waveform data of multiple periods, zero crossing is set at the beginning of the multiple periods. It has been disclosed that the zero-crossing address is detected and used as a base address for repeated reading. The zero-cross detection method for this purpose was to write sampled waveform data of multiple periods into a memory, and then read and analyze the data.

[Problem that the invention seeks to solve]

In a sampling type musical tone generator, the waveform data stored in the memory is read out not only once in the forward direction, but also repeatedly read out in the forward direction many times, read out once in the reverse direction, or read out in the reverse direction many times. It has been considered to perform readout in various ways, such as repeated readout, or readout once in the forward direction and then readout once in the reverse direction, to produce musical tones based on sampled sounds in various variations. In that case, in the former technique, a certain storage area of the memory is read out over all addresses, so if the sampled sound is stored only in a part of the storage area, blanks in the pronunciation may occur during repeated reading. Problems arise, such as the period being too long and the sound generation not starting immediately during backward reading.

To solve this problem, detect the actual final address of the external sound waveform sample data stored in memory,
It is desirable to read out the waveform sample data in the memory in the forward or reverse direction using this final address as the end or starting point.

In that case, it is conceivable to detect zero crossings of the waveform data and detect the last zero crossing detection address as the final address.

By the way, the zero-crossing detection shown in the latter prior art involves writing the sampled waveform data into memory and then reading it out and analyzing it, which takes time and makes it difficult to immediately transition to a state where sound can be produced. I can't.

Therefore, if you want to check the sampled sound by immediately reading out the sampled waveform data in an arbitrary read mode immediately after writing it into the memory, this cannot be done.

This invention has been made in view of the above-mentioned points, and involves simultaneously detecting the actual final address of external sound waveform sample data written to the memory in parallel with the writing operation, and using this final address as the end or starting point of the memory. It is an object of the present invention to provide a musical tone generating device that can perform various types of read control such as reading waveform sample data in the forward direction or in the reverse direction immediately after writing.

[Means for solving problems]

A musical sound generation device according to the present invention includes an external sound sampling means for sampling a sound signal inputted from the outside, a readable and writable storage means for storing waveform sample data, and a sound signal sampled by the external sound sampling means. write control means for writing waveform sample data into the storage means; zero-crossing detection means for detecting zero-crossings of the sound signal or the waveform sample data; and writing control means for writing waveform sample data into the storage means every time a zero-crossing is detected by the zero-crossing detection means. final address detection means for storing a data write address and detecting the last address stored when writing is completed as the final address of the waveform sample data; and a final address detected by the final address detection means. readout control means for reading out the waveform sample data of the storage means in a forward or reverse direction as an end point or a starting point, and generating a musical tone signal corresponding to the waveform sample data read from the storage means. It is something.

This is illustrated in Figure 1, where 1 is an external sound sampling means, 2 is a storage means, 3 is a write control means, 4 is a zero cross detection means, 5 is a final address detection means, and 6 is a readout control means. It is a means.

[Effect]

The sound signal input from the outside is sent to external sound sampling means 1.
The waveform sample data of the sampled sound signal is written into the storage means 2 under the control of the write control means 3. During and in parallel with this write operation, the zero cross detection means 4 detects the zero cross of the waveform sample data provided from the external sound sampling means 1 to the storage means 2. Note that this is the same even if zero crossings are detected from the sampled sound signal itself. The final address detection means 5 stores the write address of the waveform sample data in the storage means 2 every time a zero cross is detected by the zero cross detection means 4, and when the writing of the waveform sample data is completed, the last stored address is stored. is detected as the final address of the waveform sample data. The final address detected by the final address detection means 5 is used by the order control means 6 to read out the waveform sample data of the storage means 2 in the forward or reverse direction using this final address as the end point or starting point. A musical tone signal corresponding to the waveform sample data read out from the storage means 2 is generated.

In this way, since the actual final address of the external waveform sample data written in the storage means 2 is simultaneously detected in parallel with the writing operation, the waveform sample data of the storage means 2 can be forward-directed using this final address as the end point or starting point. Various types of read control such as reading in the opposite direction or in the reverse direction can be performed immediately after writing. As a result, performance performance as a sampling type musical tone generation device can be improved.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 shows the hardware configuration of an embodiment of an electronic musical instrument to which the musical tone generator according to the present invention is applied.
Various operations and processes are controlled by a microcomputer section including a program ROM (read only memory) 12 and a data and working RAM (random access memory) 13. The keyboard 14 includes a plurality of keys for specifying pitches of musical tones.

The operation panel unit 15 includes a sampling control operator group 16 for controlling the external sound sampling operation and its readout operation, an envelope control operator group 17 for setting and controlling the envelope waveform of musical tones, and various types of controls. an effect control operator group 18 for setting and controlling musical tone effects;
A group of operators 19 for setting and controlling various musical tones are also provided.

In the sampling control operator group 16, the sampling switch SMPL and the override switch 0VRWR
is a switch that instructs to write the external sound waveform sample data into the data memory 21 in the tone generator section 2o. reverse switch rv
R5 and U-turn switch UTRN and loop switch LO
OP and echo switch ECHO are switches for instructing the performance mode when reading out the waveform sample data stored in the memory 21 and performing the performance.

The sampling switch SMPL is operated to instruct that external sound sampling should be performed.

The override switch 0VRWR is operated to instruct that external sound sampling should be performed in the same way as described above, but it is used to override external sound waveform sample data that has already been stored in the memory 21. This operation is used to instruct to overwrite waveform sample data of another external sound without erasing it (this is called "override"). On the other hand, when sampling is instructed by the sampling switch SMPL, the previously stored external sound waveform sample data is erased.

The reverse switch RVR3 is operated to instruct a performance to be performed by reading out the external sound waveform sample data stored in the memory 21 in the reverse direction. This kind of reading is simply called "reverse". In addition, the memory 21
Reading in the reverse direction means reading in order from the address with the largest value. On the other hand, reading the memory 21 in the forward direction means reading data in order from the address with the smallest value.

The U-turn switch UTRN is operated to instruct a performance in which the external sound waveform sample data stored in the memory 21 is read out in the forward direction and then turned back and read out in the reverse direction. This type of readout is simply called a "U-turn".
That's what it means.

In addition, it is possible to select and instruct "U-turn" and "reverse" at the same time. In that case, after reading out the external sound waveform sample data stored in Mekili 21 in the reverse direction, turn it back in the forward direction. read out. This is called a "U-turn reverse."

The loop switch LOOP is operated to instruct repeated reading of external sound waveform sample data stored in the memory 21. This kind of reading is simply called a "loop".A normal "loop" is a memory 2
The external sound waveform sample data stored in step 1 is repeatedly read out in the forward direction.

This is called a "normal loop."

It is possible to select and instruct "loop" and "reverse" at the same time, and in that case, the external sound waveform sample data stored in the memory 21 is repeatedly read out in the reverse direction. This is called a "reverse loop."

It is possible to select and instruct "loop" and "U-turn" at the same time. In that case, after reading out the waveform sample data of the external sound stored in the memory 21 in the forward direction, it is read out in the reverse direction. repeat. This is called “
It's called a U-turn loop.

It is possible to select and instruct "loop", "U-turn" and "reverse" at the same time, in which case the memory 21
After reading out the external sound waveform sample data stored in the memory in the reverse direction, the data is repeated in the forward direction.
This is called a ``U-turn reverse loop''.

A list of performance modes as described above is shown in FIG. There are eight performance modes, and each mode is distinguished by symbols M1 to M8. The left column shows the mode name, which corresponds to the names mentioned above. Therefore, the conditions under which each mode is selected will be clear from the above. Note that the "normal" mode M
1 is a mode in which the external sound waveform sample data stored in the memory 21 is read out only once in the forward direction, and this "normal" mode is selected when no special modes M2 to M8 are selected.
mode. The right column schematically shows the readout state of waveform sample data from the memory 21 in each mode, and the direction of the arrow indicates whether the readout is in the forward or reverse direction. Mode M3 related to “loop”. M
5. M6. At M8, reading as shown is repeated. The starting point in forward reading is a predetermined start-address, and the ending point is a predetermined end address. vice versa,
The starting point in backward reading is the end address, and the ending point is the start address.

The start address and end address serve as reference addresses that indicate the starting point or ending point in forward or backward reading. In this embodiment, one reference address, or start address, is always fixed at a predetermined initial address (for example, address 0), and the other reference address, or end address, corresponds to the final zero-crossing address of the sampled waveform data. It is designed to change as appropriate. Further, the value of this reference address, that is, the end address, can be increased or decreased as appropriate by the performer. In this embodiment, the value of the end address is increased or decreased in mode M3. M5. This is possible when M6° to M8.

In order to instruct the sampling control operator group 16 to increase or decrease the above-mentioned end address.

An increase switch INC and a decrease switch DEC are provided. The address value increases according to the operation of the increase switch INC, and the address value decreases according to the operation of the decrease switch DEC. In this embodiment, for example, the increase/decrease of the end address by the increase switch INC and the decrease switch DEC is performed not in units of one address but in units of blocks consisting of a plurality of addresses.

Here, the data memory 2 in the tone generator section 20
An example of the address structure in No. 1 will be explained with reference to FIG. The entire range of addresses for storing waveform sample data of external sound for one tone consists of 16 blocks from 0 to 15, and one block consists of 256 addresses. The first address of this entire address range is the start address, and has an address value of O. The end address changes as appropriate in response to the final zero-crossing address of the sampled waveform data. In this flexible embodiment, this end address is also determined on a block-by-block basis. The value of this end address is increased or decreased according to the operation of the increase switch INC and decrease switch DEC.

An echo switch ECHO provided in the sampling control operator group 16 is for selecting an echo effect. What is the echo effect here?

Automatically sets the performance mode to "Loop" and automatically lengthens the release time of the volume envelope of the generated musical sound (
For example, set this to the longest.

The purpose is to repeatedly read out sampled waveform data from a memory 21 and to cause the musical tone to be repeatedly sounded while gently attenuating the volume envelope of the musical tone signal corresponding to the read out waveform data.

The all-cancel switch CANSEL provided in the sampling control operator group 16 cancels all or predetermined various data set, selected, changed, or adjusted on the operation panel section 15 in relation to the sampled waveform sample data. However, the contents of these data are manipulated to return them to the state they were in when they were first sampled.

In other words, it is for canceling the edited contents of various data edited in relation to the sampled waveform sample data and returning to the initial state before editing. By being able to cancel the edited content and return to the initial state before editing, it becomes possible to freely edit without fear of failure, and editing functions related to sampled waveform sample data are now available. can be improved.

Envelope control operator group 1 in operation panel section 15
Reference numeral 7 includes operators for setting and controlling the characteristics of the volume envelope waveform to be applied to the waveform sample data read from the data memory 21, such as A, D, S, R, attack time, decay time, which determines the characteristics, It consists of operators that set and control the sustain level and release time, respectively.

The effect control operator group 18 on the operation panel section 15 includes operators for setting and controlling musical sound effects such as vibrato, tremolo, and reverb, for example.

The tone generator section 20 has a function of sampling a sound signal input from the outside through a microphone 22 and converting it into digital waveform sample data, a function of writing the sampled digital waveform sample data into the data memory 21, and a function of writing the sampled digital waveform sample data into the data memory 21. It has a function of reading waveform sample data from the data memory 21 in response to key presses, etc., and a function of controlling the volume envelope of the read waveform sample data and adding various musical sound effects. The digital musical tone signal generated from the tone generator section 20 is converted into an analog signal and then provided to the sound system 23.

The timer beep circuit 24 is a circuit for generating a beep sound for a certain period of time when sampling of external sound is started. The beep sound generation time is, for example, about 300 ms, and the beep sound starts in response to the operation of the sampling switch SMPL, and when it ends, the beep end pulse BPE
Generates ND. Based on the beep end pulse BPEND, the tone generator section 20 starts a sampling operation.

Key scanning and sound generation assignment processing for detecting key presses and key releases on the keyboard 14, scanning for detecting operation of switches and the like on the operation panel section 15, and lighting/extinguishing processing of indicators, etc., and processing on the tone generator section 20. Various processes such as writing and reading control of sampling data are executed by the microcomputer section.

Among the processes executed by the microcomputer unit, examples of flowcharts of processes related to the present invention are shown in FIGS. 8 to 19.

Data and working R used in connection with this process
An example of the contents stored in AM13 is shown in FIG.

SMPFLG is a sampling flag and becomes Ig I 11 in normal sampling mode.

0VWFLG is an override sampling flag and becomes '1' in the override mode.

RVFLG is a reverse flag, and becomes it 1 to in the "reverse" performance mode. This flag is inverted from "1" to a Ore or from 1'0 to "1" every time the reverse switch RVRS is turned on.

UTFLG is a U-turn flag, and becomes "1" in the "U-turn" performance mode. This flag is inverted from "II" to "0" or from "1" to "1" every time the U-turn switch UTRN is turned on.

LPFLG is a loop flag, and becomes "1" in the "loop" performance mode. This flag changes from l(I II to (10I
I or "OII" to "1".

ECFLG is an echo flag, and becomes "1" when an echo effect is selected. This flag changes from “1” to “O” or “
Inverted from "0" to "1".

L P F L G B is the loop flag buffer, and when the echo effect is selected, the loop flag LPFL
This is to save the immediately previous contents of the loop flag LPFLG in order to forcibly set the contents of G to "1". The contents saved in this buffer LPFLGB are
Loop flag LP when echo effect is no longer selected
Returned to FLG.

NKEY is a new key code register, which stores the key code of a newly pressed or M-pressed key.

KCODE is a key code register that stores the key code corresponding to the musical tone currently being produced.

ZCRADB is a zero-crossing address buffer,
It stores the final zero-crossing address of waveform sample data sampled externally.

LPADB is an end address buffer that stores the aforementioned end address.

ATB is attack time buffer, DTB is decay time buffer, SLB is sustain level buffer, R
TB is a release time buffer 1, an attack time set and controlled by an envelope control operator group 17;
It stores data on decay time, sustain level, and release time.

RTBUF is the release time storage buffer, when the echo effect is selected the release time buffer RT
This is to save the immediately preceding contents of the release time buffer RTB in order to forcibly set the contents of B to the longest time. The contents saved in this buffer RTBUF are returned to the release time buffer RTB when the echo effect is no longer selected.

Areas are provided in the data and working RAM 13 for registers, flags, or buffers as described above. Also, in the data and working RAM 13, there is a group of effect control operators 18 in the operation panel section 15.
and other areas for storing operation detection data of the operator group 19, and other data and working areas.

A detailed example of the tone generator section 20 is shown in FIG.

In the tone generator section 20 of FIG. 6, an interface 26 is provided to exchange data with the microcomputer section via the data bus 25. Interface 26 includes a buffer register. The data given from the microcomputer section is sent to the tone generator section 2 via the interface 26.
0 to a predetermined circuit. Further, data output from a predetermined circuit within the tone generator section 20 is provided to the microcomputer section via an interface 26 and a data bus 25.

To briefly explain the main circuits in the tone generator unit 20, the data memory 21 has an address structure as shown in FIG. The read mode is set, and if the parameter is 0'', the write mode is set. AD is an address input, and DT is a data input/output terminal.

The external sound signal picked up by the microphone 22 is converted into a clock pulse φ□ by the analog/digital converter 27.
sampled and digitally converted. The digitally converted waveform sample data is sent to an adder 28 for one overwriting. The signal is applied to the data input/output terminal DT of the data memory 21 via the latch circuit 29 and the gate 30.

Further, the waveform sample data output from the analog/digital converter 27 is given to a rising edge detection circuit 31,
The rise of the sound is detected. A trigger pulse TRG is output in response to the detection of the rise of the sound. This trigger pulse TRG
is used as a signal to instruct the timing to start writing waveform sample data to the data memory 21.

Further, the waveform sample data output from the analog/digital converter 27 is applied to a zero cross detection circuit 32, where a zero cross is detected. In this embodiment, in order to simplify the configuration of the zero cross detection circuit 32, the level of the waveform sample data is determined to be within a predetermined zero judgment range (range of ±α of the zero level, where α is an appropriate level). is detected, and a zero cross detection pulse ZCR is output when the zero determination range is exceeded. The zero-crossing detection pulse ZCR is applied to the latch control input of the zero-crossing address latch circuit 33, and the write address when the zero-crossing is detected is latched into the latch circuit 33.

Since the zero cross detection pulse ZCR is generated every zero cross of the waveform sample data, the zero cross address of the latch circuit 33 is rewritten many times, and the data finally left in the latch circuit 33 is the final zero cross address of the waveform sample data. It is.

The note clock generation circuit 34 has a new key code NK.
Node clock pulse φ in response to C. occurs. The new key code NKC is for specifying the write rate or read rate of the data memory 21, and is set to a key code of a predetermined reference pitch (for example, A4 note) at the time of sampling, and is used to specify the write rate or read rate of the data memory 21. Changes will be made accordingly. Node clock pulse φ. are frequency-divided by a factor of 1 and 2 by the frequency divider 35, and the node clock pulses φ4. φ2 is obtained. The phase-advanced note clock pulse φ□ is inputted to the count clock CLK of the address counter 37 via the AND circuit 36. The slow phase note clock pulse φ2 is generated by the NAND circuit 4.
Human power R/W for reading and writing control of data memory 21 through 4
and control its read/write mode.

As described below, the sampling mode (normal sampling mode or override sampling mode)
At this time, the signal SMI or 8M2 becomes "1" and the signal 111? is sent from the OR circuit 45 to the NAND circuit 44. + is given. As a result, the NAND circuit 44 inverts the delayed note clock pulse φ2 and applies it to the read/write control input R/W of the data memory 21. Therefore, the data memory 21 is in the read mode when the leading phase note clock pulse φ□ is 11", and in the write mode when the slow phase note clock pulse φ2 is 1", and is time-divisionally operated within the time of one address. The read/write mode switches. This is a procedure for the override sampling mode, which will be described later. In addition, in various performance modes M1 to M8, the signal SMI
and 8M2 is It OII, the NAND circuit 44 always outputs 51", and the data memory 21 is always in the write mode. Note that the address counter 37 counts the note clock pulse φ□ whose frequency is divided by 1/2. , the note clock generation circuit 34 generates a note clock pulse φ with twice the frequency of the target note clock pulse ψ The preset pulse PRP that is generated and applied to the preset control input PR
The preset data applied to the preset data input PRD is preset in accordance with the preset data input PRD, and the node clock pulses φ applied to the count clock input CLK are counted using this preset value as a starting point. The address counter 37 is an up/down counter and has a direction indication signal DIR.
When is 1'', up-counting is performed, and when pa is 0'', down-counting is performed.

The output of the address counter 37 is applied to the address input AD of the data memory 21 and also to the comparator 38, and the higher 4 bits are input to the zero-cross address latch circuit 33. The address signal consists of 12 bits, the upper 4 bits identify each block from 0 to 15, and the lower 8 bits identify 256 addresses within one block. By latching the upper four bits of the address signal in the zero-crossing address latch circuit 33, the zero-crossing address is detected in block units. Latch circuit 33
The zero-crossing address data ZCRAD latched in is supplied to the microcomputer section via the interface 26.

Comparator 38 is for detecting whether the address signal generated from address counter 37 has reached the end point. When the address signal is progressing in the forward direction (that is, increasing), the end address data LPAD is selected by the selector 39 and stored in the end point address register 40, and the end address data LPAD stored in this register 40 and The comparator 38 compares the address signal with the address signal, and when the two match, outputs the end pulse END (
(set to “1”). On the other hand, when the address signal is progressing in the opposite direction (that is, decreasing), the selector 39 selects initial address data in which all 12 bits are "ON" and stores it in the end point address register 40. A comparator 38 compares the initial address data stored in the address signal with the address signal, and outputs an end pulse END when the two match.

Selection control of the selector 39 is performed by a T-flip prop 41
This is done in response to the direction instruction signal DIR output from the.

When this direction instruction signal DIR is 111 II, that is, when instructing a forward change in the address, the B input is selected, and when it is '0'', that is, when instructing a reverse change in the address, the 6 input is selected. Select.

As will be described later, the end address data LPAD is given from the microcomputer section based on the above-mentioned zero-cross address data ZCRAD, and is 4-bit data that indicates the end address in units of blocks. This block unit end address data LP
In order to convert AD into address units, an 8-bit all-par 1'' is added to the lower part of AD and is applied to the B input of the selector 39.As a result, the end address data LPAD indicates the final address in the block. shall be shown.

The output of the selector 42 is added to the preset data PRD of the address counter 37. This selector 42 is
Contrary to the selector 39 described above, when the direction instruction signal DIR is "1", that is, when instructing a forward change of the address, the initial address data of all 12 bits #Oj# added to the input to 60'' is selected. In other words, when instructing a reverse change in address, select the end address data LPAD that is added to the B input.This end address data LPAD also has 8 bits of all u l u in its lower order.
is added to indicate the final address within the block.

Note that the end point address register 40 is preset at the same time as the address counter 37a by the same pulse PRP as the preset pulse PRP applied to the preset control input PR of the address counter 37.

Load end point address data from selector 39.

T-flip-flop 4 for generating direction indication signal DIR
1 is sampling mode or various performance modes M
1 to M8, as will be described later.

The generation conditions of the preset pulse PRP for presetting the address counter 37 are also controlled in accordance with the sampling mode or various performance modes M1 to M8, as will be described later.

The AND circuit 36 which controls adding the note clock pulse φ□ to the count clock CLK of the address counter 37 is controlled in accordance with the output signal of the flip-flop 43. The state of this flip-flop 43 is controlled as described later in accordance with the sampling mode or various performance modes M1 to M8.

The waveform sample data read from the data memory 21 is input to the multiplier 46, and the envelope generator 47
is multiplied by the envelope waveform data given from .

The envelope generator 47 generates an envelope waveform having a shape set based on attack time data AT, decay time data DT, sustain level data SL, and release time data RT provided from the microcomputer unit via the interface 26, and generates a key-on pulse KONP. , ○KONP and key-off pulse KOFP, 0
0 generated in response to KOFP As is well known, an envelope waveform portion consisting of attack, decay, and sustain is generated in response to a key-on pulse, and a release portion is generated in response to a key-off pulse. Here, one key-on pulse KONP and key-off pulse KOFP are given based on normal key press operations, and the other key-on pulse 0KONP and key-off pulse 0K
OFF is given to immediately and automatically generate the musical tone that has just been sampled.

The waveform sample data whose volume envelope has been controlled by the multiplier 46 is supplied to the digital/analog converter 48, where it is converted into an analog signal, and finally supplied to the sound system 23. It is also applied to an effect circuit 49 as appropriate to provide musical sound effects such as reverb, tremolo, and vibrato.

Next, various operations of this electronic musical instrument will be explained with reference to FIGS. 8 to 19.

FIG. 8 shows the main routine. First, in the key scanning process, each key on the TN board 14 is scanned, and the pressed keys and M! Detect I. A predetermined process is executed in response to this detection. Here, when a new key press is detected, the first
The key-on event routine shown in FIG. 2 is executed, and when a new key release is detected, the key-off event routine shown in FIG. 13 is executed.

In the sampling control operator scanning process, the operation of each switch of the sampling control operator group 16 is detected, and a predetermined process is executed in response to this detection. here,
When it is detected that the sampling switch SMPL has changed from off to on, the sampling event routine shown in Figure 9 is executed and the override switch 0VRWR is turned on.
When detecting that the switch has changed from off to on, the override event routine shown in FIG. 10 is executed. Also,
Beep end pulse BP given from the timer beep circuit 24 when the beep sound at the start of sampling ends
END is detected, and in response to this detection, the timer beep end event routine of FIG. 11 is executed. Furthermore, when sampling of the external sound is completed, the sampling end event routine shown in FIG. 14 is executed in response to a sampling end signal SMPEND given from the tone generator section 20 as described later. Also, reverse switch RVR3, U-turn switch UTRN, loop switch LOOP, echo switch ECHO1 increase switch l
When it is detected that the NC1 decrease switch DEC and all cancel switch CANSEL have changed from OFF to ON, the reverse event routine, U-turn event routine, loop event routine, echo event routine, and increase event shown in FIGS. 15 to 19 are executed. A routine, a decrease event routine, and an all cancel event routine are executed.

In the envelope control operator scanning process, the operation of each operator of the envelope control operator group 17 is detected,
A predetermined process is executed in response to this detection. Here, the attack time, decay time, sustain level, and release time data set and controlled by the envelope control operator group 17 are stored in the attack time buffer ATB, decay time buffer DTB, and sustain level buffer SL.
B and release time buffer RTB.

In the effect control operator scanning process, the operation of each operator of the effect control operator group 18 is detected, and a predetermined process is executed in response to this detection. In the other operator scanning process, the operation of each operator of the other operator group 19 is detected, and a predetermined process is executed in response to this detection.

When performing a normal sampling operation, first turn on the sampling switch SMPL. In response to this, the sampling event routine of FIG. 9 starts. Here, the sampling flag SMPFLG is set to "1",
Other flags 0VWFLG-ECFLG are reset to "0" (step 1o1). Next, the second key code N
A key code of a predetermined reference pitch (for example, A4 tone) is sent as KC to the tone generator section 2o (step 1).
02). Then, a start trigger signal is sent to the timer beep circuit 24 to generate a beep sound (step 10).
3). In addition, in the flowchart, the tone generator section 20 is indicated by TG.

The timer beep circuit 24 emits a beep sound for a predetermined time (for example, 300 ms) in response to this start trigger signal, and when this time elapses, a beep end pulse BP is emitted.
Outputs END.

Referring to FIG. 6, in the tone generator section 20,
A note clock pulse φ of a reference pitch (A4 tone) is generated from the note clock generation circuit 34 in response to the given new key code NKC. occurs. During the beep sound,
This note clock pulse is now stably generated and preparation for sampling is completed. In this way, the beep serves to signal that sampling is ready.

The routine of FIG. 11 starts in response to the beep end pulse BPEND. In step 104, it is confirmed that the sampling flag SMPFLG is "1", and
Go to step 105. Here, the sampling mode signal SMI corresponding to 1 normal sampling mode is set to “1”.
”, and the sampling mode signal SM2 corresponding to the override sampling mode is set to “O” and sent to the tone generator section 20.

In the next step 106, data to be given to the tone generator section 20 is initialized as follows and sent to the tone generator section 20. Various mode signals M1 to M8 of the performance mode are set to 1'071. The end address data LPAD is set to the value "15" indicating the final block. The attack time data AT, decay time data DT, and release time data RT are each set to "0", and the sustain level data SL is set to the maximum value rMAXJ. This sets a direct keying type envelope waveform that maintains a constant envelope level from key-on to key-off. With this direct keying type envelope waveform, musical tones are produced at the same volume level as sampled.

In the next step 107, the contents of the attack time buffer ATB, decay time buffer DTB, sustain level buffer SLB, and release time buffer RTB in the microcomputer section are also initialized to those for setting a direct keying type envelope waveform in the same way as above. In the zeroth step 108, data for various musical tone effects are also initialized to predetermined contents.

On the other hand, after confirming the beep sound, the performer uses the microphone 22 to pick up a desired external sound. Referring to FIG. 6, as mentioned above, the picked up signal is sampled by the analog/digital converter 27,
converted to digital. A rising edge of the sound of the digitally converted waveform sample data is detected by a rising edge detection circuit 31, and a trigger pulse TRG is output in response to the detection of the rising edge of the sound. This trigger pulse TRG is input to an AND circuit 50. “1” of the sampling mode signal SMI is applied to the other input of the AND circuit 50 via the OR circuit 51, and the output of the AND circuit 50 becomes l(1jj) in synchronization with the trigger pulse TRG, which is the sampling mode signal SMI. It is applied as a start pulse SMPST to the set input S of the flip-flop 43 via the OR circuit 52, and is applied to the preset control input PR of the address counter 37 as a preset pulse PRP via the OR circuit 53, and to the end point address register 40. Further, the sampling start pulse SMPST is inputted to the AND circuit 56 via the OR circuit 54, and the sampling mode signal SMI is inputted to the AND circuit 56 via the OR circuit 55-, and the output "1" of the AND circuit 56 is inputted to the T- It is applied to the set input S of the flip-flop 41.

As a result, the direction instruction signal DIR output from the T-flip-flop 41 becomes "1", the selector 42 selects the initial address (all "0") and presets the address counter 37, and the selector 39 selects the final block. The indicated end address LPAD is selected and loaded into the end point address register 40, and the address counter 37 is set to count up. And flip flop 4
3 set output (11jj enables the AND circuit 36, and the note clock pulse φ□ at a rate corresponding to the A4 note is input to the address counter 37.

Thus, in response to the occurrence of trigger pulse TRG.

The address counter 37 starts counting up the node clock pulse φ□ at a rate corresponding to the A4 sound, and the generated address signal starts from the initial address (all "0") and starts at the end address LPAD in the forward direction. Change.

On the other hand, when the sampling mode signal SMI becomes "1", a signal obtained by inverting the note clock pulse φ2 is applied from the NAND circuit 44 to the read/write control manual R/W of the data memory 21, and the data memory 21 , when the phase-leading node clock pulse φ is "1", the mode is read, and when the phase-lag note clock pulse φ2 is "1", it is the write mode, and the read/write mode is switched in a time-division manner within the time of one address. . However, when the sampling mode signal SMI is "1", the sampling mode signal SM2 is "0", the gate 57 for adding the read signal of the data memory 21 to the adder 28 is closed, and the envelope A key-on pulse for generating envelope waveform data from the generator 47 is also not generated (therefore, the multiplier 46 is not connected to the data memory 2).
1 readout signal is cut), the readout has no meaning.

Digital waveform sample data of the external sound output from the analog/digital converter 27 is applied to one input of the adder 28 . The output of the gate 57 is given to the other input of the adder 28, which is "
0'', the digital waveform sample data of the external sound simply passes through the adder 28 and is applied to the latch circuit 29. The latch circuit 29 performs a latch operation at the timing of the note clock pulse φ2, which is the write timing. Note that the analog/digital conversion operation in the analog/digital converter 27 is performed at the timing of the advanced note clock pulse φ.

The output of latch circuit 29 passes through gate 30 and enters data input DT of data memory 21. The gate 30 is controlled by the output of an OR circuit 58 which receives the sampling mode signals SMI and 8M2, and the output of an AND circuit 59 which receives the NO1 to clock pulses φ2. As a result, the gate 30 is opened only in the sampling mode (normal sampling mode and override sampling mode) and only when the note clock pulse φ8 is "1", that is, only at the write timing. In addition, when in various performance modes M1 to M8,
Signals SM1 and 8M2 are “0”, and the AND circuit 59
always outputs "0" and the gate 30 is always closed, so even if noise is picked up by the microphone 22, it can be cut here.

In this way, the digital waveform sample data of the external sound is
At the write timing, the data is input to the data input DT of the data memory 21 and written to the address specified by the address signal given from the address counter 37.

On the other hand, the waveform sample data output from the analog/digital converter 27 is given to the zero cross detection circuit 32, and as described above, zero crosses are detected in parallel with the write operation. In response to the zero-crossing detection pulse ZCH output from the zero-crossing detection circuit 32, the write address when the zero-crossing is detected is latched in the zero-crossing address latch circuit 33. Zero cross detection pulse Z
Since the CR is generated every zero cross of the waveform sample data, the zero cross address of the latch circuit 33 is rewritten many times, and the data finally left in the latch circuit 33 is the final zero cross address of the waveform sample data. be. Therefore, when the sampling is finished,
The final zero-crossing address is already known.

When the write address reaches the final address of the memory 21, the end address LPAD indicating the final address of the final block stored in the end point address register 40 is
The comparator 38 outputs an end pulse END. This end pulse END is input to the AND circuit 60. Since this AND circuit 60 is enabled by the sampling mode signal S M, 111'' from the OR circuit 61, it corresponds to the end pulse END.
1'' is input from the AND circuit 60 to the OR circuit 62 and to the reset input R of the flip-flop 43 via the delay flip-flop 63.The delay flip-flop 63 delays the note clock pulse φ by one clock. One clock after the count value reaches the final address, the flip-flop 43 is reset, the AND circuit 36 is closed, and the node clock pulse φ is stopped.

In this way, the address counter 37 stops counting. Incidentally, since no preset operation is performed at this time, the count value is held at the final value.

In this way, in the sampling mode, data memory 2
Writing is performed over the entire address range from the initial address of 1 to the final address.

End pulse END is applied to AND circuit 64. Since this AND circuit 64 is enabled by 111 I+ of the sampling mode signal SMI from the OR circuit 65, 1'' corresponding to the end pulse END is output from the AND circuit 64, which is the sampling end signal S
It is sent to the microcomputer section as M P E N D. In addition, zero cross address latch circuit 33
The zero cross address data ZCRAD latched in is also sent to the microcomputer section.

Override Sampling To write waveform sample data of a newly sampled sound over the previously sampled sound, turn on the override switch 0VRWR. In response, the override event routine of FIG. 10 is executed. Here, first, override flag 0VWFLG
is set to 1'' and other flags are reset to 'O'''' (step 101a), followed by step 102a.
.

The process at step 103a is the same as steps 102 and 103 in FIG. 9, and an A4 key code is set as the new key code NKC, and a timer beep sound is generated.

When the beep ends, the timer beep end event routine of FIG. 11 is executed as described above. here,
In step 104, the sampling flag SMPFLG
is "0", so the determination is NO and the process goes to step 109. In step 109, the sampling mode signal SM
Set I to "0", set 5M2 to "1",
The signal is sent to the tone generator section 20. After that, steps 106 and 107 are performed as in the normal sampling mode.
．． 108 processing is executed.

In this way, in the override sampling mode, the sampling mode signal SMI is "0", 5M2
is "1", which is the opposite of the normal sampling mode, and the rest is the same as the normal sampling mode.

Referring to FIG. 6, similar to SMI, the sampling mode signal SM2 is an OR circuit 45.51.55.58,
61.65, and in this respect, the tone generator section 20 operates in exactly the same manner as in the normal sampling mode described above. The difference is that the signal SM
2 is applied to the control input of gate 57. As a result, the waveform sample data read from the data memory 21 is input to the adder 28 and added to new waveform sample data provided from the analog/digital converter 27.

That is, as mentioned above, from the OR circuit 45 to the NAND circuit 4
4, a signal obtained by inverting the note clock pulse φ2 is applied to the read/write control R/W of the data memory 21, and the data memory 2
1 becomes the read mode in the first half of one address time, and becomes the write mode in the second half. The waveform sample data of the previously sampled sound read out from the data memory 21 in the first half of one address time is input to the adder 28 through the gate 57 opened by the signal SM2 being "1".
It is added to the newly sampled external sound waveform sample data. The added waveform sample data is latched into the latch circuit 29 at the second half timing of one address time (timing when φ2 is "1"), as described above.
The data is input to the data memory 21 via the gate 30 and written to the corresponding address.

In this way, data obtained by adding the waveform sample data of the newly sampled sound to the waveform sample data of the already sampled sound is written into the memory 21. As described above, when the write address reaches the final address, the AND circuit 64 outputs the sampling end signal SMPE.
ND is generated. Further, as described above, the last zero-crossing address of the newly sampled waveform sample data is finally latched by the latch circuit 33.

The writing rate of waveform sample data in the normal sampling mode and the override sampling mode of the sampling rate is not limited to the standard pitch (A4 tone), but can be changed as appropriate by pressing keys on the keyboard 14.

When a key of a desired pitch desired to be set as the sampling rate is pressed on the keyboard 14, the microcomputer section detects the new pressed key and executes the key-on event routine shown in FIG. 12. In step 110, the key code related to the new key press is stored in the new key code register NKE.
Store in Y.

In the next step 111, the normal sampling flag S
MPFLG or override sampling flag 0
Check whether VWFLG is "1". If YES, that is, either sampling mode, step 112
and write the contents of the new key code register NKEY to the tone generator section 20 as the new key code NKC.
Send to. Based on this, the tone generator section 20
The node clock pulse φ generated from the note clock generation circuit 34 of. (that is, φwork, φ2) corresponds to the pitch specified on the keyboard 14.

In this way, the desired external sound may be sampled after changing the sampling rate to one corresponding to the desired pitch.

Override sampling (') Various overwriting modes are possible depending on the wishes of the JJLfi performer, but
- As an example, the following harmony sampling will be explained.

For example, in the case of a C major chord, first, the sampling rate is set to 04 note, and the 04 note sound signal of the desired tone is sampled externally.

Set the sampling rate to E4 sound, and use the same C4 as above.
Input the sound signal from the outside and perform override sampling. Furthermore, the sampling rate is set to 04 tone, and the same C4 tone sound signal as above is input from the outside for override sampling. Thus, C4,
E4. The sum of the waveform sample data of the three tones of pitch G4 is stored in the data memory 21. In this case, by reading out the waveform sample data from the data memory 21 at a desired pitch rate corresponding to the pressed key, a musical tone signal of a major chord having the pressed key as the root note can be generated.

In this way, for example, override sampling is useful when attempting to play chords with simple key press operations. For example, when the keyboard 14 is divided into key ranges and a chord is to be played in a part of the key range, if the data memory 21 is read in response to a key press in the chord performance key range, the above-mentioned method can be used. You can play simple chords.

As described above, when the sampling end signal SMPEND is generated at the end of writing the external sound waveform sample data, the sampling end event routine shown in FIG. 14 is executed.

Here, first, the zero-crossing address data ZCRAD latched in the zero-crossing address latch circuit 33 of the tone generator section 20 is taken into the zero-crossing address buffer ZCRADB in the microcomputer section (step 113).

As described above, this data ZCRAD indicates the address where the last sample data of the sampled sound is stored in the memory 21.

In the next step 114, it is checked whether the override sampling flag 0VWFLG is "1", and if No, that is, in the normal sampling mode, step 115
Then, the contents of the zero-crossing address buffer ZCRADB are stored in the end address buffer LPADB. In this way, the last zero cross address data of the waveform sample data is sent to the buffer LPA as end address data.
Stored in DB.

Next, the sampling flag SMPFLG and 0VWFL
In order to reset both G to "0" (step 116), the contents of the signal sent to the tone generator section 20 are changed to SMI
and 8M2 are both “0”, Ml is “1”, M2 to M8 are 6
Set each to '0'.

Then, the contents of the buffer LPADB are sent out as end address data LPAD (step 117).

And key-on pulse 0KONP for parrot sound.
is sent to the tone generator section 20 (step 11
8). This key-on pulse 0KONP is used to immediately generate a musical tone corresponding to the sampled waveform sample data immediately after sampling, and to confirm its content.

Processing at the end of override sampling When override sampling is completed, step 114 in FIG. It is checked whether the contents of the zero-crossing address buffer ZCRADB (indicating the final zero-crossing address of the waveform sample data sampled this time) are smaller than the contents of the zero-crossing address buffer ZCRADB (indicating the final zero-crossing address of the waveform sample data sampled this time). If YES, the process advances to step 115 and the contents of the buffer LPADB are rewritten to the current final zero-crossing address data. If NO, the process goes to step 116 via step 120 without performing step 115.

In this manner, in the case of overwriting, the final zero-crossing address of the data with the longest address length among the plurality of overwritten external sound sampling data is stored as end address data in the buffer LPADB.

Note that in step 120, the end address buffer L
Transfer the contents of PADB to zero-cross address buffer ZCRA
Set it in DB. This means that among the overwritten external sound sampling data, the final zero-crossing address of the currently sampled data (this was stored in the buffer ZCRADB at the previous step 119) is higher than the final zero-crossing address of the previously sampled data. Because of the small size, it was found that the final zero-crossing address could not be specified from the perspective of the entire overwritten data, so the true final zero-crossing address was determined from the perspective of the entire overwritten waveform sample data. This is to store the contents of the buffer LPADB specifying the buffer ZCRADB. As will be described later, during all cancel processing, it is necessary to return the contents of the zero cross address buffer ZCRADB to the end address buffer LPADB, and return the contents of the buffer LPADB to the true final zero cross address. It is necessary to save the final zero-crossing address in the buffer ZCRADB. For this purpose, the process of step 120 is inserted.

Direct sampling - When writing of externally sampled waveform sample data is completed, step 11 in Fig. 14 is completed, as described above.
Key-on pulse 0KONP for parrot sound by 8
is generated automatically.

Referring to FIG. 6, in the tone generator section 20,
This key-on pulse 0KONP for parroting sound is input to the envelope generator 47 via the OR circuit 66, and is also input to the OR circuits 52, 53, 54 and the set manual S of the flip-flop 67.

Also, by the process of step 117 of the aforementioned sampling end event routine (FIG. 14).

The performance mode signal M1 is set to 1'1'', and this signal M1 is applied to the OR circuits 55 and 61 of the tone generator section 20.
．． 68.

The condition of the AND circuit 56 is established by the key-on pulse 0KONP and the signal M1 being "1", and the T-flip-flop 4
1 is set, and the direction indication signal DIR becomes "1".

Also, in response to the key-on pulse 0KONP, the OR circuit 53
A preset pulse PRP is output from. As a result, the selector 42 selects the initial address data (all 'O').
) is selected and preset in the address counter 37, and end address data LPAD is selected by the selector 39 and loaded into the register 40. Also.

Flip-flop 4 according to key-on pulse 0KONP
3 is set, and the address counter 37 starts counting. In this case, since the new key code NKC has not been changed, note clock pulses φ□ are counted at the same rate as when writing. In this way, the address counter 37.

Up-counting is performed, and the address signal changes in the forward direction starting from the initial address and ending at the end address LPAD.

The data memory 21 is always in the read mode because the signals SMI and SM2 are both "0".

In this way, the waveform sample data that was just written is read from the beginning.

On the other hand, the envelope generator 47 generates a key-on pulse of 0K.
Envelope waveform data is generated according to ONP.

In this case, each data AT, D for envelope waveform setting
As mentioned above, T, SL, and RT are initially set to the contents that set the direct keying type envelope waveform in step 106 of the timer beep end event routine (Figure 11), so they are set at a constant level from key-on to key-off. Envelope waveform data is generated. As a result, the sampled waveform sample data is produced at the same volume level. In this way, the state of the sampled external sound signal can be immediately confirmed. When the read address reaches a value corresponding to the end address data LPAD, the comparator 38 generates an end pulse END, which is applied to the AND circuit 69. Since the other input of this AND circuit 69 is given the output "'1" of the flip-flop 67 set by the key-on pulse 0KONP, the output of the AND circuit 69 becomes "1" in response to the end pulse END. This is given to the envelope generator 47 via the OR circuit 70 as a key-off pulse OK○FP for parroting sound.The key-off pulse 0KOFF automatically created in this way eliminates the direct signal generated from the envelope generator 47. The keying type envelope waveform data falls to level O. In this way, the automatic sound generation with parrots is completed.Furthermore, the flip-flop 67 outputs a key-off pulse of
is reset by a signal delayed by a delay flip-flop 88.

The aforementioned eight performance modes M1 to M8 (see FIG. 3) are determined according to the movements of the switches RVR8, UTRN, and LO○P.

When the reverse switch RVR3 is turned on, the reverse on event routine shown in FIG. 15 is executed, and the reverse flag RVFLG is inverted from "0" to "1" or from "1" to "0" (step 121). Next step 1
Go to 24th.

When the U-turn switch UTRN is turned on, the U-turn event routine shown in FIG. 15 is executed and the U-turn flag UTFLG is inverted from "0" to "1" or from "II II II to II O" (step 122). . Next, go to step 124.

When the loop switch LOOP is turned on, the loop event routine shown in FIG. 15 is executed, and the loop flag LPF is
LG from “0” to t# I II or from “1” to “
0'' (step 123).

Next, go to step 124.

In step 124, each of the above flags RVFLG.

Based on the contents of UTFLG and LPFLG, performance modes M1 to M8 are determined according to the table below.

Table 1 Next, in step 125, mode signals M1 to M8 having contents corresponding to the determined performance mode are sent to the tone generator section.
Send to 0. That is, only one mode signal determined according to Table 1 above is "1", and the other mode signals are set to 5'0".

When reading out the waveform sample data stored in the key-on/off processing data memory 21 in the performance mode and generating a sound, a desired key on the keyboard 14 is pressed.

When a key is pressed, the key-on event routine shown in FIG. 12 is executed, and the key code of the pressed key is taken into the new key code register NKEY (step 110). In the next step 111, since the sampling flags SMPFLG and ○VWFLG are "0" in the performance mode, the determination is NO, and the process goes to step 126. Step 1
In step 26, a predetermined pronunciation assignment process is performed, which is a single note priority process since the single note priority pronunciation method is adopted in this embodiment.In the 0th order step 127, a new key press is performed according to the result of the single note priority process in the previous step. It is judged whether or not it is necessary to produce the musical tone related to the note, and if there is no need to produce it, the process goes to return, but if it is necessary, it goes to step 128. Priority may be adopted as appropriate. In step 128, register NK is used to allocate the new key code.
In the next step 129, which stores the second key code of EY in the register KCODE, the tone generator section stores the key code of the register KCODE (that is, the key code related to the newly pressed key to which the sound is newly assigned) as the new key code NKC. Send to 2o. Further step 13
At 0, the key-on pulse KONP is sent to the tone generator section 20.

When the pressed key is released, the key-off event routine shown in FIG. 13 is executed. The key code of the newly released key is taken into the new key code register NKEY (step 131), and the sampling flag SMPFL is set.
Check whether G, ○VWFLG is “1” (step 1
32) If the answer is NO, that is, the performance mode is set, the process proceeds to step 133, and it is checked whether the released key is the key currently being sounded (NKEY=KCODE). If so, a key-off pulse KOFP is sent to the tone generator section 20.

Next, the operation of the tone gelator section 20 in each performance mode M1 to M8 will be explained.

(Common explanation for each mode) In response to a key press, the key code of the pressed key is given as the new key code NKC as described above, and based on this, the note clock generation circuit 34 generates the note clock pulse φ of the pressed key. is generated. Furthermore, the flip-flop 4'3 is set by the key-on pulse KONP via the OR circuit 52, and the note clock pulse φ□ is input to the count input CLK of the address counter 37, and counting of address signals is started. Ru.

The contents of the direction indicating signal DIR generated from the T-flip-flop 41 differ depending on the states of the signals M1 to M8 corresponding to each performance mode, as will be described later. In response to this, the counting direction of the address counter 37 is determined, the address signal changes in response to the note clock pulse φ□, and waveform sample data is read out from the data memory 21.

Furthermore, the key-on pulse KONP and key-off pulse KOF generated in response to key presses and key releases as described above are also used.
P passes through OR circuit 66.70 to envelope generator 4
7, and envelope waveform data is generated accordingly. The volume envelope of the waveform sample data read from the data memory 21 is controlled in accordance with this envelope waveform data, and the sound is generated. Note that the envelope waveform setting data AT, DT, SL, and RT are set by the envelope operator group 17, and the waveform sample data is controlled by the envelope waveform of an appropriate shape set accordingly. The volume envelope is controlled.In addition, the end pulse E is output from the comparator 38.
The processing when an ND is generated differs depending on the state of the signals M1 to M8 corresponding to each performance mode, as will be described later.

(Mode M1: Normal performance) When mode signal M1 is “1”, OR circuit 54.55
key oscilloscope pulse KONP and signal M1 given via
“1” satisfies the condition of the AND circuit 56, and T-
Flip-flop 41 is set and direction indication signal DI
R becomes 111 I+.

In addition, the OR circuit 5 is activated in response to the key-on pulse K ON P.
3, a preset pulse PRP is generated.

As a result, the waveform sample data is read out only once in the forward direction from the data memory 21, starting from the initial address (all IIO'') and ending at the end address LPAD, as in the case of the above-mentioned parrot sound.

When the read address reaches the end address LPAD, the comparator 38 generates an end pulse END. This end pulse END is generated by AND circuits 60, 71, 72.
, 73. 1'' of the signal M1 is applied to the other input of the AND circuit 60 via the OR circuit 61, and in response to the end pulse END, the AND circuit 60.
．． “1” is applied to the reset input R of the flip-flop 43 via the delay flip-flop 63.

As a result, the read address becomes the end address LPAD.
When the address counter 37 reaches , the address counter 37 stops counting. The other AND circuits 71, 72, 73 receive the signal M1
It does not work when is 1'1''.

In this manner, in the performance mode M1, that is, the normal memory read mode, the data memory 21 is read out only once in the forward direction to generate sound.

(Mode M2: Reverse) When mode signal M2 is “1”, OR circuit 54.74
key-on pulse KONP and signal M2 given via
“1” satisfies the condition of the AND circuit 75, and T-
“1” is applied to the reset input R of the flip-flop 41. As a result, the T-flip-flop 41 is reset, and the direction instruction signal DIR becomes "OI+." Due to "O" of the direction instruction signal DIR, the selector 42 selects the end address data LPAD, and the selector 3 selects the end address data LPAD.
In step 9, initial address data (all "0") is selected. Also, OR circuit 5 responds to key-on pulse KONP.
3, a preset pulse PRP is generated. As a result, contrary to the above mode M1, the waveform sample data is read out from the data memory 21 only once in the reverse direction starting from the end address LPAD and ending at the initial address.

When the read address reaches the initial address, comparator 3
An end pulse END is generated from 8.

This end pulse END is generated by AND circuits 60, 71.7
Join 2,73. “1” of the signal M2 is applied to the other input of the AND circuit 60 via the OR circuit 61.
AND circuit 60 in response to the end pulse END. OR circuit 62. “1” is applied to the reset input R of the flip-flop 43 via the delay flip-flop 63. Due to this.

When the read address reaches the initial address, the address counter 37 stops counting. The other AND circuits 71, 72, and 73 do not operate when the signal M2 is "'1".

In this way, in the performance mode M2, that is, the "reverse" mode, the data memory 21 is read out only once in the reverse direction to generate sound.

(Mode M3: Loop) When mode signal M3 is “1”, OR circuit 54.55
key-on pulse KONP and signal M3 given via
is “1”, the condition of the AND circuit 56 is established, and T-
Flip-flop 41 is set and direction indication signal DI
R roars 1"1".

Further, a preset pulse PRP is generated from the OR circuit 53 in response to the key-on pulse KONP.

As a result, similarly to mode M1, waveform sample data is read out from the data memory 21 in the forward direction starting from the initial address and ending at the end address LPAD.

When the read address reaches the end address LPAD, the comparator 38 generates an end pulse END. This end pulse END is applied to the AND circuit 60, but
Since the mode signals M3 to M8 are not applied to the OR circuit 61, the end pulse END does not reset the flip-flop 43 and the address counter 37 does not stop counting.

On the other hand, due to "0" of the signals Ml and M2, the output of the OR circuit 68 becomes 41 Q u, the output of the inverter 76 which inverts this becomes "1", and the output of the AND circuit 72 becomes "1" in response to the end pulse END. becomes.

The output "1" of the AND circuit 72 is applied to the AND circuit 77. Since the output signal of the inverter 83, which is the other input of the AND circuit 77, is always "1" when the signals M4 and M7 are "0", the end signal is "1". AND circuit 77 according to pulse END
conditions are satisfied, and in response to the output signal "1" of the AND circuit 77, the delay flip-flop 78. ``A preset pulse PRP is generated via the OR circuit 53.

On the other hand, the end pulse END is also applied to the AND circuit 71, but since the output of the OR circuit 79 is 0'', the condition of the AND circuit 71 is not satisfied, and the state of the T-flip-flop 41 does not change.

The direction indication signal DIR remains at "1" and does not change, and in response to the preset pulse PRP generated as described above when the read address reaches the end address LPAD,
Again, the address counter 37 is preset with initial address data (all "0"), and the register 40 is loaded with end address data LPAD. Also,
Address counter 37 remains in up-count mode. In this way, the waveform sample data is read out from the data memory 21 again in the forward direction starting from the initial address and ending at the end address LPAD.

In this way, in the case of "loop", the waveform sample data in the data memory 21 is repeatedly read out in the forward direction, and a musical tone based on the sampled external sound is repeatedly produced many times. The sound generation can be ended by releasing the pressed key and attenuating the volume control envelope.

(Mode M4: U turn) When mode signal M4 is “1”, OR circuit 54.55
○NP and signal M4 to the key-on pulse given through
is “1”, the condition of the AND circuit 56 is established, and T-
Flip-flop 41 is set and direction indication signal DI
R becomes "1n".

Further, a preset pulse PRP is generated from the OR circuit 53 in response to the key-on pulse KONP.

As a result, similarly to mode M1, waveform sample data is read out from the data memory 21 in the forward direction starting from the initial address and ending at the end address LPAD.

When the read address reaches the end address LPAD, the comparator 38 generates an end pulse END. This end pulse END is applied to the AND circuit 60, but
Since mode signals M3 to M8 are not applied to the OR circuit 61, the output of the AND circuit 60 remains "0".Also, the end pulse END is applied to the AND circuit 73, but this output is also 1'0." In other words, if the direction indication signal DIR is "1" when the signal M4 is "1" (that is, the address is changing in the forward direction), the inverted signal of the signal M4 and the direction indication signal DIR is Input AND circuit 8
The output of the AND circuit 86 to which the signal M7 and the signal DIR are input is also "0", and the signal applied from the OR circuit 87 to the AND circuit 73 is "0", and the output of the AND circuit 73 is "0". The condition does not hold, therefore, the AND circuit 60
, 73, the output of the OR circuit 62 is 0'', and the flip-flop 43 is not reset by the end pulse END generated during the forward counting operation, and the address counter 37 does not stop counting.

On the other hand, due to "O" of the signals Ml and M2, the output of the OR circuit 68 becomes "0", and the output of the inverter 76 which inverts this becomes "0".
1”, and AND circuit 7 responds to the end pulse END.
The output of 2 becomes "1".

The output “1” of the AND circuit 72 is applied to the AND circuit 77. When signal M4 is “1”, direction indication signal DIR is #1j
l (that is, the address is changing in the forward direction), then
Inputting the signal M4 and an inverted signal of the direction instruction signal DIR,
The output of the AND circuit 80 is 640'', the signal M7 and the signal D
The output of the AND circuit 81 to which IR is input is also "O", and the OR circuit 8 to which the outputs of both AND circuits 80 and 81 are input is
The output of 2 is 110", and the inverter 83 inverts this.
The output of 111 J+ is 111 J+, and the output of the AND circuit 77 inputting this becomes "1". Therefore, AND circuit 77
A preset pulse PRP is generated via the delay flip-flop 78 and the OR circuit 53 in accordance with the output signal 1 (IIf) of the output signal 1 (IIf).

On the other hand, the end pulse END is also applied to the AND circuit 71, and the output of the OR circuit 79 becomes II due to the signal M4 being "1".
Since I II, the conditions of AND circuit 71 are satisfied,
re I II is added to the count C of the T-flip-flop 41 via the delay flip-flop 84, and the state of the T-flip-flop 41 is inverted from "1" to 0. Therefore, the direction indication signal DIR is It becomes '0''. As a result, the selector 42 selects the end address data LPAD, the selector 39 selects the initial address data (all 840 +7), and these are preset in the counter 37 by the preset pulse PRP generated as described above. It is also loaded into the register 40. In this way, contrary to the previous time, waveform sample data is read out from the data memory 21 in the reverse direction starting from the end address LPAD and ending at the initial address.

When the read address reaches the initial address, comparator 3
An end pulse END is generated from 8.

This time, the direction instruction signal DIR is 0'', its inverted signal is 1'', and the conditions of AND circuits 80 and 85 are satisfied. As a result, the output of the AND circuit 73 becomes "1" and the flip-flop 43 is reset. As a result, when the read address reaches the initial address (all 'O'), the address counter 37 stops counting.Furthermore, due to the output "1" of the AND circuit 80, the output of the AND circuit 77 becomes 140 IP, Preset pulse PRP is no longer generated.

In this manner, in the case of a "U turn", the waveform sample data in the data memory 21 is read out once in the forward direction, and then the waveform sample data in the data memory 21 is turned around in the reverse direction and read out once.

(Mode M5: Reverse loop) When mode signal M5 is "1", -OR circuit 54.7
The key-on pulse KONP and the signal M given through 4
5 is "1", the condition of the AND circuit 75 is established, and T
- Reset of the flip-flop 41 "1" is applied to the human power R. As a result, the T-flip-flop 41 is reset and the direction indication signal DIR is turned on. This "0" of the direction indication signal DIR causes the above-mentioned mode M
Similarly to 2, waveform sample data is read out from the data memory 21 in the reverse direction starting from the end address LPAD and ending at the initial address.

When the read address reaches the initial address, comparator 3
An end pulse END is generated from 8.

As in mode M3 (loop), the flip-flop 43 is not reset by the end pulse END, and the address counter 37 does not stop counting. Further, the condition of the AND circuit 77 is satisfied in response to the end pulse END, and the preset pulse PRP is generated. Furthermore, even if the end pulse END occurs, the condition of the AND circuit 71 is not satisfied and the state of the T-flip-flop 41 does not change. Therefore, the direction indication signal DIR remains "071" and does not change, and the read address is set to the initial value. In response to the preset pulse PRP generated as described above when the address is reached, the address counter 37 is again preset with end address data LPAD, and the register 40 is loaded with initial address data (all "0"). In addition, the address counter 37 remains in the down-count mode.In this way, the waveform sample data is read out again from the data memory 21 in the reverse direction starting from the end address LPAD and ending at the initial address.

In this way, in the case of "reverse loop", the waveform sample data in the data memory 21 is repeatedly read out in the reverse direction, and musical tones obtained by rearranging the sampled external sounds in the reverse direction in time are repeatedly produced. . This sound generation can be ended by releasing the pressed key and attenuating the volume control envelope.

(Mode M6: U-turn loop).

When the mode signal M6 is "1", the condition of the AND circuit 56 is established by the key-on pulse KONP applied via the OR circuit 54, 55 and the signal M6 is "1", the T-flip-flop 41 is set, and the direction Instruction signal DIR
becomes “1”.

Further, a preset pulse PRP is generated from the OR circuit 53 in response to the key-on pulse KONP.

As a result, similarly to mode M1, waveform sample data is read out from the data memory 21 in the forward direction starting from the initial address and ending at the end address LPAD.

When the read address reaches the end address LPAD, the comparator 38 generates an end pulse END. When the signal M6 is "1", the condition of the AND circuit 73 is not satisfied, the flip-flop 43 is not reset by the end pulse END, and the address counter 37 does not stop counting. Furthermore, the condition of the AND circuit 77 is satisfied by the end pulse END, and the preset pulse PRP
is generated. Further, since the output of the OR circuit 79 is "1" due to the signal M6 being "1", the condition of the AND circuit 71 is satisfied by the end pulse END, and the count power of the T-flip-flop 41 is passed through the delay flip-flop 84. 1g 111 is added to C, and the state of the T-flip-flop 41 is reversed from "1" to 11 OIP.

Therefore, the direction indication signal DIR becomes "0". As a result, the counting direction of the address counter 37 is reversed from the previous time, and the waveform sample data is read out from the data memory 21 in the reverse direction starting from the end address LPAD and ending at the initial address.

When the read address reaches the initial address.

An end pulse END is generated, as before.

The conditions of the AND circuits 71 and 77 are satisfied, the preset pulse PRP is generated, and the T-flip-flop 4
The state of 1 is inverted from "0" to "III" and the direction indication signal DIR becomes "1".As a result, the direction indication signal DIR becomes "1".

The counting direction of the address counter 37 returns to the forward direction.
Waveform sample data is read out from the data memory 21 in the forward direction starting from the initial address and ending at the end address LPAD.6Next, when the end pulse END is generated, the counting direction of the address counter 37 is reversed. .

Thereafter, similarly, every time the end pulse END is generated,
Repeat U-turn reading.

In this way, in the case of "U-turn loop", after reading the waveform sample data in the data memory 21 in the forward direction,
A U-turn reading operation in which the waveform sample data in the data memory 21 is read out by turning it in the opposite direction is repeated many times.

(Mode M7: U-turn/reverse) When mode signal M7 is "1", OR circuit 54.74
key-on pulse KONP and signal M7 given via
is “1”, the condition of the AND circuit 75 is established, and T-
The flip-flop 41 is reset and the direction indication signal D
IR becomes "0".

By "0" of this direction instruction signal DIR, the end address LP is
Waveform sample data is read from the data memory 21 in the reverse direction starting from AD and ending at the initial address.

When the read address reaches the initial address.

An end pulse END is generated from the comparator 38.

This end pulse END is applied to the AND circuit 73, but its output is 0'', that is, when the signal M7 is 1'', the direction instruction signal DIR is ``O'' (that is, the address is changing in the opposite direction). Then, the output of the AND circuit 86 inputting the signal M7 and the direction instruction signal DIR is "0", the output of the AND circuit 85 is also "0", and the signal applied from the OR circuit 87 to the AND circuit 73 is "0". Yes, AND circuit 7
Condition 3 does not hold. Therefore, in mode M7,
End pulse EN generated during reverse direction counting operation
Depending on D, the flip-flop 43 is not reset;
The address counter 37 does not stop counting.

In addition, the signal M7 is 1'1'' and the direction indication signal DIR is 0.
”, the outputs of the AND circuit 81 and the OR circuit 82 become “0”.
”, and the AND circuit 77 responds to the end pulse END.
The output becomes 1'', and a preset pulse PRP is generated via the delay flip-flop 78 and the OR circuit 53.

On the other hand, the end pulse END is also applied to the AND circuit 71, and the output of the OR circuit 79 becomes 111 due to the signal M7 being "1".
11, the condition of the AND circuit 71 is satisfied, and the T-flip-flop 4 is passed through the delay flip-flop 84.
1'1'' is added to the count input C of 1, and the state of the T-flip-flop 41 is inverted from '0'' to #IIt. Therefore, the direction instruction signal DIR becomes "1". As a result, the selector 42 selects the initial address data (all "O"), the selector 39 selects the end address data LPAD, and the preset pulse PRP generated as described above causes these to be transferred to the counter 3.
7 and also loaded into register 40. In this way, contrary to the previous time, the data memory 2 starts from the initial address and ends from the end address LPAD.
Waveform sample data is read out in the forward direction from 1.

When the read address reaches the end address LPAD, the comparator 38 generates an end pulse END. This time, the direction indication signal DIR is II II II, and the conditions of AND circuits 81 and 86 are satisfied.

As a result, the output of the AND circuit 73 becomes "1", and the flip-flop 43 is reset. As a result, when the read address reaches the end address LPAD, the address counter 37 stops counting. Also,
Due to the output "1" of the AND circuit 81, the output of the AND circuit 77 becomes "10", and the preset pulse PRP is no longer generated.

In this way, in the case of "U-turn reverse", the waveform sample data in the data memory 21 is read out once in the reverse direction, and then the waveform sample data in the data memory 21 is turned around in the forward direction and read out once.

As a result, a new performance effect is realized in which a musical tone in which the sampled external sounds are rearranged temporally backward is produced once, and then the sampled tone is rearranged temporally in the forward direction and produced once again. be able to.

(Mode M8: U-turn reverse loop) When the mode signal M8 is "1", the key-on pulse KONP given via the OR circuit 54.74 and the signal M8 are "1".
As a result, the condition of the AND circuit 75 is satisfied, the T-flip-flop 41 is reset, and the direction instruction signal DIR becomes P0''.

Due to the output of this direction instruction signal DIR, the waveform sample data is transferred from the data memory 21 in the reverse direction starting from the end address LPAD and ending at the initial address, as in the case of mode M7 (U-turn/reverse) described above. Read out.

When the read address reaches the initial address, comparator 3
An end pulse END is generated from 8.

When the signal M8 is 1'', the condition of the AND circuit 73 is not satisfied, the flip-flop 43 is not reset by the end pulse END, and the count of the address counter 37 is not stopped. conditions are met, preset pulse PRP
is generated.

Furthermore, the output of the OR circuit 79 is set to “1” by the signal M8.
1'', the condition of the AND circuit 71 is satisfied by the end pulse E N D, and the delay flip-flop 84
"1" is added to the count input C of the T-flip-flop 41 via the T-flip-flop 41, and the state of the T-flip-flop 41 is inverted from "0" to "1". Therefore, direction signal D
IR becomes “1”, which causes address counter 3
The counting direction of 7 is reversed from the previous time, and the initial address (
Waveform sample data is read out from the data memory 21 in the forward direction starting from all "0") and ending at the end address LPAD.

When the read address reaches the end address LPAD, the end pulse END is generated, and the conditions of the AND circuits 71 and 77 are satisfied as described above, and the preset pulse P is generated.
At the same time that RP is generated, the state of the T-flip-flop 41 is inverted from "1" to "O" and the direction indicating signal DIR is generated.
becomes “0”.

As a result, the counting direction of the address counter 37 returns to the opposite direction, and the waveform sample data is read out from the data memory 21 in the reverse direction starting from the end address LPAD and ending at the initial address. Next, when the end pulse END is generated.

The counting direction of the address counter 37 is set to the forward direction.

Thereafter, similarly, every time the end pulse END is generated,
Repeat "return/reverse" reading.

Thus, in the case of return reverse loop J,
After reading out the waveform sample data in the data memory 21 in the reverse direction, "return/reverse" reading is repeated many times, in which the waveform sample data in the data memory 21 is turned around and read out in the forward direction.

As a result, a musical tone in which the sampled external sounds are rearranged temporally backward is produced once, and then the sampled tone is rearranged temporally in the forward direction and produced once again.
You can achieve new performance effects by repeating ``Return/Reverse'' many times. This sound generation can be ended by releasing the pressed key and attenuating the volume control envelope.

End address ゛　・　　　゛ By the process of step 115 in FIG. 14 described above.

End address buffer L in the microcomputer section
As the end address data stored in the PADB, the address storing the data of the final zero-crossing portion of the sampled original waveform, that is, the final zero-crossing address (for example, an address in block units) is initially set. End address data L used by the tone generator section 20 in each of the aforementioned performance modes M1 to M8.
PAD is the data stored in this end address buffer LPADH, and if the initial settings remain as described above, the end address data LPAD
is the final zero-crossing address itself in the sampled original waveform (that is, the zero-crossing address buffer ZC
data stored in RADB).

In this way, when the final zero cross address data itself in the sampled original waveform is used as the end address data LPAD, musical tones corresponding to all the original waveforms sampled from the outside are produced in the performance mode. However, if the end address data LPAD used by the tone generator section 20 in each of the above-mentioned performance modes M1 to M8 is not limited to the final zero cross address data itself in the sampled original waveform, but can be changed as appropriate, the performance effect can be improved. can be further increased.

To that end, changing this end address data 9 LPAD requires an increment switch INC and a decrement switch D
This can be done by operating the EC. In addition, in this embodiment, when in a mode in which sampled waveform data is repeatedly read out and sounded, that is, in "loop", "reverse loop", "return loop", or "return reverse loop", the Such changes are possible. This is because during such repeated performances, it is quite effective to control the length of one repetition cycle by adjusting the end address. However, the present invention is not limited to this, and the end address data LPAD may be increased or decreased in other performance modes as well.

When the increment switch INC is turned on, the increment event routine shown in FIG. 17 is executed. Here, step 13
5, it is checked whether the loop flag LPFLG is "1", and if YES, the process goes to step 136, but if NO, the process goes to return. MS, M6. This is to perform this control at M8. In step 136, the contents of the end address buffer LPADB are incremented by one. Note that if the contents of the buffer LPADB reach the maximum value in this increment operation, the maximum value is held.

Since the data stored in the above-mentioned passing buffer LPADB is in block units, this increase is also performed in block units. In this case, in the zero-th order step 137 where the maximum value is "15", the contents of the end address buffer LPADB are sent to the tone generator unit 20 as end address data LPAD.

When the decrease switch DEC is turned on, the decrease event routine shown in FIG. 18 is executed. Step 135a here
, 136a, and 137a are each step 1 in FIG.
The process is almost the same as that of steps 35, 136, and 137, and the difference is that in step 136, the end address buffer LP
While the contents of ADB were increased by 1, step 136
The only point in a is that the contents of this buffer LPADB are decreased by 1.

Thus, the end address buffer L I) A D
By increasing or decreasing the contents of B, the value of the end address data LPAD used by the tone generator section 20 can be increased or decreased.

By increasing/decreasing the value of the end address data LPAD in this way, it is possible to change and adjust the end point address in forward reading and the starting point address in backward reading, and the starting point of repetition in loop performance. You can change the address freely. Therefore, the mode of repeated reading can be freely changed by adjusting the increase/decrease change of the end address data LPAD.

For example, if noise is included in the waveform sample data stored at an address before the final address of the waveform sample data, the end address data LPA
By decreasing the value of D and adjusting the address closer to the front, it is possible to prevent addresses containing noise from falling within the range of addresses to be read from the data memory 21 during performance. You can cut the pronunciation of the sample data part.

Alternatively, by increasing the value of the end address data LPAD and adjusting it to an address beyond the final address of the waveform sample data, the data memory
The range of addresses to be read from 1 can be expanded to addresses where waveform sample data is not actually stored, and by repeatedly reading in this expanded address range, you can consciously read out data at the joints of repeated reading. It is also possible to create a special performance effect in which the sound is repeated intermittently by creating a silent section of an appropriate length.

Note that the end address buffer LPADB is changed by the increase switch INC and decrease switch DEC.
is the contents of the zero-crossing address buffer ZCRAD
The original final zero-crossing address in the original waveform stored in B is not changed.

This is used to return the contents of the end address buffer LPADB to the original final zero-crossing address in the original waveform during all cancel processing to be described later.

Echo Switch When the echo switch ECHO is turned on, the echo event routine shown in FIG. 16 is executed. In step 138, the echo flag ECFLG is inverted from 0" to "1" or from "1" to 11011. In step 139, it is checked whether the echo flag ECFLG is 11".
1'I II, go to step 140 and save the contents of the loop flag LPFLG to the loop flag buffer LPF.
After saving it to LGB, set the loop flag LPFLG to tt
Set to I II. In this way, the performance mode is automatically set to a mode related to "loop", ie, "loop", "reverse loop", "U-turn loop", or "U-turn reverse loop".

In the next steps 124a and 125a, the same processing as steps 124 and 125 in FIG. 15 is performed, and the performance mode is set to M.
Decide on one from 1 to M8. However, in this case, since the loop flag LPFLG is set to 1'', the "loop" related performance mode M3. M5. M6. It is always determined to be one of M8.

Next, in step 141, the release time buffer RT
The contents of B are stored in the release time storage buffer RTBUF, and in step 142, the contents of the release time buffer RTBUF are stored in the release time storage buffer RTBUF.
Set the contents of B to the maximum value MAX. Then, in step 143, the contents of the release time buffer RTB are sent to the tone generator section 20 as release time data R.
Send as T.

As a result, the release time of the envelope waveform data generated by the envelope generator 47 is set to be the longest, and the generated musical tone attenuates extremely slowly after the key is released. Moreover, the performance mode is “loop” related mode M
3. M5. M6. M8, the waveform sample data stored in the data memory 21 is read out repeatedly in the forward direction, reverse direction, or alternately switching between forward and reverse directions, and the volume of the corresponding musical tone gradually decreases. Repeatedly sounded at the level. Note that since the waveform sample data that is repeatedly read is a sample of external sound, it generally has its own amplitude envelope extending from the rise to the fall of the sound. Therefore, it is possible to realize an echo-like effect in which a sound with an amplitude envelope ranging from the rise to the fall of the sound is repeatedly produced many times, and the volume gradually attenuates. Moreover, the difference from a simple conventional echo is the "loop" related performance mode M3. M5. As a result of the sound generation control by M6 and M8, sounds may be pronounced in the opposite direction to their original chronological order, may be pronounced according to their original chronological order, or may be pronounced alternately in a combination thereof. Furthermore, by combining this with the above-mentioned end address increase/decrease adjustment control, it is possible to realize a free echo effect that was completely absent in the past.

When the echo flag ECFLG becomes xt'Oto, the loop flag buffer LPF is
By returning the contents of LGB to the loop flag LPFLG, the contents of the loop flag LPFLG are returned to the state before applying the echo effect. Next steps 124b, 125
At step b, the same processing as steps 124 and 125 in FIG. 15 is performed, and the performance mode is determined to be one of M1 to M8.

In the next step 145, the contents of the release time storage buffer RTBUF are returned to the release time buffer RTB, thereby returning the contents of the release time buffer RTB to the state before the echo effect was applied.

All cancel processing All or predetermined data set/selected/changed/adjusted in the operation panel section 15 in relation to the sampled waveform sample data are canceled, and the contents of these data are sampled first. If you want to return to the previous state, operate the all cancel switch CANSEL. Then, the all cancel event routine shown in FIG. 19 is executed.

First, in step 146, each flag S M P F
LG, 0VWFLG, LPFLG, UTFLG, RVF
Reset LG and ECFLG to “O”. This corresponds to each switch SMP L, O in the operation panel section 15.
V RW R, L OOP, U T RN, R
This is to cancel the sampling mode and performance modes M2 to M8 set according to the operations of VR8 and ECHO, and to initialize the performance mode M1.

In the next step 147, the original final zero cross address data in the original waveform stored in the zero cross address buffer ZCRADB is transferred to the end address buffer L.
Store in PADH. This is because the contents of the end address buffer LPADB may be changed depending on the operation of the increase switch INC and the decrease switch DEC as described above, so such changes are canceled and ``llll
This is to return the contents of the second address buffer LPADB to the original final zero-crossing address in the original waveform.

In step 148, the attack time buffer ATB,
The contents of the decay time buffer DTB, sustain level buffer SLB, and release time buffer RTB are initialized to the contents for setting the above-mentioned direct keying type envelope waveform.

This corresponds to each buffer ATB, DTB, SLB, RTB changed according to the operation of the envelope control operator group 17.
This is to cancel the contents of , and initialize the contents of the direct keying type envelope waveform.

In step 149, data to be given to the tone generator section 20 is initialized as follows and sent to the tone generator section 20. Sampling mode signal SMI
and set 3M2 to “OI+”.

Set the performance mode signal M1 to 1" and set the remaining performance mode signals M2 to M8 to "0". End address data LP
Set AD to the last zero-crossing address data stored in the end address buffer LPADB. Attack time data AT, decay time data DT, sustain level data SL, and release time data RT are provided in two buffers ATB, DTB, SLB, and RT, respectively.
Set the contents of B. In the next step 150, data for various musical sound effects are also initialized to predetermined contents.

In this way, when the all cancel switch CANSEL is operated, all or predetermined data set, selected, changed, or adjusted on the operation panel section 15 in relation to the waveform sample data are canceled. The data contents are returned to the state they were in when they were first sampled. In other words.

The edited contents of various data edited in relation to the sampled waveform sample data are canceled and returned to the initial state before one editing. By being able to cancel the edited content and return to the initial state before editing, it becomes possible to perform free editing without fear of failure, and it is possible to edit data related to the sampled waveform sample data. Editing functionality can be improved.

Furthermore, in the above embodiment, it is assumed that the waveform sample data stored in the data memory is expressed using the PCM (Pulse Code Modulation) method; however, the present invention is not limited to this.
The data may be expressed using an appropriate data compression method, such as adaptive differential PCM, delta modulation (DM), or adaptive delta modulation (ADM). Alternatively, the sampled waveform sample data may be written into the data memory after being subjected to appropriate data correction processing (for example, normalization processing so that the amplitude level is approximately constant over the entire interval). In this case, the data correction process (level standardization process, etc.) may be performed on an analog sound signal picked up by a microphone.

The processes shown in FIGS. 8 to 19 executed by one software process in the microcomputer section may be executed by a dedicated hardware circuit.

On the other hand, although the data memory read/write control circuit in the tone generator section is constituted by a dedicated hardware circuit in FIG. 6, it can also be executed by software processing in the microcomputer section. Further, in FIG. 6, some common circuits (such as an address counter) are used for read/write control, but write control and read control may be performed by separate circuits.

In the above embodiment, a single tone pronunciation method is used, but it goes without saying that a multiple tone pronunciation method may also be used. In that case, a well-known technique for processing sound generation assignment for multiple channels may be used.

Further, in the above embodiment, the musical tone generating device of the present invention is applied to an electronic musical instrument equipped with a keyboard, but the present invention is not limited to this, but it is applicable to other electric or electronic musical instruments, a modular keyboard, or an appropriate input device. The musical sound generating device of the present invention may be applied to a sound source device module that is used by selectively connecting to equipment, a sound system, an effect device, a general-purpose computer, etc. as appropriate.

Although not specifically shown in the above embodiment, the operation panel section also displays the currently selected performance mode, the contents of the currently set end address data LPAD, the contents of various envelope setting data, and other various settings. It is preferable to provide a display device such as an LED that displays the contents of the data.

In addition, in the above embodiment, three switches RVRS, UT
8 performance modes M1~ depending on the RN and LOOP repetitions
M8 is determined, but each mode M1 to M8
A separate switch may be provided for individually selecting the .

Although the tone generator section in Figure 6 uses only externally sampled sounds as its sound source, it is not limited to this, and may have other appropriate sound sources, and can select desired tones from among a plurality of ready-made tones and externally sampled tones. It is also possible to have a configuration in which the tone color can be selected as appropriate.

In the above embodiment, immediately after sampling an external sound, a key-on pulse 0KONP is generated by software processing (step 118 in FIG. 14) as a trigger for automatically generating the sampled sound. may be generated by a dedicated hardware circuit in the tone generator section. For that purpose, for example, the sampling end signal SMPE
When ND is output, that is, when the end pulse END is output, the address counter 37 does not stop counting, but continues to count up from the initial address by letting the overflow occur, and the sampling end signal SM
It is preferable to input PEND to the envelope generator 47 as the key-on pulse 0KONP for parrot return, set the sampling mode signals SMI and SM2 to "0", and set the mode signal M1 to "1".

Furthermore, in the above embodiment, the reading rate of the data memory is the same as the writing rate in the parrot sound generation immediately after sampling the external sound.

This may be different.

The method of detecting a zero cross is not limited to the one shown in the above embodiment, and any method may be used. For example, instead of adopting a zero judgment range with a certain width as in the above embodiment, it is possible to detect that the level of the waveform sample data actually changes from positive to negative, and then from negative to positive. good. Alternatively, zero crossings may be detected in an analog sound signal picked up by a microphone.

Further, in the above embodiment, the addresses corresponding to the detected zero crosses are stored as data in block units, but this may be stored as data in address units.

Similarly, the end address data (LPAD) corresponding to the final zero-crossing address is not limited to data in units of blocks, but may be stored in data in units of addresses. In this case, it is preferable that the amount of increase and decrease when increasing or decreasing the end address data can also be finely adjusted for each address. Further, the reference address to be subjected to increase/decrease adjustment is not limited to the end address as in the above embodiment, but may be an initial address or both.

In addition, if the actual final zero-crossing address is stored for each block and the end address data is increased or decreased in block units, the actual final zero-crossing address in the block defined as the end address is stored as the end address (12-bit (end address in address units).

Furthermore, in the above embodiment, the increase/decrease adjustment of the end address data is possible when the loop flag is set, that is, when the musical tone corresponding to the sampled external sound is repeatedly sounded, but this is not limited to this, and in other cases. Alternatively, the end address data (reference address data) may be increased, decreased, or adjusted.

Furthermore, in the above embodiment, in the all-cancel process, all data set and controlled by the operation panel are canceled and returned to a predetermined initial state, but this is based on data closely related to the sampled external sound. It is also possible to cancel only this and return to a predetermined initial state.

For example, it is not necessary to cancel data for various musical tone effects.

〔Effect of the invention〕

As described above, according to the present invention, the actual final address of the external sound waveform sample data written in the storage means is simultaneously detected in parallel with the writing operation.
It is now possible to perform performances based on various readout formats in which the waveform sample data in the storage means is read out in the forward or reverse direction with this final address as the end or starting point immediately after writing, and this allows sampling-based musical tone generation. The performance performance of the device can be improved.
It has this excellent effect.

[Brief explanation of the drawing]

FIG. 1 is a functional block diagram showing an overview of the musical tone generating device according to the present invention, and FIG. 2 is a functional block diagram showing the outline of the musical tone generating device according to the present invention.
A hardware configuration diagram showing an example of a child instrument of an LA child instrument. 3 is a diagram schematically showing the data memory readout format in various performance modes realized in the embodiment of FIG. 2, and FIG. 4 is a diagram showing the address structure of the data memory included in the tone generator section of FIG. 2. A diagram showing an example. FIG. 5 is a diagram showing an example of a memory map of data and working memory in the microcomputer section of FIG. 2. FIG. 6 is a block diagram showing a detailed example of the tone generator section of the second garden, and FIG. 7 is a timing chart showing an example of generation of note clock pulses in FIG. 8 to 19 are flowcharts showing examples of programs executed in the microcomputer section of FIG. 2, in which FIG. 8 is a main routine, FIG. 9 is a sampling event routine, and FIG. 10 is an override event. Routine, FIG. 11 is a timer beep end event routine. FIG. 12 shows the key-on event routine, FIG. 13 shows the key-off event routine, FIG. 14 shows the sampling end event routine, FIG. 15 shows the reverse event routine, U-turn event routine, and loop event routine, and FIG. 16 shows the echo event routine. FIG. 17 shows an increase event routine, FIG. 18 shows a decrease event routine, and FIG. 19 shows an all cancel event routine. 1...External sound sampling means, 2...Storage means,
3...Write control means, 4...Read control means, 1
4...Keyboard, 15...Operation panel section, 16...Sampling control operator group, 17...Envelope control operator group, 18...Effect control operator group, 20...Tone generator Part, 21... Data memory, 22.
...Microphone, 24...Timer beep circuit, 2
7... Analog/digital converter, 28... Adder for overwriting, 32... Zero cross detection circuit, -3
3... Zero cross address latch circuit, 34... Note clock generation circuit, 37... Address counter,
38... Comparator, 40... End point address register,
47...Envelope generator. Patent applicant: Nippon Musical Instruments Manufacturing Co., Ltd. Agent: Patent attorney: Iizuka Engraving of drawing with lid (No changes in 'a' Figure 1 Q missing D Figure 16 Figure 18 Procedural amendment form) % formula % 1, Indication of the case 1986 Patent Application No. 1210 2, Name of the invention Musical tone generator 3, Person making the amendment Relationship to the case Patent applicant (name) (407) Nippon Gakki Mfg. Co., Ltd. 4, Agent as per attached sheet (No change in content)

Claims (3)

[Claims] (1) External sound sampling means for sampling a sound signal input from the outside; readable/writable storage means for storing waveform sample data; and said storage for storing the waveform sample data of the sound signal sampled by said external sound sampling means. writing control means for writing into the storage means; zero-cross detection means for detecting zero-crossings of the sound signal or the waveform sample data; and storing a write address of the waveform sample data in the storage means each time a zero-crossing is detected by the zero-crossing detection means. final address detection means for detecting the last address stored when writing is completed as the final address of the waveform sample data; A musical tone generating device, comprising readout control means for reading waveform sample data of the means in a forward or reverse direction, and generating a musical tone signal corresponding to the waveform sample data read from the storage means. (2) The final address detection means stores a block corresponding to an address where a zero crossing is detected in block units consisting of a plurality of addresses, and when writing is completed, the last address in the last block stored is 2. The musical tone generating device according to claim 1, wherein the address is detected as the final address of the waveform sample data. (3) The musical tone generating device according to claim 1, wherein the zero cross detection means detects whether the level of the sound signal or waveform sample data falls within a predetermined zero determination range.