JPS63287826A - Production of active matrix display device - Google Patents
Production of active matrix display deviceInfo
- Publication number
- JPS63287826A JPS63287826A JP62124519A JP12451987A JPS63287826A JP S63287826 A JPS63287826 A JP S63287826A JP 62124519 A JP62124519 A JP 62124519A JP 12451987 A JP12451987 A JP 12451987A JP S63287826 A JPS63287826 A JP S63287826A
- Authority
- JP
- Japan
- Prior art keywords
- array substrate
- electrode lines
- active matrix
- electrode wires
- display device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000011159 matrix material Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims description 18
- 238000007689 inspection Methods 0.000 claims description 14
- 239000004973 liquid crystal related substance Substances 0.000 claims description 13
- 230000005611 electricity Effects 0.000 abstract description 17
- 230000003068 static effect Effects 0.000 abstract description 17
- 230000015572 biosynthetic process Effects 0.000 abstract description 5
- 230000002950 deficient Effects 0.000 abstract description 4
- 238000003491 array Methods 0.000 abstract 2
- 230000015556 catabolic process Effects 0.000 abstract 2
- 230000006378 damage Effects 0.000 description 6
- 230000000694 effects Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- FFBHFFJDDLITSX-UHFFFAOYSA-N benzyl N-[2-hydroxy-4-(3-oxomorpholin-4-yl)phenyl]carbamate Chemical compound OC1=C(NC(=O)OCC2=CC=CC=C2)C=CC(=C1)N1CCOCC1=O FFBHFFJDDLITSX-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000009429 electrical wiring Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000004026 adhesive bonding Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136204—Arrangements to prevent high voltage or static electricity failures
Landscapes
- Physics & Mathematics (AREA)
- Liquid Crystal (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、大容量で高画質な表示が得られる、アクティ
ブマトリクス型の表示装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing an active matrix display device that can provide a large capacity and high quality display.
従来の技術
第3図は、アクティブマトリクスアレー基板上の電気的
配線模式図の一例を示し、9行8列のマトリクスの場合
を示す。第3図において、aユルミ、は行電極線であり
、b1〜b1は列電極線である。また、それぞれの交点
にQxxで代表的に示される薄膜トランジスタなどのス
イッチング素子ならびにdllで代表的に示される絵素
電極が設置される。このよう7な電気配線を施されたア
クティブマトリクスアレー基板と、主面上の少なくとも
一部に透明電極が形成された別の対向基板とを平行対峙
させ、その間に液晶を封入することにより液晶表示装置
が製造される。BACKGROUND OF THE INVENTION FIG. 3 shows an example of a schematic electrical wiring diagram on an active matrix array substrate, and shows a matrix of 9 rows and 8 columns. In FIG. 3, ``a'' is a row electrode line, and ``b1'' and ``b1'' are column electrode lines. Further, at each intersection, a switching element such as a thin film transistor, typically indicated by Qxx, and a picture element electrode, typically indicated by dll, are installed. A liquid crystal display is produced by arranging an active matrix array substrate with such 7 electrical wirings and another counter substrate on which transparent electrodes are formed on at least a portion of the main surface to face each other in parallel, and sealing a liquid crystal between them. A device is manufactured.
第4図は液晶表示装置の一般的な製造工程のフロー図を
示す。第4図において、アレー基板製造工程1が完了後
、断線やショートなどの不良に関する断線・ショート検
査工程2が入り、次に対向基板とアレー基板をはり合せ
て液晶を挟持させるパネル組立工程3を行なう。パネル
組立工程3完了後、画像の検査工程4が入り、不良のも
のは救済工程5後、出荷検査工程6を行なって出荷され
る。FIG. 4 shows a flowchart of a general manufacturing process for a liquid crystal display device. In FIG. 4, after the array substrate manufacturing process 1 is completed, the disconnection/short circuit inspection process 2 for defects such as disconnections and short circuits begins, and then the panel assembly process 3 involves gluing the opposing substrate and the array substrate together to sandwich the liquid crystal. Let's do it. After the panel assembly process 3 is completed, an image inspection process 4 begins, and defective products undergo a repair process 5, a shipping inspection process 6, and are shipped.
発明が解決しようとする問題点
しかるに、上述したごとき液晶表示装置の製造工程にお
いては、アレー基板製造工程1、パネル組立工程3およ
び不良パネル救済工程5などにおいて静電気が発生する
ことが多く、アレー基板のハンドリングや移載に際して
特定の行電極線または列電極線に静電気の充放電が生じ
る。静電気の充放電の生じた特定の行電極線または列電
極線に接続された薄膜トランジスタなどのスイッチング
素子は、静電気の充放電が生じなかった他の行電極線ま
たは列電極線との間の静電気による大きな電位差に晒さ
れ、本来の性能が劣化してしまうことが多かった、特に
、アクティブマトリクスアレー基板と対向基板とに液晶
配向処理をした後に、貼合せて液晶を注入し、偏向板を
貼付するというパネル組立工程3において、アレー基板
が静電気で破壊されることが多かった。Problems to be Solved by the Invention However, in the manufacturing process of the liquid crystal display device as described above, static electricity is often generated in the array substrate manufacturing process 1, the panel assembly process 3, the defective panel relief process 5, etc. When handling or transferring, static electricity is charged and discharged to specific row or column electrode lines. A switching element such as a thin film transistor connected to a specific row electrode line or column electrode line that has been charged or discharged with static electricity may be connected to other row or column electrode lines that have not been charged or discharged with static electricity. The original performance often deteriorates due to exposure to a large potential difference. In particular, after the active matrix array substrate and the counter substrate have been subjected to liquid crystal alignment treatment, they are laminated together, liquid crystal is injected, and a polarizing plate is attached. In panel assembly process 3, the array substrate was often destroyed by static electricity.
そこで第5図に示すように、行電極線a0〜a。Therefore, as shown in FIG. 5, the row electrode lines a0 to a.
と列電極線b□〜b、を導電部材A□、A2.B□。and column electrode lines b□ to b, and conductive members A□, A2. B□.
B2.C,D、E、Fによりすべて電気的に短絡させる
ことにより、行と列の間に静電的電圧が印加されないよ
うにして、アレー基板の静電気による破壊を防いでいた
。B2. By electrically shorting C, D, E, and F, no electrostatic voltage is applied between the rows and columns, and damage to the array substrate due to static electricity is prevented.
しかし、このような静電対策パターンでは、行と列に別
々の信号を載せることができないので、このままではト
ランジスタの特性検査や断線・ショート検査および画像
検査などの検査が不可能であり、第4図に示すように静
電対策パターンは製造工程、組立工程、救済工程におい
て必要に応じて最高3回の形成−除去を繰り返えす必要
があった。However, with such an electrostatic countermeasure pattern, it is not possible to carry separate signals for rows and columns, so it is impossible to carry out tests such as transistor characteristics inspection, disconnection/short circuit inspection, and image inspection. As shown in the figure, the electrostatic countermeasure pattern had to be formed and removed up to three times as necessary during the manufacturing process, assembly process, and relief process.
本発明は上記問題点を解決するもので、静電対策パター
ンの形成−除去の回数を減らすことのできるアクティブ
マトリクス表示装置の製造方法を提供することを目的と
するものである。SUMMARY OF THE INVENTION The present invention solves the above-mentioned problems, and aims to provide a method for manufacturing an active matrix display device that can reduce the number of times an electrostatic countermeasure pattern is formed and removed.
問題点を解決するための手段
上記問題点を解決するために本発明は、複数本の行電極
線、この行電極線と交差する複数本の列電極線、および
前記行電極線と列電極線との交点にスイッチング素子お
よび絵素電極を有するアクティブマトリクスアレー基板
と、少なくとも一部に透明電極を有する対向基板と、そ
れらの基板間に挟持された液晶とからなるアクティブマ
トリクス表示装置の製造方法であって、前記アクティブ
マトリクスアレー基板の製作中または製作が終了した後
に、前記行電極線と列電極線の少なくとも一方の一端ま
たは両端を行は行どうし、列は列どうしを互いに電気的
に並列に短絡させ、その後に前記対向基板と貼り合せて
液晶を挟持させ、所定検査後に前記電気的短絡を切り離
すものである。Means for Solving the Problems In order to solve the above problems, the present invention provides a plurality of row electrode lines, a plurality of column electrode lines that intersect with the row electrode lines, and the row electrode lines and column electrode lines. A method for manufacturing an active matrix display device comprising an active matrix array substrate having a switching element and a pixel electrode at the intersection with a counter substrate having a transparent electrode on at least a portion thereof, and a liquid crystal sandwiched between these substrates. During or after the manufacture of the active matrix array substrate, one or both ends of at least one of the row electrode lines and the column electrode lines are electrically parallel to each other. A short circuit is made, and then the liquid crystal is sandwiched by bonding with the counter substrate, and the electrical short circuit is cut off after a predetermined inspection.
作用
上記構成により、アレー基板の各電極線の形成と同時に
またはアレー基板完成後に行電極線および列電極線のそ
れぞれが電気的に並列に短絡されているため、パネル組
立や画像検査その他のハンドリング時に静電気による破
壊を防ぐことが可能であり、かつ、その状態でもアレー
基板および表示パネルの特性の測定が可能であるので、
静電対策パターンの形成−除去の回数を従来のものより
低減でき、コストの低減が可能となる。Effect With the above configuration, the row electrode lines and the column electrode lines are electrically short-circuited in parallel at the same time as each electrode line of the array substrate is formed or after the array substrate is completed, so that it is easy to use during panel assembly, image inspection, and other handling. It is possible to prevent damage caused by static electricity, and it is also possible to measure the characteristics of the array substrate and display panel even in this state.
The number of times the electrostatic countermeasure pattern is formed and removed can be reduced compared to the conventional method, and costs can be reduced.
実施例 以下本発明の一実施例を図面に基づいて説明する。Example An embodiment of the present invention will be described below based on the drawings.
第1図は本発明製造の一実施例におけるアクティブマト
リ・クス表示装置のマトリクスアレー基板の概略平面図
である。第1図において、アクティブマトリクスアレー
基板製造中または製造を完了した後に、複数の行電極線
a工〜a9と、複数の列電極線b□〜b8の両方をそれ
ぞれ行は行どうし、列は列どうしを導電部材A1. A
2およびB1.B。FIG. 1 is a schematic plan view of a matrix array substrate of an active matrix display device according to an embodiment of the present invention. In FIG. 1, during or after manufacturing the active matrix array substrate, a plurality of row electrode lines a to a9 and a plurality of column electrode lines b to b8 are connected to each other. The conductive members A1. A
2 and B1. B.
を用いて電気的に並列に短絡し、その後に第2図のフロ
ー図に示すようにパネルの組立工程3を行ない、不良パ
ネル救済工程5のあとで最終的に導電部材A、、A2お
よびB1.B2を除去することにより、a□〜a、およ
びb□〜b7の複数本の行および列電極線を切り離す。After that, as shown in the flowchart of FIG. 2, the panel assembly process 3 is performed, and after the defective panel relief process 5, the conductive members A, , A2 and B1 are finally connected in parallel. .. By removing B2, a plurality of row and column electrode lines a□ to a and b□ to b7 are separated.
このように行電極線a□〜a9および列電極線b1〜b
sをそれぞれ並列に短絡することによって、行電極線、
列電極線の各々の電極線の固有の容量をCa、Cbとし
行電極線の数をmおよび列電極線の数をnとした場合、
行電極線群の容量mcaおよび列電極線群の容量nCb
と大きな容量にすることができ、静電気の影響を低減し
て静電気でアレー基板が破壊されることを低減するもの
である。In this way, the row electrode lines a□ to a9 and the column electrode lines b1 to b
By short-circuiting s in parallel, the row electrode lines,
When the specific capacitance of each column electrode line is Ca, Cb, the number of row electrode lines is m, and the number of column electrode lines is n,
Capacitance mca of row electrode line group and capacitance nCb of column electrode line group
It is possible to achieve a large capacity, reduce the effects of static electricity, and reduce damage to the array substrate due to static electricity.
つまり、静電気の充放電を行または列電極のそれぞれ切
り離された状態で特定の電極線において生じた場合は、
静電気の電荷量をQとすると、行および列電極線に生じ
る電位はそれぞれVa=Q/Ca ・−・11)
vb= Q / cb −−−−−−(2)とな
る。一方、それぞれの電極線が並列に短絡された場合は
、行および列電極に生じる電位は、静電気の電荷が全体
に分散され、それぞれVa’ = Q / m Ca
−−(3)Vb’=Q/nCb ・−−−−・(
4)となり、静電気に対するアレー基板への影響が行・
列電極線において、行・列電極線の数の逆数だけ低減さ
れたものとなる。In other words, if static electricity is charged and discharged in a specific electrode line with the row or column electrodes separated,
When the amount of static electricity is Q, the potentials generated in the row and column electrode lines are Va=Q/Ca (11) vb=Q/cb (2). On the other hand, when the respective electrode lines are short-circuited in parallel, the potentials generated at the row and column electrodes are such that the electrostatic charges are distributed throughout, and Va' = Q / m Ca
--(3) Vb'=Q/nCb ・------・(
4), and the effect of static electricity on the array substrate is
The number of column electrode lines is reduced by the reciprocal of the number of row and column electrode lines.
一方、パネル組立工程3のうちの画像検査工程4におい
ても、導電部材A□またはA、、 B、またはB2のそ
れぞれに液晶表示装置を動作させるのに近い信号を印加
することによって、模擬的に画像検査が行なえるため、
パネルの選別を行なった後より表示装置として組立てる
までのハンドリング時に発生する静電気による破壊を防
止することができる。On the other hand, in the image inspection step 4 of the panel assembly step 3, a signal similar to that used to operate a liquid crystal display device is applied to each of the conductive members A□, A, B, or B2 to simulate the operation of the liquid crystal display device. Because image tests can be performed,
It is possible to prevent damage caused by static electricity generated during handling from the time the panels are sorted to the time they are assembled into a display device.
さらに、アレー電気検査の段階において、行電極線およ
び列電極線が、導電部材A工またはA 2 HBlまた
はB2によって電気的に短絡されているので導電部材A
1またはA、、B□またはB2の一箇所に信号を印加す
ることにより、アレー基板上の行・列間の短絡不良やそ
の他の検査が行えるため、アレー検査自身も簡略化でき
る。Furthermore, at the stage of array electrical inspection, the row electrode lines and the column electrode lines are electrically short-circuited by the conductive member A or A 2 HBl or B2, so the conductive member A
By applying a signal to one location of 1 or A, , B□ or B2, it is possible to inspect short circuits between rows and columns on the array substrate and other defects, thereby simplifying the array inspection itself.
このように、第2図に示すパネル製造工程において、静
電対策パターンを有したままほとんどの検査が行えるた
め、静電対策パターンの形成−除去を1回または2回で
済ませることができ、従来のものの3回に比べて製造工
程を非常に簡略化できる。たとえば、第2図において、
(イ)または(ロ)の工程を用いることが可能となり、
静電対策パターンの形成・除去の回数を低減させること
ができる格別の効果を得ることができる。In this way, in the panel manufacturing process shown in Figure 2, most inspections can be performed with the anti-static pattern still in place, so the formation and removal of the anti-static pattern can be completed in one or two times, compared to conventional methods. The manufacturing process can be greatly simplified compared to the previous three times. For example, in Figure 2,
It becomes possible to use the process (a) or (b),
A special effect can be obtained in that the number of times of formation and removal of electrostatic countermeasure patterns can be reduced.
なお、第1図においては、行電極線および列電極線の両
方をその両端で並列に電気的に短絡する場合を説明した
が、これは効果を最大限に発輝するためには最良の例で
ある。しかし、第1図の例に限定されるものではなく、
他の例として第1図におけるA1のみ、またはB1のみ
、あるいはA1とB1など静電気による破壊に対し影響
を受けやすい電極線のみまたは電極線の一端また両端に
電気的に並列に短絡を施すことによっても効果を期待で
きる。In addition, in Fig. 1, we have explained the case where both the row electrode line and the column electrode line are electrically short-circuited at both ends, but this is the best example to maximize the effect. It is. However, it is not limited to the example shown in FIG.
Other examples include only A1 in FIG. 1, only B1, or only electrode wires such as A1 and B1 that are susceptible to destruction by static electricity, or by electrically shorting one or both ends of the electrode wires in parallel. can also be expected to be effective.
発明の効果
以上のように、本発明のアクティブマトリクス表示装置
の製造方法によれば、アレー基板の各電極線の形成と同
時にまたはアレー基板完成後に行電極線および列電極線
のそれぞれが電気的に並列に短絡されるため、パネル組
立や画像検査その他のハンドリング時に静電気による破
壊を防ぐことが可能であり、かつ、その状態でもアレー
基板および表示パネルの特性の測定が可能である。した
がって、静電対策パターンの形成−除去の回数を減らす
ことができ、コストの低減が可能となる。Effects of the Invention As described above, according to the method for manufacturing an active matrix display device of the present invention, each of the row electrode lines and column electrode lines is electrically connected simultaneously with the formation of each electrode line of the array substrate or after the completion of the array substrate. Since they are short-circuited in parallel, it is possible to prevent damage due to static electricity during panel assembly, image inspection, and other handling, and it is also possible to measure the characteristics of the array substrate and display panel even in this state. Therefore, it is possible to reduce the number of times the electrostatic countermeasure pattern is formed and removed, and costs can be reduced.
第1図は本発明の製造方法の一実施例におけるアクティ
ブマトリクス表示装置のマトリクスアレー基板の概略平
面図、第2図は同マトリクスアレー基板の製造工程を示
すフロー図、第3図はマトリクスアレー基板の構成を示
す概略平面図、第4図は従来のマトリクスアレー基板の
製造工程を示すフロー図、第5図は従来の製造方法にお
けるマトリクスアレー基板の概略平面図である。
aよ〜a9・・・行電極線、b工〜b8・・・列電極線
、c1□・・・スイッチング素子、d xx・・・絵素
電極、A□。
A、、B□、B2・・・導電部材。
代理人 森 本 義 弘
第1図
y
5゜
az % aq−−一行電麺
bt −bs−−一列1如陳
Cn−一−ス不y+ン2素手
dtt−一一絞青鎌
A、A2.Btlh−4’l晴ル
第2図
第3図
第4図
第5図
tFIG. 1 is a schematic plan view of a matrix array substrate of an active matrix display device in one embodiment of the manufacturing method of the present invention, FIG. 2 is a flow diagram showing the manufacturing process of the matrix array substrate, and FIG. 3 is a matrix array substrate. FIG. 4 is a flow diagram showing the manufacturing process of a conventional matrix array substrate, and FIG. 5 is a schematic plan view of the matrix array substrate in the conventional manufacturing method. a~a9...row electrode line, b~b8...column electrode line, c1□...switching element, dxx...pixel electrode, A□. A,, B□, B2... Conductive member. Agent Yoshihiro Morimoto 1st figure y 5゜az % aq--1 line denmen bt -bs--1 row 1 RuchenCn-1-sufuy+n 2 bare hands dtt-11 squeeze blue sickle A, A2. Btlh-4'l Haru Figure 2 Figure 3 Figure 4 Figure 5 t
Claims (1)
の列電極線、および前記行電極線と列電極線との交点に
スイッチング素子および絵素電極を有するアクティブマ
トリクスアレー基板と、少なくとも一部に透明電極を有
する対向基板と、それらの基板間に挟持された液晶とか
らなるアクティブマトリクス表示装置の製造方法であっ
て、前記アクティブマトリクスアレー基板の製作中また
は製作が終了した後に、前記行電極線と列電極線の少な
くとも一方の一端または両端を行は行どうし、列は列ど
うしを互いに電気的に並列に短絡させ、その後に前記対
向基板と貼り合せて液晶を挟持させ、所定検査後に前記
電気的短絡を切り離すアクティブマトリクス表示装置の
製造方法。1. an active matrix array substrate having a plurality of row electrode lines, a plurality of column electrode lines intersecting the row electrode lines, and switching elements and picture element electrodes at the intersections of the row electrode lines and the column electrode lines; A method for manufacturing an active matrix display device comprising a counter substrate having a transparent electrode on at least a portion thereof and a liquid crystal sandwiched between these substrates, the method comprising: during or after manufacturing the active matrix array substrate; One end or both ends of at least one of the row electrode wire and the column electrode wire are electrically shorted in parallel between the rows and the columns, and then bonded to the counter substrate to sandwich the liquid crystal, and A method of manufacturing an active matrix display device, which disconnects the electrical short circuit after inspection.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62124519A JP2723517B2 (en) | 1987-05-20 | 1987-05-20 | Active matrix array substrate for inspection and method of manufacturing active matrix display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62124519A JP2723517B2 (en) | 1987-05-20 | 1987-05-20 | Active matrix array substrate for inspection and method of manufacturing active matrix display device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63287826A true JPS63287826A (en) | 1988-11-24 |
JP2723517B2 JP2723517B2 (en) | 1998-03-09 |
Family
ID=14887489
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62124519A Expired - Lifetime JP2723517B2 (en) | 1987-05-20 | 1987-05-20 | Active matrix array substrate for inspection and method of manufacturing active matrix display device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2723517B2 (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5895383A (en) * | 1981-11-30 | 1983-06-06 | 株式会社東芝 | Matrix type display |
JPS6148978A (en) * | 1984-08-16 | 1986-03-10 | Seiko Epson Corp | Active matrix substrate |
-
1987
- 1987-05-20 JP JP62124519A patent/JP2723517B2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5895383A (en) * | 1981-11-30 | 1983-06-06 | 株式会社東芝 | Matrix type display |
JPS6148978A (en) * | 1984-08-16 | 1986-03-10 | Seiko Epson Corp | Active matrix substrate |
Also Published As
Publication number | Publication date |
---|---|
JP2723517B2 (en) | 1998-03-09 |
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