JP3327739B2 - Active matrix substrate - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix substrate suitably used for a display device using, for example, a liquid crystal.

[0002]

2. Description of the Related Art FIG. 9 is a plan view showing the structure of a conventional active matrix substrate 1. As shown in FIG. FIG. 10 is a plan view showing a region of one picture element surrounded by the gate wiring G and the data wiring D. FIG. 11 is a sectional view taken along line II of FIG. The active matrix substrate 1 includes an insulating substrate 2,
Gate wiring G, data wiring D, terminals TG, TD, gate and data short-circuit wiring 4, picture element electrode 6, and TFT
(Thin film transistor) It is configured to include the element 7.

An insulating substrate 2 made of, for example, glass
On one surface 2a, strip-shaped gate wirings G made of n Tas or the like are formed parallel to each other with an interval. Further, strip-shaped data wirings D realized by m Tas or the like are formed with a gate insulating film to maintain insulation from the gate wirings G and to be spaced apart from each other in a direction orthogonal to the gate wirings G. . A plurality of rectangular regions 5 formed by intersecting the gate lines G and the data lines D are picture element regions, and the display regions 3 are constituted by the plurality of picture element regions 5. N and m are positive integers.

In one picture element region 5, a picture element electrode 6 and a TFT element 7 are provided as shown in FIG. TF
The T element 7 connects the picture element electrode 6 to the gate wiring G and the data wiring D, and as shown in FIG. 11, the gate electrode 8, the gate insulating film 9, the a-Si layer 10,
Etching stopper layer 11, n ⁺ a-Si layer 12, 1
3, including the source electrode 14 and the drain electrode 15. The gate electrode 8 is connected to the gate line G, and the gate insulating film 9 is formed on the entire surface of one surface 2a of the substrate 2 so as to cover the gate line G and the gate electrode 8. On the surface of the gate insulating film 9 on the gate electrode 8, an a-Si layer 10 and an etching stopper layer 11 are formed in order, and furthermore, an n ⁺ a-layer is formed in a region where the source electrode 14 and the drain electrode 15 are to be formed. Si layers 12 and 13 are respectively formed. Source electrode 14 formed on one n ⁺ a-Si layer 12 is connected to data line D, and the other n ⁺ a-S
The drain electrode 15 formed on the i-layer 13 is
Connected to The picture element electrode 6 is realized by a transparent electrode such as ITO (indium tin oxide), and the gate electrode 8, the source electrode 14 and the drain electrode 15 are realized by Ta, for example.

[0005] On one surface 2a of the insulating substrate 2, a ring-shaped gate and a data shorting wiring 4 are formed so as to surround the gate wiring G and the data wiring D. Here, the wiring 4 is configured by the wirings 4a to 4d formed substantially in parallel along four sides of the one surface 2a of the insulating substrate 2 having a rectangular shape. Terminals TG and TD are formed at one end of the gate wiring G and the data wiring D, respectively. The gate wiring G and the data wiring D are connected to the gate and the data short wiring 4 via the terminals TG and TD. An active matrix substrate 1 having such a configuration is disclosed in, for example, Japanese Patent Application Laid-Open No. 3-116117.

For example, when assembling a liquid crystal display device,
The active matrix substrate 1 having such a shape is used, and the dielectric breakdown of the TFT element 7 and the intersection of the wirings G and D due to static electricity generated by friction or the like during an assembly operation is prevented. That is, the static electricity is transmitted to all the gate wirings G and all the data wirings D by the gate and the data shorting wiring 4. As a result, the potential does not partially become high, and dielectric breakdown can be prevented.
Finally, the region of the insulating substrate 2 on which the gate and the data short-circuit wiring 4 are formed is cut to complete the liquid crystal display device.

When a liquid crystal display device is manufactured, whether a good display state is obtained, that is, whether a break occurs in the gate wiring G and the data wiring D, whether the gate wiring G and the data wiring D are present or not. Is checked for a short circuit. For example, the inspection for disconnection is performed by applying a single inspection signal having the same waveform from the terminals TG and TD to the gate wiring G and the data wiring D before cutting the gate and the data shorting wiring 4 respectively. Will be Inspection of a short circuit is performed by cutting a portion of the gate and the data short-circuit wire 4 and then applying different test signals to the adjacent wires to the gate wire G and the data wire D.

FIG. 12 is a plan view showing another example of the area of one picture element. In the other example, the conductor layer 16 connected to the pixel electrode 6 is formed on the gate wiring G different from the gate wiring G to which the pixel electrode 6 is connected by the TFT element 7 via the gate insulating film 9. Capacitance element 1 which is arranged and includes the gate wiring G, the gate insulating film 9 and the conductor layer 16.
7 is characterized. Such a configuration is a so-called Cs on Gate system. When a data signal is applied to the data line D and the gate line G is selected, the TFT element 7 is turned on, and the data signal is applied to the pixel electrode 6. At this time, a predetermined charge is charged in the auxiliary capacitance element 17 in order to maintain sufficient display contrast and obtain high display reliability.

In the case of such a configuration, before disconnection of the gate and the data short-circuit wiring 4, a disconnection test in which a single test signal is applied to the gate wiring G, the adjacent gate wiring G has the same waveform. Since the signal is supplied, the above-described charging cannot be performed reliably, a good display state cannot be obtained, and the occurrence of disconnection cannot be confirmed. Therefore, a disconnection inspection is performed after the gate and the data short-circuit wiring 4 are cut off.

[0010]

In the prior art active matrix substrate 1 having the structure shown in FIG.
After the portion of the wiring 4 is cut, an inspection for a short circuit is performed.
In the conventional active matrix substrate 1 having the structure shown in FIG. 2, inspection for disconnection and short circuit is performed after the wiring 4 is partially cut. For this reason, static electricity is generated in the inspection and assembling steps after the cutting, which causes dielectric breakdown at intersections of the TFT elements 7 and the wirings, thereby increasing the incidence of defective products. As described above, it is impossible to carry out inspection and assembly after sufficiently taking measures against static electricity in the above-described conventional technology.

[0011] Further, a configuration which enables disconnection and short-circuit inspection before cutting the portion of the wiring 4 is disclosed in Japanese Patent Publication No. Hei 7-1164.
No. 0 discloses this. In this configuration, the gate electrode G and the data line D are connected to the metal film formed on the insulating substrate by a plurality of lines alternately and the common electrode formed outside the input terminals of the gate line G and the data line D. The pattern and the metal film are connected via a capacitor. Such a capacitor portion is a portion that is ultimately cut, and it is generally preferable to create the capacitor portion without any effort and cost, and after taking sufficient measures against static electricity with a simpler configuration, Inspection and assembly are desired.

It is an object of the present invention to provide an active matrix substrate capable of performing an inspection for disconnection and short-circuit of a wiring while taking sufficient countermeasures against static electricity with a simpler configuration.

[0013]

SUMMARY OF THE INVENTION The present invention relates to an insulating substrate and a plurality of band-shaped gates formed on one surface of the insulating substrate at intervals in parallel with each other and having terminals formed at one end thereof. Wiring and a plurality of strips formed on one surface of an insulating substrate, which are spaced apart from each other in a direction orthogonal to the gate wiring while maintaining insulation from the gate wiring, and having terminals formed at one end thereof. A data line, a pixel electrode provided for each of a plurality of rectangular pixel regions formed by intersecting the gate line and the data line, and a pixel electrode, a gate, and a data provided for each pixel region. A switching element for individually connecting the wiring and, on one surface of the insulating substrate, are formed in a ring shape at intervals from each other along a peripheral portion of the insulating substrate so as to surround all the gate wiring and the data wiring, Game A plurality of short-circuit wirings in which at least one of the wirings and the data wirings are sequentially connected at predetermined intervals through respective terminals, and an insulating film formed to cover the short-circuit wirings An active matrix substrate characterized by including: According to the present invention, a plurality of gate wirings and a plurality of data wirings are arranged on an insulating substrate so as to be orthogonal to each other. In addition, short-circuit wires are arranged along the periphery of the insulating substrate so as to surround all the gate wires and the data wires. A plurality of short-circuit wirings are formed, and at least one of the gate wirings and the data wirings is sequentially connected via a respective terminal at predetermined intervals. In a plurality of rectangular picture element regions formed by the intersection of the gate wiring and the data wiring, a picture element electrode and a switching element are provided. Since at least one of the plurality of gate lines and the data lines is sequentially connected via the terminals at predetermined intervals through the terminals, for example, static electricity generated at the time of assembling a liquid crystal display device or the like. Can be prevented from being transmitted to a plurality of wirings connected to each other and having only a portion at a high potential, thereby preventing dielectric breakdown. Although the substrate portion on which such a short-circuit wiring is formed is finally cut, in the configuration of the present invention, it is determined whether or not a break has occurred in the gate wiring and the data wiring before cutting. Whether a short circuit has occurred,
Alternatively, it can be inspected whether a short circuit has occurred between the data wirings. For example, inspection of disconnection of gate wiring
This can be performed by applying a single inspection signal having the same waveform to all the short-circuit wirings and measuring the resistance value. As a result, the same signal is applied to all the gate lines. Inspection of a short circuit of a gate wiring can be performed by giving a test signal of a different waveform to at least an adjacent short wiring to a short wiring connected to the gate wiring, and measuring a resistance value. . As a result, different signals are applied to at least adjacent gate wirings. For data wiring, disconnection and short-circuit inspection can be performed in the same manner. If it is determined that no disconnection or short circuit has occurred by performing such an inspection, the substrate portion on which the short-circuit wiring is formed is cut. As described above, disconnection and short-circuit can be inspected in a state where at least one of the plurality of gate wirings and the data wiring is short-circuited. Therefore, it is possible to prevent the dielectric breakdown at the intersection of the switching element and the wiring due to the static electricity generated during the inspection. Further, unlike the related art, it is not necessary to provide a capacitor, and it is possible to perform an inspection for disconnection and short circuit of the wiring after taking countermeasures against static electricity with a relatively simple configuration. In addition, by connecting all the gate wirings to one of the plurality of short-circuiting wirings, the gate wirings and the data wirings are provided with a simple configuration for preventing static electricity, and then the disconnection and the short-circuiting of the data wirings are inspected. And inspection of disconnection of the gate wiring. In addition, by connecting all the data wirings to one of the plurality of short-circuiting wirings, the gate wirings and the data wirings are provided with a simple configuration for preventing static electricity, and then the disconnection and the short-circuiting of the gate wirings are inspected. Inspection of disconnection of data wiring can be performed. Further, the connection of the short-circuit wiring is performed via respective terminals of the gate wiring and the data wiring.

Further, the short-circuit wiring of the present invention is connected to a plurality of gate short-circuit wirings in which gate wirings are sequentially connected at predetermined intervals, and data wirings are sequentially connected at predetermined intervals. And a plurality of data short-circuit wirings. According to the invention, the short-circuit wiring includes a plurality of gate short-circuit wirings and a plurality of data short-circuit wirings. Therefore, it is possible to inspect disconnection and short-circuit of the gate wiring and the data wiring in a state where both the gate wiring and the data wiring have taken sufficient countermeasures against static electricity.

Further, according to the present invention, a picture element electrode is formed on a gate wiring different from a gate wiring connected by a switching element via an insulator, provided for each picture element region.
It is characterized by including a conductor layer connected to the picture element electrode.
According to the present invention, an auxiliary capacitance element is provided for each picture element region. The auxiliary capacitance element includes a conductor layer formed on a gate wiring different from a gate wiring to which a pixel electrode is connected by a switching element via an insulator, a gate wiring on which the conductor layer is stacked, and the insulator. Is done. In the case where such an auxiliary capacitance element is provided, if an inspection signal having the same waveform is applied to an adjacent gate wiring, the auxiliary capacitance element cannot be reliably charged, a good display state cannot be obtained, and disconnection occurs. Although it is not possible to reliably check for the presence of
By sequentially connecting the gate lines to a plurality of gate short-circuit lines at predetermined intervals, the inspection signal having the same waveform is not given to the adjacent gate lines, and the charging is performed reliably. A good display state can be obtained, and the presence or absence of disconnection can be reliably inspected.

[0016]

FIG. 1 is a plan view showing the structure of an active matrix substrate 21 according to a first embodiment of the present invention. FIG. 2 is an enlarged partial plan view showing the active matrix substrate 21. FIG. 3 is a cross-sectional view of FIG.
It is II sectional drawing. The active matrix substrate 21
Insulating substrate 22, gate wiring G, data wiring D, terminal T
G, TD, gate short wiring 24, data short wiring 2
5 to 27, connecting wires 28 to 30 and gate insulating film 3
2 is included.

An insulating substrate 2 made of, for example, glass
On one surface 22a of each of the two, band-shaped gate wirings G made of n Tas or the like are formed parallel to each other and spaced from each other. Further, strip-shaped data wirings D realized by m Tas or the like are kept insulated from the gate wirings G by the gate insulating film 32 and are spaced apart from each other in a direction orthogonal to the gate wirings G. It is formed. A plurality of rectangular regions 31 formed by intersecting the gates and the data lines G and D are picture element regions, and a plurality of picture element regions 3 are formed.
1 constitutes a display area 23. In one picture element region 31, a picture element electrode and a TFT element, which will be described later, and an auxiliary capacitance element are formed. N and m are positive integers.

On one surface 22a of the insulating substrate 22, a ring-shaped gate shorting wire 24 and a plurality (three in this embodiment) of data are provided so as to surround all the gate wires G and all the data wires D. Short-circuit wirings 25 to 27 are formed at intervals from each other. In this embodiment,
The wiring 24 is formed by wirings 24a to 24d formed substantially in parallel along four sides of one surface 22a of the rectangular insulating substrate 22, and the wiring 25 is formed by wirings 25a to 25d.
However, the wiring 26 is changed to the wiring 27 by the wirings 26a to 26d.
The wirings 27 are respectively constituted by a to 27d. The wirings 25a to 25d are outside the wirings 24a to 24d, the wirings 26a to 26d are outside the wirings 25a to 25d, and the wiring 2
Wirings 27a to 27d are formed outside 6a to 26d, respectively.

A terminal T is provided at one end of the plurality of gate lines G.
G are formed, and all the gate lines G are connected to the gate short-circuit line 24 via the terminal TG. A terminal TD is formed at one end of each of the plurality of data wirings D, and the plurality of data wirings D are respectively connected to data shorting wirings 25 to 27 by connection wirings 28 to 30 formed by connecting to the terminals TD. Connected. The wiring 28 is for connecting the data wiring D to the data shorting wiring 25, the wiring 29 is for connecting the data wiring D to the data shorting wiring 26, and the wiring 30 is for connecting the data wiring D. This is for connecting to the data short-circuit wiring 27.

Referring to FIGS. 2 and 3, gate short-circuiting wiring 24 and data short-circuiting wirings 25 to 27 are formed in the order of gate insulating film 32 on each wiring formed outward of insulating substrate 22. On the front surface, the connection wiring 28 extends to the area of the data shorting wiring 25, the connection wiring 29 extends to the area of the data shorting wiring 26, and the connection wiring 30 extends to the area of the data shorting wiring 27. Formed.

Gate insulating film 3 on data shorting wiring 25
A contact hole 28a (shown by diagonal lines in FIG. 2) is formed in the region 2 where the wiring 28 is formed. Thus, the wiring 28 directly contacts the data shorting wiring 25, and the data wiring D1 and the data shorting wiring 25 are connected. In a region of the gate insulating film 32 on the data short-circuiting wiring 26 and in a region where the wiring 29 is formed, a contact hole 29a (shown by hatching in FIG. 2) is formed. As a result, the wiring 29 directly contacts the data shorting wiring 26, and the data wiring D2 and the wiring 26 are connected. Data short wiring 2
In the region of the gate insulating film 32 on the gate 7 and in the region where the wiring 30 is formed, a contact hole 30a (shown by hatching in FIG. 2) is formed. Thus, the wiring 30 directly contacts the wiring 27, and the data wiring D3
And the wiring 27 are connected.

Thus, the plurality of data lines D are 2
Every other is connected to the same data short-circuit wiring 25-27. In this embodiment, an example will be described in which three data short-circuit wirings are formed and every third data wiring D is connected to the same data short-circuit wiring. However, the number of data short-circuit wirings is not limited to three. The data wirings D may be connected to a plurality of data shorting wirings at predetermined intervals.

FIG. 4 shows a gate wiring G and a data wiring D
It is a top view which shows the area | region of one picture element enclosed with. FIG. 5 is a sectional view taken along line III-III of FIG. One picture element area 31
Is provided with a pixel electrode 33 and a TFT element 34.

The TFT element 34 connects the picture element electrode 33 to the gate wiring G and the data wiring D, and includes a gate electrode 35, a gate insulating film 32, and an a-Si layer 3.
6, etching stopper layer 37, n ⁺ a-Si layer 38,
39, a source electrode 40 and a drain electrode 41. The gate electrode 35 is connected to the gate line G, and the gate insulating film 32 is formed on the entire surface of one surface 22 a of the substrate 22 so as to cover the gate line G and the gate electrode 35. On the surface of the gate insulating film 32 on the gate electrode 35,
An a-Si layer 36 and an etching stopper layer 37 are formed in this order, and further, in a region where a source electrode 40 and a drain electrode 41 are to be formed, an n ⁺ a-Si layer 38,
39 are formed respectively. One n ⁺ a-Si layer 38
The source electrode 40 formed thereon is connected to the data wiring D, and the drain electrode 41 formed on the other n ⁺ a-Si layer 39 is connected to the pixel electrode 33. Picture element electrode 33
Is realized by a transparent electrode such as ITO, for example, and includes a gate line G, a data line D, a gate electrode 35, and a source electrode 4.
Zero and drain electrode 41 are realized, for example, by Ta.

The active matrix substrate 21 having such a structure is manufactured as follows. First, for example, a Ta film is formed on one surface 22a of the insulating substrate 22 over the entire surface, and the Ta film is patterned to form the gate wiring G, the terminal TG, the gate short wiring 24, and the data short wiring 25 to 27 are formed simultaneously. A gate insulating film 32 is formed on the entire surface of the surface 22a on which these members are patterned to cover all the formed members. Further, the constituent members of the TFT element 34 other than the source electrode 40 and the drain electrode 41 and the pixel electrode 33 are formed in each of the pixel regions. Contact holes 28a to 30a are formed at predetermined locations in the gate insulating film 32 where these are formed. Further, for example, a Ta film is formed on the entire surface covering the formed member, and the Ta film is patterned to form a source electrode 40 and a drain electrode 4.
1, data line D, terminal TD, and connection lines 28 to 3
0 is formed.

The active matrix substrate 21 produced in this manner is used, for example, in a liquid crystal display device by disposing a liquid crystal layer between the active matrix substrate 21 and a counter substrate. The counter substrate is formed by forming a counter electrode facing the pixel electrode 33 on an insulating substrate made of, for example, glass.

Active matrix substrate 21 of this embodiment
Are short-circuited by connecting all of the plurality of gate wires G to the gate short-circuit wire 24, and the plurality of data wires D are connected to the data short-circuit wires 25 to 27 by a predetermined number, respectively. Shorted every time. For this reason, when assembling a liquid crystal display device using the active matrix substrate 21, for example, it is possible to prevent a partially high potential due to static electricity generated by friction or the like, and the intersection of the TFT element 34 and the wirings G and D due to the static electricity. Partial dielectric breakdown can be prevented.

Also, whether or not a good display state can be obtained,
That is, the inspection as to whether the gate wiring G and the data wiring D are disconnected or short-circuited is performed as follows. First, disconnection inspection is performed by applying a single inspection signal having the same waveform to all the gate lines G and the data lines D via the lines 24-27. Inspection of a short circuit between adjacent data lines D is performed by applying inspection signals having different waveforms to the adjacent lines 25 to 27 and applying an inspection signal to the data lines D via the lines 25 to 27. As a result, different test signals are applied to the adjacent data lines D. In this embodiment,
A different inspection signal can be applied to every two data lines D, and three types of inspection signals can be applied.

As a result of such inspection, if it is determined that no disconnection or short circuit has occurred, the active matrix substrate 2
1 is cut into a portion where the wirings 24 to 27 are formed and a portion other than the portion.

As described above, according to the configuration of the active matrix substrate 21 of the present embodiment, in a state where countermeasures against static electricity are taken,
An inspection for disconnection of the gate wiring G and an inspection for disconnection and short-circuit of the data wiring D can be performed. Accordingly, the TFT element 34 and the wiring G,
The dielectric breakdown at the intersection of D can be prevented. Also, it is possible to take measures against static electricity only by connecting the gate wiring G and the data wiring D to the short-circuit wirings 24 to 27 formed on the one surface 22a of the insulating substrate 22 along the periphery of the insulating substrate 22. Can be made, and short-circuit wires 24-2
7 can be easily formed simultaneously with the gate wiring G.

FIG. 6 is an enlarged partial plan view showing an active matrix substrate 44 according to a second embodiment of the present invention. FIG. 7 is a sectional view taken along line IV-IV and VV of FIG. The active matrix substrate 44 has a configuration similar to that of the active matrix substrate 21, but a plurality (two in this embodiment) of gate short-circuit wirings 2.
4 and 42 are provided, and every other gate wiring G is connected to the same wiring 24 and 42. The same components as those of the active matrix substrate 21 are denoted by the same reference numerals.

The wiring 42 for the gate short-circuit is composed of the wirings 24 to 27
Similarly to the above, four wirings are formed substantially in parallel along four sides of one surface 22a of the insulating substrate 22, and each wiring is formed outside the wirings 27a to 27d.
The gate line G1 is the gate short-circuit line 2 as in the above embodiment.
4 is connected. The gate wiring G2 is connected to a gate short-circuit wiring 42 via a connection wiring 43 connected to a terminal TG2 formed at one end of the wiring G2. The connection wiring 43 is on the gate insulating film 32 and is connected to the terminal T
It is formed to extend from the region where G2 is disposed to the region where the gate short wiring 42 is disposed. Gate insulating film 32
, Contact holes 43a and 43b (shown by diagonal lines in FIG. 6) are formed in portions on the terminal TG2 and the gate short wiring 42, respectively. Thus, the connection wiring 43 directly contacts the terminal TG2 and the wiring 42, and the gate wiring G2 and the wiring 42 are connected.

In this manner, every other gate wiring G is connected to the same wiring 24, 42. In this embodiment,
Two gate short-circuit wirings are formed, and the gate wiring G becomes 1
Although an example in which every other line is connected to the same short-circuit line will be described, the number of gate short-circuit lines is not limited to two. I just need.

The active matrix substrate 44 having such a structure is manufactured as follows. Insulating substrate 22
On the one surface 22a, the gate wiring G, the terminal TG, and the wirings 24-27, 42 are simultaneously formed in the same manner as described above. Further, a gate insulating film 32 is formed on the entire surface so as to cover all the formed members. Further, the constituent members of the TFT element 34 other than the source electrode 40 and the drain electrode 41 and the picture element electrode 33 are formed. The gate insulating film 32 has contact holes 28a to 30a, 43
a, 43b are formed. Further, a Ta film, for example, is formed on the entire surface covering the formed member, and the film is patterned to form a source electrode 40, a drain electrode 41, a data wiring D, a terminal TD, and wirings 28 to 30, 43. .

The active matrix substrate 44 of the present embodiment
Means that a plurality of gate wirings G are formed by a predetermined number of wirings 24 and 42 respectively.
, And short-circuited for each of the wirings 24 and 42, a plurality of data wirings D are connected to the wirings 25 to 27 by a predetermined number, and short-circuited for each of the wirings 25 to 27. Therefore, similarly to the above-described embodiment, the TFT element 34 caused by static electricity during inspection and assembly is used.
And the dielectric breakdown at the intersection of the wires G and D can be prevented.

The inspection of the short circuit can be performed not only for the data wiring D but also for the gate wiring G. In this embodiment, two types of inspection signals can be given to every other gate wiring G.

FIG. 8 is a plan view showing another example of the area of one picture element. In the other example, the conductor layer 45 connected to the pixel electrode 33 is provided on a gate wiring G different from the gate wiring G to which the pixel electrode 33 is connected by the TFT element 34.
It is characterized by having an auxiliary capacitance element 46 which is arranged via the gate insulating film 32 and comprises the gate wiring G, the gate insulating film 32 and the conductor layer 45. Such a configuration is a so-called Cson Gate system. For example, a data signal is applied to data line D and gate line G
Is selected, the TFT element 34 is turned on, and a data signal is applied to the pixel electrode 6. At this time, in order to maintain sufficient display contrast and obtain high display reliability, the auxiliary capacitance element 46 is charged with a predetermined charge.

The above-described second embodiment provides a particularly excellent effect in an active matrix substrate having such an auxiliary capacitance element 46. That is, the auxiliary capacitance element 46 is configured to include the gate wiring G adjacent to the gate wiring G to which the pixel electrode 33 is connected via the TFT element 34. When a data signal is applied to the data line D and the gate line G is selected, the auxiliary capacitance element 46 charges. Therefore, in the configuration of the first embodiment, a single inspection signal having the same waveform is applied to the adjacent gate lines G at the time of inspection for disconnection of the gate line G, so that a normal charging operation in the auxiliary capacitance element 46 is performed. This is not performed, and it is not possible to reliably inspect whether or not the gate wiring G is disconnected.

However, according to the configuration of the second embodiment, different inspection signals can be applied to every other gate wiring G. For example, an inspection signal is applied to one gate wiring G and the other gate wiring is applied. By not giving it to G, a normal charging operation can be performed, and the inspection for disconnection of the gate wiring G can be reliably performed. In the configuration of the present embodiment, the data line D
In the same manner as described above, a short-circuit inspection can be performed, and a more detailed inspection can be performed.

Further, as a third embodiment of the present invention,
A configuration in which the data wirings D of the first embodiment are all connected to one data shorting wiring, and the gate wirings G are connected to a plurality of (for example, two as in the second embodiment) gate shorting wirings. Can be realized. In this case, disconnection and short-circuit can be inspected for the gate line G, and disconnection can be inspected for the data line D.

In the three embodiments described above, the example in which the TFT element 34 is used as the switching element has been described. However, the switching element is not limited to the TFT element.
For example, an MIM (Metal-Insulator-Metal) element may be used. In addition, short-circuit wirings 24 to 27, 42
May not be formed simultaneously with the gate wiring G, and may be formed simultaneously with the data wiring D, for example.

[0042]

As described above, according to the present invention, at least one of the plurality of gate wirings and data wirings is connected via the respective terminals by the short-circuiting wiring. The static electricity generated at the time of assembling is transmitted to the connected wiring, and it is possible to prevent only a part of the wiring from becoming a high potential, thereby preventing the switching element and the wiring intersection from being broken down. In addition, it is possible to inspect the disconnection and short-circuit of the gate wiring and the data wiring while leaving the portion where the short-circuit wiring is formed. Therefore, disconnection and short-circuit can be inspected in a state where sufficient measures against static electricity are taken, and insulation breakdown due to static electricity generated at the time of inspection can be prevented.
In addition, the short-circuit wiring can be performed via respective terminals of the gate wiring and the data wiring.

Further, by connecting all the gate wirings to one of the plurality of short-circuit wirings, the inspection for disconnection and short-circuit of the data wiring and the inspection for disconnection of the gate wiring are performed in a state where countermeasures against static electricity are taken. Can be done with

Further, by connecting all the data wirings to one of the plurality of short-circuit wirings, the inspection for disconnection and short-circuit of the data wiring and the inspection for disconnection of the gate wiring are performed in a state where countermeasures against static electricity are taken. Can be done with

Further, according to the present invention, the short-circuit wiring includes the gate short-circuit wiring and the data short-circuit wiring. Therefore, the inspection can be performed in a state where sufficient measures against static electricity are taken for both the gate wiring and the data wiring.

According to the present invention, the auxiliary capacitance element is provided in the picture element region. Although the auxiliary capacitance element is provided on a gate wiring different from the gate wiring to which the pixel electrode is connected by the switching element, a different inspection signal can be given to the adjacent gate wiring, so that the auxiliary capacitance element is charged. This can be performed reliably, a good display state can be obtained, and the presence or absence of disconnection can be reliably confirmed.

[Brief description of the drawings]

FIG. 1 is a plan view showing a configuration of an active matrix substrate 21 according to a first embodiment of the present invention.

FIG. 2 is an enlarged partial plan view showing an active matrix substrate 21;

FIG. 3 is a sectional view taken along line II-II of FIG. 2;

FIG. 4 is a plan view showing an area of one picture element.

FIG. 5 is a sectional view taken along the line III-III in FIG. 4;

FIG. 6 is an enlarged partial plan view showing an active matrix substrate 44 according to a second embodiment of the present invention.

FIG. 7 is a sectional view taken along lines IV-IV and VV of FIG. 6;

FIG. 8 is a plan view showing another example of the area of one picture element.

FIG. 9 is a plan view showing a configuration of a conventional active matrix substrate 1.

FIG. 10 is a plan view showing a region of one picture element.

FIG. 11 is a sectional view taken along the line II of FIG. 10;

FIG. 12 is a plan view showing a region showing another example of one picture element.

[Explanation of symbols]

 21, 44 Active matrix substrate 22 Insulating substrate 23 Display region 24, 42 Wiring for gate shorting 25 to 27 Wiring for data shorting 28 to 30, 43 Wiring for connection 28a to 30a, 43a, 43b Contact hole 31 Pixel region 32 Gate Insulating film 33 Pixel electrode 34 TFT element 35 Gate electrode 40 Source electrode 41 Drain electrode 45 Conductive layer 46 Auxiliary capacitance element

 ──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-3-94223 (JP, A) JP-A-4-287020 (JP, A) JP-A-6-160901 (JP, A) JP-A-6-160901 130412 (JP, A)

Claims (3)

(57) [Claims] An insulating substrate; a plurality of strip-shaped gate wirings formed on one surface of the insulating substrate at intervals in parallel with each other and having terminals formed at one end thereof; and one of the insulating substrates. A plurality of strip-shaped data wirings, which are formed on the surface with insulation from the gate wiring and are spaced apart from each other in a direction perpendicular to the gate wiring and have terminals formed at one end thereof, A picture element electrode provided for each of a plurality of rectangular picture element areas formed by intersecting the data wiring, and a picture element electrode provided for each picture element area to individually connect the picture element electrode with the gate and the data wiring The switching element, on one surface of the insulating substrate, along the periphery of the insulating substrate so as to surround all the gate wiring and the data wiring,
A plurality of short-circuit wirings formed in a ring shape at intervals from each other, and at least one of a gate wiring and a data wiring is sequentially connected at predetermined intervals through respective terminals; And an insulating film formed over the wiring. 2. The plurality of short-circuit wirings, wherein a plurality of gate short-circuit wirings are sequentially connected at predetermined intervals, and a plurality of data wirings are sequentially connected at predetermined intervals. 2. The active matrix substrate according to claim 1, further comprising: 3. A conductor layer provided for each picture element region, wherein a picture element electrode is formed on a gate wiring different from a gate wiring connected by a switching element via an insulator, and a conductor layer connected to the picture element electrode is formed. The active matrix substrate according to claim 1, wherein the active matrix substrate includes: