JPS63287080A - Manufacture of semiconductor laser - Google Patents

Abstract

PURPOSE:To enable operation of the title laser at a high oscillation efficincy, a low threshold value current and high output, by utilizing the surface azimuth dependence of a liquid phase epitaxial growth (LPE) method for selectively forming a current block layer on the surface except a groove. CONSTITUTION:An n-type InP current block layer 3, a GaInAsP buffer layer 4, a p-type InP clad layer 5, a GaInAsP active layer 6 and an n-type InP protective layer 7 are formed by turns on a p-type InP substrate 1 provided with a groove by an LPE method. Thereby, the layer 3 does not grow in the inside of the groove due to the surface azimuth dependence of the LPE method. The layer 4 has only a little surface azimuth dependency so as to grow in the inside of the groove and the layers after the layer 5 grow also thereon. Later, an inverse mesa type stripe is formed by etching, while n-type and p-type InP current stricture layers 10, 11 are made to grow by the LPE method. When this laser operated, an interface of the layers 3, 4 and the layers 10, 11 becomes an inverse bias, the current does not flow in the part of a grating to be an outer waveguide path. Accordingly, an operation of a good oscillation efficiency, a low threshold value current and a high output can be per-formed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method of manufacturing a semiconductor laser that performs basic longitudinal wave oscillation.

(Conventional technology) Conventionally, as a semiconductor laser capable of longitudinal single mode oscillation,
DBR (pistributad Bragg R)
effrector) type semiconductor lasers have been proposed. Figure 4 is a reference: Proceedings of the 46th Academic Conference of the Japan Society of Applied Physics, 1985, 206 pages, 2P-N-9, 2P-N
-10 The conventional implantable fiunde -I disclosed in
nlegratad Guide structure DBR (BH-L
FIG. 5A is a structural diagram of a semiconductor laser (G-DBR), and FIGS. 5A to 5D are process diagrams of its manufacturing process.

First, on the hp-InP substrate 12, a p-1nP lower two-rad layer 13, a GaInAsP active layer 14, and an n-InP
The protective layer 15 is grown by liquid phase epitaxial growth ('L P E
) in law.

They are formed sequentially (see FIG. 5(a)). Next, n-In
Unnecessary portions of the P protective layer 15 and the GaInAsP active layer 14 are removed by etching to expose a portion of the surface of the p-InP lower cladding layer 13, and this portion is etched using a normal holographic phosphorography technique. A companion grating 1'3a (also referred to as corrugation) having pits and depth is formed (see FIG. 5(b)). The portion with the grating 13a functions as an external waveguide region 13b.

Next, by the second LPE method') n-GaInAsP
Outer waveguide layer 16. An n-InP upper cladding layer 17 is sequentially formed over the entire surface (see FIG. 5(C)). Next, in the ninth stage of transverse mode control and current confinement, an inverted mesa-shaped stripe 18 is formed in the 9 (011) direction using phosphorography technology and chemical etching in the same way as in the manufacturing method of ordinary buried medium conductor lasers. (See Figure 5(d)). Active layer 14
The width W is set to an appropriate width for stable transverse mode oscillation, and according to the above-mentioned document, it is 2 to 3 μm. Next, the third
In the second LPE process, the inverted mesa stripe 18 was formed using n-InP.
First current confinement layer 19 and p-InP second current confinement layer 20
(See Figure 4).

Next, the n-InP upper cladding layer 17 and the p-InP second
sio! on the surface of the current confinement layer 20. An active region 13c with a GaInAsP active layer 14 is formed.
An electrode window is opened in the upper part of the n-InP upper cladding layer 17 (see FIG. 4). Although not shown in FIG. 4, the n-InP upper cladding layer 17 including the insulating film 21
A negative electrode is formed on the entire side, and a positive electrode is formed on the p-InP substrate 12 side to obtain a semiconductor laser.

Next, the operation will be explained. When a proper bias is applied to both electrodes (not shown), a current flows from the p-InP substrate 12 side to the negative electrode of the window-type electrode above the n-InP upper cladding layer 17. Since this negative electrode is a window-type electrode located above the active region 13c, no current flows through the external waveguide region 13b provided with the grating 13a. Mayu, in the buried layer part, the n-InP first current confinement layer 19 and the p-In
Since the interface of the P second current narrowing layer 2° is reverse biased, no current flows.

In the active region 13c, a current flows through the active layer 14 due to the forward bias, and light is generated. This light is guided to the external waveguide region 13b, Bragg-reflected by the grating 13m,
Oscillates in a single vertical mode. In this case, the outer waveguide region 1
The oscillation efficiency will be better if no current is allowed to flow through 3b so as to reduce optical loss.

(Problems to be Solved by the Invention) However, even with the manufacturing method described above, when the current is not allowed to flow in order to reduce optical loss in the external waveguide region 13b, the insulating film 21 such as Sin is used. This is done by forming an electrode in a window shape above the active region 13c.
In this case, since the current spreads in the n-InP upper cladding layer 17, a small current inevitably flows into the external waveguide region 13b.
The loss increases due to the current flow, and the oscillation efficiency deteriorates, making it impossible to obtain a low threshold current and high output, making it impossible to obtain a technically satisfactory result.9.

The present invention eliminates the problem of reduced oscillation efficiency caused by large optical loss in the external waveguide region as described above, and provides a semiconductor laser capable of operating with high oscillation efficiency, low threshold current, and high output. The purpose is to provide a manufacturing method.

(Means for Solving the Problems) A method for manufacturing a semiconductor laser according to the present invention includes a method for manufacturing a BH-BIG semiconductor laser in which a grating is formed on a portion of a lower cladding layer.
- In a method of manufacturing a DBR type semiconductor laser, (100
) with a (111)A side surface [
A plurality of long grooves are formed in the (011) direction, a current blocking layer is selectively formed on the surface other than the grooves using LPE, and a buffer layer is further formed on the entire surface using LPE. .

(effect) A method of manufacturing a semiconductor laser according to the present invention is as follows.

A current blocking layer is formed on the surface other than the groove by utilizing the plane orientation dependence of the growth rate of LPE, and a reverse bias layer is created with the current blocking layer and the buffer layer above it, and the external conduction of the grating on this layer is Avoid passing current into the wave region.

(Example) Hereinafter, an example of the present invention will be described in detail based on the drawings. 1 to 3 are process diagrams showing one embodiment of the present invention. First, p-InP with (100) surface
An etching mask, for example SiO!, is placed on the substrate l. A film 2 is formed, and a large number of long etching windows 2a are opened in the (011) direction in a row in the (011) direction (see FIG. 1(a)).
)reference). The thickness of the film 2 is approximately 0.2 μm, and the dimensions of the etching window 2a are (dimension Wa in the 0111 direction).
is 1.5 to 3μm, and the dimension in the (OIT) direction is approximately 5μm.
m, and the distance Wc between the etching windows 2a is 0.5
~1.5 μm The total array width Wd of each etching window 2a in the (011) direction is set to 150 to 2004 m. Next, a groove 1a is formed by etching the p-InP substrate 1' through the etching window 2a using a bromine-methanol solution, and then the KStO and film 2 are removed (see FIG. 1(b)). . Figure 1 (0) is the A-A' cross section of No. 111N (b), that is, [
FIG. 1(d) shows the state of the cross section along the [011] direction.
shows the state of the B-8' cross section, that is, the next cross section along the [O11] direction. When the depth of the valley groove 1a as shown in FIGS. 1(e) and 1(d) is set to about 0.2 μm, a (111)A surface appears on the side surface of the groove la, and the bottom surface of the groove 1a becomes a curved surface (a surface with properties similar to the (111) A surface, although there is no surface orientation).

Next, the groove 1a'ff is set on the p-InP substrate l.
In the second LPE method, the n-InP current blocking layer 3 and the p-G
aInAsP buffer layer 4. The p-InP lower cladding layer 5, the GaInAsP active layer 6, and the n-InP protective layer 7 are grown in sequence (see FIG. 2(a) and the same figure (cut)). However, FIG. 1(c), and FIG. 2(b) is a cross-sectional view similar to FIG. 1(d).In this growth, the n-InP current current block 2 layer 31a is formed into an etching window 2a. If the dimensions are the same, the growth temperature is 600℃.
It does not grow inside the groove 1a at all. This is LPE
Due to the unique property of InP, the (111) A side is (10
0) It takes advantage of the fact that it is significantly difficult to grow compared to the surface. In addition, some growth may occur on the (100) plane between the 2 layers 3 grooves 1a of the %n-(np current crystals, but this does not pose a problem due to the characteristics of the laser.p-GaIn
Compared to InP, the AsP buffer layer 4 has less dependence on the plane orientation of growth (it can grow inside the (111) A-plane groove 1a in the same way as on the (100) surface, and can grow on the (100) surface. It is also possible to grow the layers after the p-InP lower cladding layer 5 on the entire surface.
Let it grow until the interface with it becomes flat.

The following steps are almost the same as those for manufacturing a conventional BH-BIG-DBR semiconductor radar. Unnecessary parts of the i*-InP protective layer 7 and GaInAaP active layer 6 are removed by etching, and this is the part where the groove 1m is located! D p- on the (011) direction side
The surface of the InP lower cladding layer 5 is exposed, and a sub-grating 5a having an appropriate pitch and depth is formed thereon using a normal holographic phosphorography technique (see FIG. 2(e)). .

Next, by a second LPE method, an n-GaInAsP external waveguide layer 8 and an n-InP upper two rad layer 9 are sequentially formed over the entire surface (see FIG. 2(d)).

Next, as shown in Fig. 3(a), the conventional BH-BIG-
In the same way as the method for manufacturing a DBR semiconductor laser, unnecessary portions are removed by etching in an inverted mesa shape to form an inverted mesa stripe M. This inverted mesa stripe M is formed in the (011) direction so as to be located above the groove l&.The "neck" part 5b of the inverted mesa may be almost the same as that of the conventional type, and in the figure, it is located below the p-InP. In the case of cladding layer 5, n
An example is shown in which the -InP current blocking layer 3 is etched until a part of it is exposed. Next, in the third LPE method, n-In
P first current confinement layer 10. p-InP second current confinement layer 11
．． The entire structure is grown, and an inverted mesa stripe M is buried (see FIG. 3(b)).

Regarding the electrodes, the same electrodes as those of the conventional BH-BIG-DBR semiconductor laser may be used, or both the positive and negative electrodes may be full-surface electrodes.

When a semiconductor laser manufactured by such a manufacturing method is operated with a normal bias applied to the entire surface electrode, the part marked with an x in FIG. does not flow. That is, n-I
The interface between the nP current current block 2 layer 3 and the GaInAsP buffer layer 4 and the n-InP first current confinement layer io and p-I
The interface with the nP second current confinement layer 11 becomes a reverse bias, and no current flows through the portion of the grating 5a on the interface between the n-InP current block layer 2 layer 3 and the GaInAsP buffer layer 4.

In the above description, a p-InP substrate was used and the following case was explained as an example. However, even if an n-InP substrate is used, a semiconductor laser can be manufactured in exactly the same manner by simply reversing the conductivity type.

(Effect of the invention) According to the manufacturing method of the present invention as described above.

In a method for manufacturing a BH-BIG-DBR type semiconductor laser, a current blocking layer is selectively formed on the surface of a semiconductor substrate other than the T-groove by utilizing the plane orientation dependence of the growth rate of the LPE method, and then Since we created a reverse bias area with the buffer layer and set it so that no current flows into the external waveguide area with the grating above it, we created a low-loss waveguide area with good oscillation efficiency, low threshold current, and high It can be expected that output operation will be possible, and that manufacturing will be possible in three LPEs, as with conventional products.

[Brief explanation of drawings]

1 to 3 are process diagrams showing a method for manufacturing a semiconductor laser according to an embodiment of the present invention, and FIG. 4 is a conventional BH-
A structural diagram of a BIG-DBR semiconductor laser, and FIG. 5 is a process diagram showing a method of manufacturing a conventional BH-BIG-DBR semiconductor laser. 1 = p-InP substrate, la"-groove, 2 - Sin, film. 2a... window for etching, 3... n-InP current current block 2 layer... P-GaInAsP buffer layer,
5”.p-InP lower cladding layer, 5a...
grating, 6... Ga In, AsP active layer, 7... n-InP protective layer, 8... external waveguide layer,
9...n-InP upper cladding layer, 10...n-I
nP first current confinement layer-1ll...p-InP second current confinement layer, M...inverted mesa type stripe. Figure 1 ￥55FIA Figure 5

Claims (1)

[Claims] A semiconductor substrate having a (100) surface and a side surface having (111)
Create multiple long grooves in the [01@1@] direction on the A side [011]
Next, a current blocking layer, a buffer layer of the opposite conductivity type to the current blocking layer, a lower cladding layer, an active layer, and a protective layer are sequentially grown by liquid phase epitaxial growth to form the current blocking layer a second step of selectively growing the layer in areas other than the grooves and flattening the entire surface on the upper part of the lower cladding layer, and then selectively etching a part of the protective layer and the active layer. a third step of forming a grading on the removed and exposed lower cladding layer; and a fourth step of sequentially growing an outer waveguide layer and an upper cladding layer by liquid phase epitaxial growth.
Next, an inverted mesa stripe is formed in the [011] direction at the top of the groove, and a first current confinement layer and a second current confinement layer are sequentially grown by liquid phase epitaxial growth to fill the inverted mesa stripe. A method for manufacturing a semiconductor laser, comprising a fifth step.