JPS59125686A - Semiconductor laser - Google Patents
Semiconductor laserInfo
- Publication number
- JPS59125686A JPS59125686A JP66283A JP66283A JPS59125686A JP S59125686 A JPS59125686 A JP S59125686A JP 66283 A JP66283 A JP 66283A JP 66283 A JP66283 A JP 66283A JP S59125686 A JPS59125686 A JP S59125686A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- active layer
- current
- crystal
- type inp
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
- H01S5/227—Buried mesa structure ; Striped active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
- H01S5/227—Buried mesa structure ; Striped active layer
- H01S5/2275—Buried mesa structure ; Striped active layer mesa created by etching
- H01S5/2277—Buried mesa structure ; Striped active layer mesa created by etching double channel planar buried heterostructure [DCPBH] laser
Landscapes
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Semiconductor Lasers (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、光通信等に用いる半導体レーザに関し、特に
活性層への電流の閉じ込めを改善して、高出力動作を可
能にした半導体レーザに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor laser used for optical communication and the like, and more particularly to a semiconductor laser in which current confinement in an active layer is improved and high output operation is possible.
帯状の活性層を、それよりも屈折率が小さく禁制帯幅の
大きな半導体層で囲んだ埋め込みへテロ構造半導体レー
ザ(以下BHLDと略す)は、低い発振しきい値、安定
な発振横モード等のために、光通信や光情報処理用の光
源として実用化されようとしている。このBHLDにお
いて良好な特性を実現するためには、活性層へ電流を効
果的に集中して流す必要があり、各種の電流ブロック構
造が考案されている。その−例どじで第1図に、本願の
発明者らが考案した二重チャンネル型プレーナBHLD
(以下DC−PBHLDと略す)の断面図を示す。これ
は平担なI n P基板1上にn−4nPバッファ層2
.InGaAsP活性層3、p−InE!クラッド層4
を成長させた二11ヘテロ構造(DH)基板に、2本の
平行な溝10.11を形成し、それによって帯状活性層
20を形成し、その後、再び結晶成長を行ない、p−I
nP電流閉じ込め層5、n−InP電流閉じ込め層6、
p−InP埋め込み層7、p−InGaA、sPコンタ
クト層8′fc順次形成し、p側およびn側の電極30
.31を形成したものである。このDC−PBHLDに
オイテは、2本の溝10.11 (7)外側に+ p−
n p n0層構造を持つ電流ブロック構造が形成
されている。この構造中にはもとのDHウェハーのIn
GaA、sPi性層3が電流阻止層21゜22として残
されておシ、これが電流集中に有効に働くことが確かめ
られている。すなわち、 DC−PBHLDではp−n
−p−nのサイリスク構造を構成する2種のトランジス
タのうち、利得の高いn−p−n)ランリスクのp−I
nPベースとn−InPエミッタの間に、それらよシも
禁制帯幅の小さいInGaAsP電流阻止層が挾まれて
お9、これによってこのトランジスタのキャリア転送効
率が大幅に低下し、しだがってとのn−p−n)ランリ
スクの利得が下がる。その結果、p−n−p−nサイリ
スク構造はターン・オンしにくくな、シ、電流が有効に
活性領域へ集中する。一般に、半導体レーザの活性層の
厚さは、低しきい値、低垂直放射角等を実現するために
かなシ薄く形成される。例えば、従来のDC−PBHL
Dでは01μm程度にとられている。従来のDC−PB
HLDでは電流ブロック構造中に活性層と同じ組成、同
じ厚さの電流阻止層が形成されるために、電流阻止層の
厚さは有効な電流閉じ込めを実現するためには不十分で
、そのため高注入励起レベルでこのp−n−p−11ザ
イリスタがターン・オンしてし甘うことが多く、高出力
動作がやや困難であった。A buried heterostructure semiconductor laser (hereinafter abbreviated as BHLD), in which a band-shaped active layer is surrounded by a semiconductor layer with a smaller refractive index and a larger forbidden band width, has features such as a low oscillation threshold and stable oscillation transverse mode. Therefore, it is being put into practical use as a light source for optical communications and optical information processing. In order to achieve good characteristics in this BHLD, it is necessary to effectively concentrate and flow current to the active layer, and various current blocking structures have been devised. As an example, FIG. 1 shows a dual channel planar BHLD devised by the inventors of the present application.
(hereinafter abbreviated as DC-PBHLD) is shown. This is an n-4nP buffer layer 2 on a flat InP substrate 1.
.. InGaAsP active layer 3, p-InE! Cladding layer 4
Two parallel grooves 10 and 11 are formed in the 211 heterostructure (DH) substrate on which the p-I
nP current confinement layer 5, n-InP current confinement layer 6,
A p-InP buried layer 7, p-InGaA, and sP contact layer 8'fc are sequentially formed, and p-side and n-side electrodes 30 are formed.
.. 31 was formed. This DC-PBHLD has two grooves 10.11 (7) + p- on the outside.
A current block structure having an n p n0 layer structure is formed. In this structure, there is In of the original DH wafer.
The GaA and sPi layers 3 are left as current blocking layers 21 and 22, and it has been confirmed that this works effectively for current concentration. That is, in DC-PBHLD, p-n
- Of the two types of transistors constituting the p-n run risk structure, the p-I with the higher gain n-p-n) run risk
An InGaAsP current blocking layer with a smaller bandgap is sandwiched between the nP base and the n-InP emitter,9 which significantly reduces the carrier transfer efficiency of this transistor and therefore n-p-n) run risk payoff decreases. As a result, the pnpn cell structure is difficult to turn on, and current is effectively concentrated in the active region. Generally, the active layer of a semiconductor laser is formed very thin in order to achieve a low threshold value, a low vertical radiation angle, and the like. For example, conventional DC-PBHL
In D, it is set to about 01 μm. Conventional DC-PB
In HLD, a current blocking layer with the same composition and same thickness as the active layer is formed in the current blocking structure, so the thickness of the current blocking layer is insufficient to realize effective current confinement, and therefore high This p-n-p-11 zyristor often turns on slowly at the injection excitation level, making high output operation somewhat difficult.
本発明の目的は、高注入励起レベルでもMs流閉ザの構
成は、帯状の活性層と、との活性層よりIi(折率が小
さく禁制帯幅が大きくこの活性層の少々くとも長手方向
の両側及び上下面を囲む半導体層と、前記活性層の両側
を囲む前記半導体層の少なくとも前記長手方向外側に接
して形成しである電流ブロック構造の多層半導体層とを
有し、前記電流ブロック構造多層半導体rv=は禁制帯
幅が前記活性層とほぼ等しくその活性層よシ厚い電流阻
止層を含むことを特徴とする。The object of the present invention is that even at a high injection excitation level, the structure of the Ms flow closure is such that the active layer has a band-like active layer, and has a smaller refractive index and a larger forbidden band width than the active layer Ii (lower refractive index and larger forbidden band width). and a multilayer semiconductor layer having a current block structure formed in contact with at least the outer side in the longitudinal direction of the semiconductor layer surrounding both sides of the active layer, the current block structure The multilayer semiconductor rv= is characterized in that it includes a current blocking layer whose forbidden band width is approximately equal to that of the active layer and which is thicker than the active layer.
以下図面を参照して本発明の詳細な説明する。The present invention will be described in detail below with reference to the drawings.
第2図は本発明の望ましい実施例の断面図、第3図(a
) 、 (b)及び(C’)はその実施例の製作工程に
おける3つの段階を示す断面図である。この実施例では
電流阻止層21.22は、帯状活性層20 よりも厚く
なっており、高注入励起レベルにおいてもp−n−p−
nサイリスタはターン・オンせず、有効な電流閉じ込め
が行なわれることが確かめられ、従来のDC−PBHL
Dよシも高出力動作が可能であった。この実施例の製造
方法を第3図(a) 、 (b)及び(C)をもとに説
明する。FIG. 2 is a sectional view of a preferred embodiment of the present invention; FIG.
), (b) and (C') are cross-sectional views showing three stages in the manufacturing process of the embodiment. In this embodiment, the current blocking layers 21, 22 are thicker than the band-shaped active layer 20, and even at high injection excitation levels, the current blocking layers 21, 22 are
It was confirmed that the n-thyristor does not turn on and effective current confinement occurs, and the conventional DC-PBHL
D type was also capable of high output operation. The manufacturing method of this embodiment will be explained based on FIGS. 3(a), (b) and (C).
まず、(001)InP基板1に、フォトリングラフィ
法と塩酸系のエッチャントによる化学エツチング法とに
より、上部の幅約5μm1高さ1μmで、<110>方
位のメサストライプ4oを形成する。次いで、液相成長
法によシ、この基板1上にn−InPバッファ層2、I
nGaAsP活性層3、p−InPクラッド層4を順次
成長させ、二重へテロ構造結晶41を作る。n−InP
バッファ層2およびp−InPクラッド層4の成長は過
飽和度を約8゜Cとったスーパークーリング法で、活性
層3の成長は溶液中にInPの結晶が溶けきれずに浮ん
でいるいわゆる二相溶液法で行なった。層2,3.4の
厚さは、メサストライプ40以外の部分でそれぞれ2μ
m、03μm、1μmとなるようにした。このとき、メ
サストライプ40の上面では、層2,3゜4の厚さは、
それぞれ、1.5μm、0.1μm、0.7μn]とな
った。すなわち、過飽和度が比較的小さい二相溶液法で
成長する場合、メサストライプの上の成長速度はそれ以
外の平担部での成長速度よりも著しく小さくなる。本実
施例では、この性質を利用して、厚さの異なるInGa
AsP層金−回の結晶成長過程で作製した。このとき、
帯状活性層20となる部分はメサストライプ40の上に
形成されるので、電流阻止層21.22となる部分よシ
も基板1から遠い位置に形成されている。First, a <110> oriented mesa stripe 4o is formed on the (001) InP substrate 1 by photolithography and chemical etching using a hydrochloric acid etchant, with an upper width of about 5 μm and a height of 1 μm. Next, an n-InP buffer layer 2 and an I
An nGaAsP active layer 3 and a p-InP cladding layer 4 are sequentially grown to form a double heterostructure crystal 41. n-InP
The buffer layer 2 and the p-InP cladding layer 4 are grown using a supercooling method with a supersaturation degree of about 8°C, and the active layer 3 is grown using a so-called two-phase method in which InP crystals are not completely dissolved but are floating in the solution. The solution method was used. The thickness of layers 2 and 3.4 is 2μ each except for the mesa stripe 40.
m, 03 μm, and 1 μm. At this time, on the upper surface of the mesa stripe 40, the thickness of the layers 2 and 3°4 is
1.5 μm, 0.1 μm, and 0.7 μm, respectively. That is, when growing by a two-phase solution method with a relatively low degree of supersaturation, the growth rate on the mesa stripe is significantly lower than the growth rate on the other flat areas. In this example, by utilizing this property, InGa with different thicknesses
The AsP layer was fabricated using a gold crystal growth process. At this time,
Since the portion that will become the band-shaped active layer 20 is formed on the mesa stripe 40, the portion that will become the current blocking layers 21 and 22 is also formed at a position far from the substrate 1.
次に、やはり、フォトリングラフィ法と、ブロム・メタ
ノールエンチャントを用いた化学エノチフグ法とを用い
て、前述の二重へテロ構造結晶41に2本の平行な溝1
0,11e形成する。このとき、第3図(C)に点線で
示したエツチング前の結晶41表面の形状と、エンチン
グ後の溝10.11 との位置関係を定める。す々わち
、2本の溝10.11に挾まれた帯状活性層20を含む
活性層メサストライプ23は、もとのメサストライプ4
0部分のほぼ中央に来るように、しかも2本の溝10.
11は、二重へテロ構造結晶41のメサストライプ40
以外の部分にまで届くようにする。この後、再び結晶成
長炉に入れ、p−InPおよびn−InP の電流閉
じ込め層5,6、p−InP埋め込み層7、p−工nG
aA、sPコンタクト層8を順次に二相溶液法で成長す
る。このとき、各層の成長時間を適切に設定することに
より、前二者5,6は活性層メサストライプ23の上面
には成長せず、後二者7.8は結晶表面全面にわ直って
成長させることが可能である。層5,6,7.8の厚さ
は、平担部でそれぞれ0.5μmj0.5μm、1.5
μm、0.7μmとした。これに続いて成長表面にp側
電極30、基板1を研磨で薄くしだ後n1’lll電極
31金蒸着して合金化し、へき開、スクライビング等で
ペレットに切り出して第2図に断面を示したような素子
の製作が完了する。第4図は、本発明の実施例のパルス
ち、流−光出力特性と、従来のDC−PBHLDのパル
ス電流−光出力特性の一例を示す。本発明の実施例の光
出力は曲線50で示されるように、片面からの光出力1
50mW以上が得られているのに対して、第1図の従来
素子の特性は曲線51で示されるように、約100mw
で出力飽和が激しくなり、これ以上の高出力動作は不可
能である。これは、本発明の実施例では、電流ブロック
構造中の電流阻止層21.22の厚さが、従来のものよ
りも厚いだめに、このp−n−p−nサイリスク構造が
より高い励起レベルまでターン・オンすることがなくな
ったために、高注入励起状態でも帯状活性層20以外へ
流れるもれ電流が大幅に減少したためである。本発明で
は、メサストライプ基板上に二重へテロ構造を形成する
ことにより、帯状活性層20と電流阻止層21.22を
同時に、しかも前者を良好な横モード安定性、低しきい
値が得られるように十分に薄クシ、かつ後者を厚く形成
することを可能にしているので、従来のBHLDとほぼ
同程度の工数で高出力特性が大幅に改善されたBHLD
が実現できた。Next, the two parallel grooves 1 are formed in the double heterostructure crystal 41 using the photophosphorography method and the chemical enotyphragm method using bromine-methanol enchantment.
0,11e is formed. At this time, the positional relationship between the shape of the surface of the crystal 41 before etching shown by the dotted line in FIG. 3(C) and the groove 10.11 after etching is determined. That is, the active layer mesa stripe 23 including the band-shaped active layer 20 sandwiched between the two grooves 10 and 11 is the same as the original mesa stripe 4.
10. so that it is almost in the center of the 0 part, and two grooves 10.
11 is a mesa stripe 40 of a double heterostructure crystal 41
Make it possible to reach other parts. After that, it is placed in the crystal growth furnace again, and the current confinement layers 5 and 6 of p-InP and n-InP, the p-InP buried layer 7, and the p-nG
The aA and sP contact layers 8 are sequentially grown using a two-phase solution method. At this time, by appropriately setting the growth time of each layer, the first two layers 5 and 6 do not grow on the upper surface of the active layer mesa stripe 23, and the latter two layers 7 and 8 grow over the entire crystal surface. It is possible to do so. The thickness of layers 5, 6, and 7.8 is 0.5 μm, 1.5 μm, and 0.5 μm, respectively, in the flat part.
μm, 0.7 μm. Subsequently, the p-side electrode 30 was placed on the growth surface, and the substrate 1 was thinned by polishing, then gold was deposited on the n1'lll electrode 31 to form an alloy, and the pellet was cut out by cleaving, scribing, etc., and the cross section is shown in Figure 2. The fabrication of such an element is completed. FIG. 4 shows an example of the pulse current-light output characteristics of the embodiment of the present invention and the pulse current-light output characteristics of a conventional DC-PBHLD. The light output of an embodiment of the invention is shown by curve 50, as shown by curve 50, where the light output from one side is 1
While more than 50 mW is obtained, the characteristics of the conventional element in FIG. 1 are approximately 100 mW, as shown by curve 51.
At this point, output saturation becomes severe and higher output operation is impossible. This is because, in the embodiment of the present invention, the thickness of the current blocking layer 21,22 in the current blocking structure is thicker than that of the conventional one, so that this p-n-p-n silicon risk structure has a higher excitation level. This is because the leakage current flowing to areas other than the band-shaped active layer 20 is significantly reduced even in a highly implanted excited state. In the present invention, by forming a double heterostructure on a mesa stripe substrate, the band-shaped active layer 20 and the current blocking layer 21, 22 can be formed simultaneously, and the former can have good transverse mode stability and a low threshold value. This makes it possible to form a thin enough comb to allow the comb to be thicker, and a thicker comb to achieve a BHLD with significantly improved high-output characteristics, with approximately the same number of steps as a conventional BHLD.
was realized.
以上詳述したように、本発明によれば、高注入励起レベ
ルでも15i流閉じ込め機能が有効に働き、高出力動作
が可能な半導体レーザが提供できる。As detailed above, according to the present invention, it is possible to provide a semiconductor laser in which the 15i flow confinement function works effectively even at a high injection excitation level and is capable of high output operation.
【図面の簡単な説明】
第1図は従来の埋め込み構造半導体レーザの断面図、第
2図は本発明の望ましい実施例の断面図、第3図(a)
、 (b)及び(C)はこの実施例の製造工程の3つ
の段階における結晶をそれぞれ示す断面図、第4図はパ
ルス電流−光出力特性図である。
1・・・・・・基板、2・・・・・・バッファ層、3・
・・・・・活性層、4・・・・・クラッド層、5,6・
・・・・・電流閉じ込め層、7・・・・・・埋め込み層
、8・・・パ・コンタクト層、10.11・・・・・・
清、20・・・・・帯状活性層、21.22・・・・電
流阻止層、23・・・・・活性層メサストライプ、30
.31・・・・電極、40・・・メザストライプ、41
1・・・・ 二重へテロ構造結晶。
]、・ゾ、″′[Brief Description of the Drawings] Fig. 1 is a sectional view of a conventional buried structure semiconductor laser, Fig. 2 is a sectional view of a preferred embodiment of the present invention, and Fig. 3(a).
, (b) and (C) are cross-sectional views showing the crystal at three stages of the manufacturing process of this example, and FIG. 4 is a pulse current-light output characteristic diagram. 1...Substrate, 2...Buffer layer, 3.
...Active layer, 4...Clad layer, 5, 6.
...Current confinement layer, 7...Buried layer, 8...Par contact layer, 10.11...
Clear, 20... Band-shaped active layer, 21.22... Current blocking layer, 23... Active layer mesa stripe, 30
.. 31... Electrode, 40... Mezza stripe, 41
1... Double heterostructure crystal. ],・zo,″′
Claims (1)
制帯幅が大きくこの活性層の少なくとも長手方向の両側
及び上下面を囲む半導体層と、前記活性層の両側を囲む
前記半導体層の少なくとも前記長手方向外側に接して形
成しである電流ブロック構造の多層半導体層とを有し、
前記電流ブロック構造多層半導体層は禁制布幅が前記活
性層とほぼ等しくその活性層より厚い電流阻止層を含む
ことを特徴とする半導体レーザ。 (2)前項記載の半導体レーザにおいて、前記各半導体
層が形成しである基板の底面と前記活性層との距離はそ
の底面と前記電流阻止層との距離よシ大きいことを特徴
とする半導体レーザ。[Scope of Claims] G) A band-shaped active layer, a semiconductor layer having a smaller refractive index and a larger forbidden band width than the active layer, surrounding at least both longitudinal sides and upper and lower surfaces of the active layer; a multilayer semiconductor layer having a current block structure formed in contact with at least the longitudinal outside of the semiconductor layer surrounding both sides;
A semiconductor laser characterized in that the current blocking structure multilayer semiconductor layer includes a current blocking layer having a forbidden width approximately equal to that of the active layer and thicker than the active layer. (2) In the semiconductor laser described in the preceding item, the distance between the bottom surface of the substrate on which each of the semiconductor layers is formed and the active layer is greater than the distance between the bottom surface and the current blocking layer. .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP66283A JPS59125686A (en) | 1983-01-06 | 1983-01-06 | Semiconductor laser |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP66283A JPS59125686A (en) | 1983-01-06 | 1983-01-06 | Semiconductor laser |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59125686A true JPS59125686A (en) | 1984-07-20 |
JPH0449791B2 JPH0449791B2 (en) | 1992-08-12 |
Family
ID=11479932
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP66283A Granted JPS59125686A (en) | 1983-01-06 | 1983-01-06 | Semiconductor laser |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59125686A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62230078A (en) * | 1986-03-31 | 1987-10-08 | Nec Corp | Buried semiconductor laser |
JPS63215090A (en) * | 1987-03-04 | 1988-09-07 | Matsushita Electric Ind Co Ltd | Semiconductor laser |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5712580A (en) * | 1980-06-26 | 1982-01-22 | Nec Corp | Manufacture of semiconductor light-emitting device |
-
1983
- 1983-01-06 JP JP66283A patent/JPS59125686A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5712580A (en) * | 1980-06-26 | 1982-01-22 | Nec Corp | Manufacture of semiconductor light-emitting device |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62230078A (en) * | 1986-03-31 | 1987-10-08 | Nec Corp | Buried semiconductor laser |
JPS63215090A (en) * | 1987-03-04 | 1988-09-07 | Matsushita Electric Ind Co Ltd | Semiconductor laser |
Also Published As
Publication number | Publication date |
---|---|
JPH0449791B2 (en) | 1992-08-12 |
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