JPS63287054A - One-transistor type dynamic memory cell - Google Patents

Abstract

PURPOSE:To reduce the area of a memory cell, by providing two capacitors up and down in parallel in the insides of grooves, which are formed in the surface of a semiconductor substrate, and introducing impurities from the same layer as a poly Si layer, which is to become a memory device furthermore. CONSTITUTION:Grooves 11a and 11b are formed in an Si substrate 1. Then a first memory capacitor is formed with p<+> regions 21a and 21b and poly Si electrodes 22a and 22b so as to hold capacitor insulating films 4a and 4b, which are formed on the bottom surfaces and the side surfaces of the grooves 11a and 11b. A second memory capacitor is formed with the electrodes 22a and 22b and a poly Si electrode 5 so as to hold capacitor insulating films 24a and 24b, which are formed on the surfaces of the electrodes 22a and 22b. Poly Si layers 100a and 100b are formed at the same time when the electrodes 22a and 22b are formed. Impurities are implanted into the layers 100a and 100b. Thereafter, the source and the drain of a writing transistor are formed by the diffusion of the impurities from the layers 100a and 100b. Thus the two capacitors are provided in parallel. Contact holes for connecting the electrodes 22a and 22b to the substrate 1 are not required. Therefore, the occupying area of the memory cells can be reduced remarkably.

Description

DETAILED DESCRIPTION OF THE INVENTION Conventionally, the capacity of a memory capacitor has been secured by microfabrication techniques and thinning of insulating films and the like. but,
There are limits to microfabrication and film thinning, and various memory cells have been proposed in order to secure more memory capacitor capacity within a limited cell area. Figure 6 is an example of IEE Transactions Electronic Devices, Volume 1 CD-31, 146-F53.
Page (Engineering IClCl, Trams,] [flsotr
o21 Deviaas vol, KD-31, P
P) 46-53) 1 corrugated capacitor cell 1 (%A' Oorrugatel 0ap
aoitor 0ell (000)' ) as H,
This is a trench-type memory cell shown by Sunami (H, Sunami) et al., and FIG. 3 (&) Ifi is a plan view, and FIG.

In the figure, (1) is a P-type silicon substrate, C2) is a field oxide film for isolation between elements, C3) is a channel stop P middle region for isolation between elements, (4) is a capacitor insulating film, and (5) is a (6) is a word line to which a word line signal is applied and forms the gate electrode of an access transistor; (7) is an N+ region connected to a bit line; (8) is the contact hole,
(9) is a metal wiring constituting a bit line, and aG is an N-type inversion layer or a grooved N+ region which constitutes a storage terminal of a memory cell gate and is of the opposite conductivity type to the silicon substrate (1). . This memory cell M is intended to substantially increase the area by forming a trench in a semiconductor substrate and using the side surfaces of the trench as a memory capacity.

Since the conventional improved dynamic memory cell is constructed as described above, the distance between the grooved regions (X1a) and (1111) must be reduced in order to achieve higher integration. Therefore, the opposing memory terminal (log
) and (xob) become narrower, and the depletion layers formed on the sides are connected, causing leakage between adjacent memory cells M, resulting in the destruction of stored information.
The drawback is that it cannot necessarily support high integration.

Further, as another example in which the memory capacity is increased using grooves, the one shown in FIG. 6 can be considered.

In this sixth decoy, (1) to 4), (a) to 9) are the same or equivalent parts to the memory cell shown in FIG. 3, I is a grooved area, and (2) is a A high-concentration P group region that becomes a cell plate electrode, of course a polysilicon electrode that forms a memory terminal, and @ is a contact hole.

In such a dynamic memory cell, the charge storage electrode is read and written to the N+ region 7 of the write transistor.
), it is necessary to open a contact hole @ for connection to the terminal, which poses an obstacle to higher density.

Furthermore, since photolithography is performed on an extremely thin capacitor insulating film (4), impurity contamination and damage to the capacitor insulating film (4) due to the use of photoresist are unavoidable, resulting in electrical damage to the capacitor insulating film (4). This has caused the inconvenience of significantly deteriorating reliability.

[Problem that the invention seeks to solve]

Because the conventional dynamic memory cell is configured as described above, it cannot necessarily support high integration, and in the conventional example shown in FIG. 5, the memory terminal is inside the semiconductor substrate.
Carriers generated by alpha rays, etc. flow into the memory terminal,
There were problems such as the occurrence of soft errors in which stored information was destroyed.

In addition, in the case of a memory cell that uses polysilicon as a charge accumulation node, a contact hole must be formed for connection to the substrate, which increases the memory cell area and degrades the electrical reliability of the capacitor insulating film. There was a point.

The invention was made to solve the above-mentioned problems, and it is possible to prevent deterioration of the capacitor insulating film, secure sufficient memory capacity in a reduced memory cell, and An object of the present invention is to obtain a one-transistor type dynamic memory cell suitable for high integration and capable of avoiding an increase in leakage between adjacent memory cells.

[Means for solving problems]

The l-transistor type dynamic memory cell according to the present invention has a first polysilicon electrode formed of a silicon substrate and a first polysilicon electrode inside a groove formed on a surface of a semiconductor substrate.
A second capacitor formed by a first polysilicon electrode and a second polysilicon electrode is stacked on top of the second capacitor, and these two capacitors are connected in parallel to a memory terminal. The polysilicon layer of the first electrode and the polysilicon layer forming the source and drain electrodes of the read/write transistor are made of the same layer, and the structure is such that there is no contact hole connecting the storage terminal and the read/write transistor. .

[Effect]

In this invention, a first capacitance between the first polysilicon electrode and the silicon substrate is formed in the lower layer of the first polysilicon electrode within a groove formed on the surface of the semiconductor substrate, and a first capacitance is formed in the upper layer of the first polysilicon electrode. forms a second capacitor with the second polysilicon electrode, and by using the two capacitors in parallel, the memory capacity can be dramatically increased. The structure is resistant to leaks and soft errors between matching memory cells. Also, by making the first polysilicon electrode, which is the memory terminal, and the polysilicon, which forms the source and drain electrodes of the read/write transistor, in the same layer. By eliminating the contact hole connecting the storage terminal and the read/write transistor, the memory cell area can be significantly reduced, and deterioration of the capacitor insulating film can be prevented.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
Figure (-) is a plan view of an l-transistor type dynamic memory cell according to an embodiment of the present invention, and Figure 1 ('b) is a cross-sectional view at person-B. In Figure 1, a5
is a grooved region, @ is a high concentration P-type region which becomes the silicon substrate side electrode of the first capacitor Mol, - is the first region which becomes a memory terminal
Polysilicon electrode, which forms the dielectric of the second capacitor MO2 capacitor insulation! , (s) is the second capacity M
Cell plate which is the second polysilicon electrode which becomes the counter electrode of O2! The pole, (? &) () b) is the access transistor A! (6-) is the gate electrode of the access transistor AT, (loo &) (lo
ob) is the same polysilicon layer as the polysilicon electrode -, and is a polysilicon layer forming source/drain (2) (tube) electrodes. M is one memory cell consisting of one transistor and one capacitor, and a large number of 0 cells are arranged in a MYRIX shape depending on the storage capacity (number of bits) of the storage device.
The contact hole (8) is provided in common between two adjacent memory cells M and at the boundary.

During operation of the semiconductor memory device, the substrate (1) is held at a negative potential of 0 to -3 [V] by a substrate potential generation circuit (not shown), and the cell plate (5) is Oa A voo.

It is held at a constant value of a positive potential such as Too (Too minus power supply voltage).

This memory cell is formed by digging a groove I in a silicon substrate (1) and then oxidizing the bottom and side surfaces of the groove.
across the capacitor insulating film (4), the P+ region (to)
and the first polysilicon electrode port, the first memory capacity M
The first polysilicon electrode and the second The polysilicon electrode (5) of the second memory capacitor MO
2 and stacked on top of the first memory capacity fiMO1. At the same time as forming the first polysilicon electrode @ which will become the memory terminal, the polysilicon layer α0
0) is formed, then impurity ions are implanted into the polysilicon layer (100), and then the polysilicon 71 (1oo) in the area where the bottom of the gate electrode (6&) is to be formed is removed, followed by heat treatment. The source/drain regions (7) of the read and write transistors are formed by impurity diffusion from the polysilicon layer aoo>.

Therefore, the storage terminal and transistor region (7) are connected via the same layer αOQ).
The charge stored in the storage terminal is transferred to the bit line (
9).

In this way, in the memory cell according to this embodiment, which does not require forming a contact hole for connecting the first polysilicon electrode to the silicon substrate, it is possible to significantly reduce the area occupied by the memory cell. In addition, in the conventional memory cell having the contact hole shown in FIG. 4, it is necessary to open a contact hole in the capacitor insulating film (4), which significantly deteriorates the electrical reliability of the capacitor insulating film as described above. However, when using the structure of the present invention, after forming the capacitor insulating film (4), the first polysilicon electrode b (100) is deposited on the surface of the capacitor insulating film (4). , such inconveniences can be completely eliminated.

In addition, in the memory cell of this example, the silicon substrate (1)
The surface area of the capacitor is effectively increased by utilizing the side walls of the groove formed in the groove, and as is clear from the equivalent circuit of FIG. 2, silicon substrates ( Inc.), the first and second memory capacitors Mol with the second polysilicon electrode r5) as the counter electrode.
, MO2 are formed, the memory capacity increases dramatically. For example, if the thickness of the capacitor insulating film (4) on the silicon substrate (to) and the thickness of the capacitor insulating film (material) on the first polysilicon electrode (to) are the same, then from the storage terminal (to) The memory capacity as seen is approximately doubled because the capacities Mol and 102 are connected in parallel via a power supply (not shown). At this time, silicon substrate 6! The first memory capacity Mol formed between the silicon substrate surface (2
), the capacitance decreases due to the expansion of the depletion layer.
The surface concentration of the silicon substrate @ forming the is 1.0181b. Also, in this memory cell, since the semiconductor substrate surface @ which becomes the counter electrode of the first memory capacitor is of the same conductivity type as the semiconductor substrate (1), the adjacent The problem described in the conventional example that memory cells are connected by a depletion layer and leakage force occurs between memory cells does not occur at all. Therefore, the distance between adjacent memory cells can be reduced to a minimum value determined by processing limits, which has an extremely large advantage in increasing density.

Furthermore, in this embodiment, since the storage terminal is insulated from the semiconductor substrate (1), charges generated in the semiconductor substrate (1) due to alpha particles etc. flow into the storage terminal and destroy the stored information. It is also possible to almost completely solve the problem of soft errors.

Further, as shown in FIG. 3, silicon oxide is applied to the surface region so as to limit the electrical contact area between the surface region of the semiconductor substrate (1) excluding the source/drain region (LOOA) and the polysilicon electrode (1OOA). Insulating film (log)
A contact hole (8) is formed on this insulating film (101).
), it is possible to significantly reduce the junction area of the source/drain region (a) without particularly increasing the area. For this reason, the burden generated in the semiconductor substrate (1) by alpha particles, etc. flows into the source/drain region () &), destroying the stored information. , the junction capacitance of the source and drain (7&), which acts as a parasitic capacitance of the bit line voltage 9), also becomes significantly smaller, resulting in a continuous signal "-f To (O8H-T: IJ capacitance, OB is the bit line capacitance, vo (voltage written to the memory cell) becomes large, making it possible to provide a memory device that is resistant to noise and has a large operating margin.

Furthermore, the gate length of the read/write transistor is determined by the interval between the polysilicon electrodes (LOOA) and (100B) that form the source/drain electrodes (7), so the gate electrode (6) is
LOOA) and (LOOB), and the width of the gate electrode (6) can be made wider.
The wiring resistance of the gate electrode (6) can be reduced.

Furthermore, in this embodiment, the charge storage region and the source/drain region of the read/write transistor ()a), (
) Polysilicon layer (loo&) forming the electrode of b)
, (root)) are formed of the same polysilicon layer, it is possible to form an isolation region between memory cells M by embedding a thick insulating film (2) between the polysilicon patterns. . As shown in Figure 4, in conventional memory cells, the 10008 isolation method using selective oxidation has been widely used, but the generation of bird peaks due to the lateral growth of the oxide film is unavoidable, and the device There was a limit to how narrow the width of the separation area could be. In a non-example, after forming a polysilicon layer pattern b (100), an impurity doping region t is formed in the region where there is no polysilicon layer using an ion implantation method to increase the substrate concentration.
S> is formed, and further, in the region where there is no polysilicon layer,
The device isolation region is formed by burying an insulating film (2) such as an oxide film. This method of forming the device isolation region does not generate any bird peaks, so the isolation region can be formed to the minimum size determined by photolithography. It is possible to narrow the width, which is extremely effective in increasing the density of storage devices.

In the above embodiment, an N-channel type element is used for the memory cell U, but it is clear that a P-channel type element may be used and the same effects as in the above embodiment can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, the surface area of the capacitor is effectively increased by utilizing the sidewalls of the grooves dug in the silicon substrate, and silicon Two capacitors are provided in parallel with the substrate and the second polysilicon electrode as opposing electrodes,
Furthermore, impurities are introduced into the same polysilicon layer as the first polysilicon layer that will serve as the storage terminal to form the source and drain regions of the access transistor.
A one-transistor type dynamic device that can prevent deterioration of the electrical reliability of the capacitor insulating film, can form a large memory capacity in an extremely small area, and is resistant to leaks between adjacent memory cells and soft errors. This has the effect of realizing a memory cell.

[Brief explanation of the drawing]

1(a) and (b) are diagrams showing a one-transistor type dynamic memory cell according to an embodiment of the present invention, FIG. 2 is a diagram showing the circuits of the memory cell shown in FIG. 1, and FIG.
(-) (b) is a diagram showing a one-transistor type dynamic memory cell according to another embodiment of the present invention, and FIG.
&) (1)) is an enlarged view of the isolation region between elements of the present invention, and Figures 5 (,) (b) and 6 (a) and (b) are diagrams showing conventional trench-type dynamic memory cells. In the diagram, (1)...P-type silicon substrate, C2)
...Field oxide film, (3)...Channel stop P+ region fi, (4)...Capacitor insulating film on the silicon substrate surface, (5)...Self-rate charge ti%AT...
・Access transistor, (6)...word line, (7
)...N middle area, (8)...bit line hole, (9)...bit line, 0...grooving area, (foundation)
... P middle region, @... First polysilicon electrode that becomes a memory terminal, (c)... Capacitor insulating film between polysilicon, (100)... Polysilicon that becomes a source/drain diffusion source Silicon layer (YOX)... is an insulating film. In addition, the same reference numerals in the figures indicate the same or corresponding parts.

Claims (6)

[Claims] (1) In a semiconductor memory device in which one memory cell is composed of one transistor and one capacitor, the semiconductor substrate and a first groove formed opposite to the semiconductor substrate are located inside a groove formed on the surface of the semiconductor substrate. A first capacitor is formed between the first electrode and a second electrode formed on the first electrode, and a second capacitor is formed between the first electrode and a second electrode formed on the first electrode, and the memory capacity of one memory cell is equal to the first capacitor. and a second capacitor, the first electrode serving as a storage terminal is made of a polysilicon layer, and the source and drain of the transistor for reading and writing are doped with impurities from the polysilicon layer. A one-transistor type dynamic memory comprising an impurity region formed using a polysilicon layer, and wherein the bottom of the gate electrode of the transistor is defined at both ends by a polysilicon layer forming a source/drain electrode. cell. (2) The one-transistor type dynamic memory cell according to claim 1, wherein the gate electrode of the transistor has a structure in which it rides on a polysilicon layer that serves as the source and drain. (3) Claims 1 or 2, characterized in that the contact between the polysilicon layer forming the source/drain electrodes of the transistor and the wiring forming the bit line is formed on an insulating film. 1-transistor type dynamic memory cell described in . (4) The surface of the groove in the semiconductor substrate forming the first capacitor has the same conductivity type as the semiconductor substrate, and has a conductivity type opposite to that of the diffusion region of the read/write transistor. A one-transistor type dynamic memory cell according to any one of claims 1 to 3. (5) The surface concentration of the groove in the semiconductor substrate is 10^1^8
5. The one-transistor type dynamic memory cell according to claim 1, wherein the one-transistor type dynamic memory cell is at least /cm^3. (6) A thick insulating film is formed between the first electrode patterns, and an inter-memory cell isolation region is provided with a high substrate concentration under the insulating film. The one-transistor type dynamic memory cell according to any one of Item 5.