JPS63284913A - Variable gain amplifier - Google Patents

Variable gain amplifier

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Publication number
JPS63284913A
JPS63284913A JP11970387A JP11970387A JPS63284913A JP S63284913 A JPS63284913 A JP S63284913A JP 11970387 A JP11970387 A JP 11970387A JP 11970387 A JP11970387 A JP 11970387A JP S63284913 A JPS63284913 A JP S63284913A
Authority
JP
Japan
Prior art keywords
transistor
gain
differential amplifier
base
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11970387A
Other languages
Japanese (ja)
Other versions
JPH0612860B2 (en
Inventor
Koichi Matsumoto
幸一 松本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP11970387A priority Critical patent/JPH0612860B2/en
Publication of JPS63284913A publication Critical patent/JPS63284913A/en
Publication of JPH0612860B2 publication Critical patent/JPH0612860B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To prevent the DC potential of an output terminal from being changed even when a total gain is closed tight, by changing a ratio to mix the outputs of two amplifiers by a current source controllable electrically and the gain of a differential amplifier with a high gain. CONSTITUTION:A variable gain amplifier is constituted by providing a first differential amplifier consisting of transistors (Tr) 16 and 17 and resistors 13 and 14, and a second differential amplifier consisting of Trs 18 and 19. In such constitution, constant current sources 7 and 8 are controllable electrically and generate equal voltages for a control voltage. In such a case, it is assumed that the currents of the current sources 7 and 8 are I7 and I8, and the resistance values of the resistors 13-15 and 20-21 are R13-R15 and R20-R21. And when it is I7=I8 and I7=0 and I8=0, by setting the emitter currents of the Trs 16-19 at IE16-IE19 and the voltage of a power source 1 at V1 and the forward direction voltages of the bases and the emitters of the Trs 16 and 18 at VBE16 and VBE18, a result is shown in equation I if it is I7=I8not equal to 0. Therefore, equations II and III are satisfied, and it is possible to prevent the DC potential of the output terminals 22 and 23 from being changed by the current I7.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、トランジスタの差動増幅器に関し、特にAG
C(自動利得制御)増幅器に用いられる、電流や電圧に
よって利得を変えることのできる可変利得増幅器に関す
る。
[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a transistor differential amplifier, and in particular to an AG
This invention relates to a variable gain amplifier that is used in C (automatic gain control) amplifiers and whose gain can be changed depending on current and voltage.

〔従来の技術〕[Conventional technology]

従来この種の回路としては第1図に示す様な構成がよく
知られている。信号源102から入力された信号は、ト
ランジスタ106,107と定電流源103とで構成さ
れた差動増幅器で電流増幅され、トランジスタ108.
109で構成された差動型のベース接地増幅器にエミッ
タから入力される。
Conventionally, as a circuit of this type, a configuration as shown in FIG. 1 is well known. A signal input from the signal source 102 is current-amplified by a differential amplifier composed of transistors 106 and 107 and a constant current source 103, and is then amplified by a differential amplifier composed of transistors 106 and 107 and a constant current source 103.
The signal is input from the emitter to a differential type common base amplifier configured with 109.

この時、ベースバイアス電圧源105と104の電圧V
、とv18が等しければ、信号はトランジスタ108と
109に半分ずつ分けられる。V2O3を変化すること
で、負荷抵抗110を流れる電流を増減し利得を変える
。なお、101は電源である。
At this time, the voltage V of the base bias voltage sources 105 and 104
, and v18 are equal, the signal is split in half between transistors 108 and 109. By changing V2O3, the current flowing through the load resistor 110 is increased or decreased and the gain is changed. Note that 101 is a power source.

第4図は従来例の利得を上げた時の入力振幅と出力の関
係を表わした略図であり、第5図は従来例の利得を下げ
た時の入力振幅と出力の関係を表わした略図である。
Fig. 4 is a schematic diagram showing the relationship between input amplitude and output when the gain of the conventional example is increased, and Fig. 5 is a schematic diagram showing the relationship between input amplitude and output when the gain of the conventional example is decreased. be.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

前述した第1図の回路では、利得が減るにつれ、負荷と
しての抵抗110の両端に取り出せる出力信号の振幅が
小さくなることや、トランジスタ106.107の動作
点はV、o4に無関係だからV1O4を上げて回路全体
の利得を下げても最大許容入力は大きくならないという
欠点がある。又従来例の回路では信号成分だけでなくト
ランジスタ108のコレクタ直流電流もV2O3によっ
て変化するので利得はかυでなく出力端子111の直流
電位も変化してしまう欠点がある。
In the circuit shown in FIG. 1 described above, as the gain decreases, the amplitude of the output signal that can be taken out across the resistor 110 as a load decreases, and since the operating points of transistors 106 and 107 are independent of V and o4, V1O4 is increased. The disadvantage is that even if the gain of the entire circuit is lowered, the maximum allowable input will not increase. Further, in the conventional circuit, not only the signal component but also the collector DC current of the transistor 108 changes depending on V2O3, so there is a drawback that not only the gain but also the DC potential of the output terminal 111 changes.

〔問題点を解決するだめの手段〕[Failure to solve the problem]

本発明の可変利得増幅器は、差動増幅器を構成する第1
.第2のトランジスタを有し、この第1゜第2のトラン
ジスタのエミッタには、各々同じ値を有する第1.第2
の抵抗を介して第1の定電流源に接続され、第二の差動
増幅器を成すエミッタ同士が接続された第3.第4のト
ランジスタを有し、前記第3のトランジスタのベースは
前記第1のトランジスタのベースに接続され、前記第3
のトランジスタのコレクタは前記第1のトランジスタの
コレクタに接続され、前記第4のトランジスタのベース
は前記第2のトランジスタのベースニ接続され、前記第
4のトランジスタのコレクタは前記第2のトランジスタ
のコレクタに接続され、前記第1.第3のトランジスタ
のコレクタと第2゜第4のコレクタの少なくとも一方に
出力を取り出すことを目的とした負荷あるいは負荷回路
を備え、前記第3.第4のトランジスタのエミッタ同士
の接続点と前記第1の定電流源とが第2の抵抗を介して
接続され、前記第3.第4のエミッタの接続点に前記第
1の電流源と等しい電流の第2の電流源が接続され、前
記第1.第2の電流源の電流値を電気的に制御し変化さ
せる手段を有していることを特徴とする。
The variable gain amplifier of the present invention comprises a first
.. a second transistor, and the emitters of the first and second transistors each have the same value. Second
is connected to the first constant current source through a resistor, and the third. a fourth transistor, the base of the third transistor is connected to the base of the first transistor, and the base of the third transistor is connected to the base of the first transistor;
The collector of the transistor is connected to the collector of the first transistor, the base of the fourth transistor is connected to the base of the second transistor, and the collector of the fourth transistor is connected to the collector of the second transistor. connected to the first. A load or a load circuit for the purpose of taking out an output is provided to at least one of the collector of the third transistor and the second and fourth collectors, A connection point between the emitters of the fourth transistor and the first constant current source are connected via a second resistor, and the third. A second current source having a current equal to that of the first current source is connected to the connection point of the fourth emitter, and a second current source having a current equal to that of the first current source is connected to the connection point of the fourth emitter. It is characterized by having means for electrically controlling and changing the current value of the second current source.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例の回路図である。FIG. 1 is a circuit diagram of an embodiment of the present invention.

トランジスタ24、電源1、定電流源3、抵抗9.10
はベース直流バイアス回路である。トランジスタ16,
17、抵抗13,14で第1の差動増幅器を構成してい
る。トランジスタ18.19はエミッタ同士が直接結線
されていて第1の差動増幅器より高い利得を持りた第2
の差動増幅器を成す。
Transistor 24, power supply 1, constant current source 3, resistor 9.10
is the base DC bias circuit. transistor 16,
17, and resistors 13 and 14 constitute a first differential amplifier. The transistors 18 and 19 have their emitters directly connected to each other and have a higher gain than the first differential amplifier.
It forms a differential amplifier.

定電流源7,8は電気的に制御可能で制御電圧vcに対
し、ともに等しい電流を発生する。電流源7゜8の電流
値をI?、L  とする。抵抗13 、14 、15゜
20.21の抵抗値をR13,RI41 RI51 R
4゜、R2,とする。I、=I、でI、=O、1,=O
の時、トランジスタ16〜19のエミッタ電流を各々I
g□6.工8□7゜II工8 + I 119とすると
、 工E16・R13=ΔVag+2Rts・Igxa  
 −=(1)I E16°R13)ΔVBgすらば IE16@R13中2R15lB18       ・
−・・・・(2)Iy=Is#Oの時は VI  VBB18  Rls(2Igtg+Iy)=
Vt −■Bgts−R13Igxs・・・・・・(3
) Vtはt源1o電圧、vBgts *VBB16はトラ
ンジスタ18.16のベース、エミッタ順方向電圧であ
る。
The constant current sources 7 and 8 are electrically controllable and both generate the same current with respect to the control voltage vc. The current value of current source 7°8 is I? , L. The resistance values of resistors 13, 14, 15゜20.21 are R13, RI41 RI51 R
4°, R2, I, = I, and I, = O, 1, = O
When , the emitter currents of transistors 16 to 19 are respectively I
g□6. Engineering 8□7゜II Engineering 8 + I 119, Engineering E16・R13=ΔVag+2Rts・Igxa
-=(1)I E16°R13) If ΔVBg is IE16@R13 2R15lB18 ・
-・・・(2) When Iy=Is#O, VI VBB18 Rls(2Igtg+Iy)=
Vt-■Bgts-R13Igxs...(3
) Vt is the t source 1o voltage, vBgts *VBB16 is the base-emitter forward voltage of the transistor 18.16.

にはボルツマン定数、Tは絶対温度、qは電荷素置であ
る。ここで(2)と同様の近似を行ってVBIB 18
 中VBE16 r  (3)式を整理シテ(4)式と
(5)式を比較するとRls”I、ルR1s+Rts)
の項だけ増減していることがわかシ、出力端子22゜2
3の直流電位が工、によって変動しないことが判明する
is the Boltzmann constant, T is the absolute temperature, and q is the charge element. Here, by making the same approximation as in (2), VBIB 18
Medium VBE16 r Organize equation (3) and compare equations (4) and (5): Rls"I, R1s+Rts)
It can be seen that the term increases and decreases by the term, output terminal 22゜2
It turns out that the DC potential of No. 3 does not change due to engineering.

第2の差動増幅器の小信号電圧利得をAvzとすれば(
4)式よシ 同様に第一の差動増幅器1の利得AVIを求める。
If the small signal voltage gain of the second differential amplifier is Avz, then (
4) Find the gain AVI of the first differential amplifier 1 in the same manner as in equation 2.

よって第1図の回路の総合利得AVは Ay = AVI + AV2 になる様に各々の回路定数を選べば、利得AvはI、の
1次単調減少関数になる。
Therefore, if each circuit constant is selected so that the overall gain AV of the circuit shown in FIG. 1 becomes Ay = AVI + AV2, the gain Av becomes a linear monotonically decreasing function of I.

次に最大許容入力に関する考察を行う。Next, we will consider the maximum allowable input.

式(4)十式(s) ” I 6 / 2よって負荷2
0.21を流れる直流電流I1.Isと無関係である。
Equation (4) 10 equations (s) ” I 6 / 2 Therefore, load 2
0.21 of the direct current I1. It has nothing to do with Is.

従って負荷20.21の両端から取り出せる最大振幅は
I s x Rv(又はl6XR1υである。
Therefore, the maximum amplitude that can be extracted from both ends of the load 20.21 is I s x Rv (or 16XR1υ).

ここでA V =A vx +A V2が(6)式の条
件を満すとして 最大許容人力Vimaxは R13や工、やKは入力信号やI?、ILに無関係な定
数とみなせるから K R1s > O又K。>0 (7)式から工、が大きくなるとVimaxは大きくな
ることがわかる。
Here, assuming that A V = A vx + A V2 satisfies the condition of equation (6), the maximum allowable human power Vimax is R13 or the force, and K is the input signal or I? , can be regarded as a constant unrelated to IL, so K R1s > O or K. >0 From equation (7), it can be seen that Vimax increases as k increases.

すなわち第1図の回路は、端子工、によって利得が制御
可能で出力端子の直流電位が利得に無関係に一定でさら
に低利得になるほどダイナミックレンジが広がるのであ
る。
That is, in the circuit shown in FIG. 1, the gain can be controlled by the terminals, the DC potential at the output terminal is constant regardless of the gain, and the lower the gain, the wider the dynamic range.

第2図は利得をしぼった時の負荷の電圧出力と入力電圧
の略図にして示したものである。
FIG. 2 is a schematic diagram of the voltage output and input voltage of the load when the gain is reduced.

第3図は第2図同様に利得を上げた時の入出力を示した
略図である。
FIG. 3 is a schematic diagram showing input and output when the gain is increased, similar to FIG. 2.

第6図はPNPトランジスタによって本発明の他の実施
例の回路図である。第1図と同じ素子には同じ番号を付
す。トランジスタ24.25と抵抗13.14が利得の
低い第一の差動増幅器を構成し、トランジスタ26.2
7で利得の高い第二の差動増幅器が構成される。
FIG. 6 is a circuit diagram of another embodiment of the present invention using a PNP transistor. Elements that are the same as in FIG. 1 are given the same numbers. Transistor 24.25 and resistor 13.14 constitute a first differential amplifier with low gain, and transistor 26.2
7 constitutes a second differential amplifier with high gain.

トランジスタ34と抵抗35で構成される定電流源が、
カレントミラ一対の基準電流を発生させ、この電流は、
可変電圧源37で制御される。トランジスタ29.抵抗
32で構成される定tg源とトランジスタ38.抵抗3
9で構成される定電流源は同じ電流値を有し電圧源37
によって電流値が変化する。
A constant current source composed of a transistor 34 and a resistor 35 is
A reference current for a pair of current mirrors is generated, and this current is
It is controlled by a variable voltage source 37. Transistor 29. A constant tg source consisting of a resistor 32 and a transistor 38. resistance 3
The constant current sources 37 and 9 have the same current value and the voltage source 37
The current value changes depending on the

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、利得が高く、かつ利得自
体がエミッタ電流に強く依存する差動増幅器と、エミッ
タに抵抗が挿入され利得が低く、かつ利得が前出のエミ
ッタに挿入された抵抗の値でほぼ決定されエミッタ電流
にほとんど依存しない差動増幅器を有し、電気的に制御
可能な電流源によって二つの増幅器の出力を混合する比
率と、前記利得の高い差動増幅器の利得を変えることで
、総合利得をしぼった場合にも高い最大許容入力振幅を
実現し、出力端子の直流電位が変化しない可変利得増幅
器を実現できる。
As explained above, the present invention provides a differential amplifier that has a high gain and whose gain itself strongly depends on the emitter current, and a differential amplifier that has a resistor inserted in the emitter and has a low gain and whose gain is has a differential amplifier that is approximately determined by the value of and is almost independent of the emitter current, and changes the ratio at which the outputs of the two amplifiers are mixed by an electrically controllable current source and the gain of the high gain differential amplifier. This makes it possible to realize a high maximum allowable input amplitude even when the overall gain is reduced, and to realize a variable gain amplifier in which the DC potential at the output terminal does not change.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の回路図、第2図。 第3図は第1図の動作を示す説明図、第6図は本発明の
他の実施例の回路図、第1図は従来例の回路図、第4図
、第5図は第1図の動作を示す説明図である。 1・・・・・・トランジスタのベースバイアスIZ6’
X、2・・・・・・電源、3・・・・・・定電流源、4
,5・・・・・・位相が互いに180°ずれた信号源、
6・・・・・・差動増幅器を成す定電流源、7,8・・
・・・・定電流源、9.10・・・・・・抵抗、11,
12・・・・・・結合コンデンサ、13.14・旧・・
エミッタ抵抗、15・・・・・・抵抗、16.17 )
ランジスタ、18,19・・・・・・トランジスタ、2
0.21・旧・・負荷抵抗、22.23・・・・・・出
力端子、24,25・・・・・・トランジスタ、26.
27・・・・・・トランジスタ、28・・・・・・トラ
ンジスタ、29,30,33.38・・・・・・トラン
ジスタ、31,32,36,39・・・・・・抵抗、3
4・・・・・・トランジスタ、35・・・・・・抵抗、
37・・・・・・可変電圧源。 第 1 図 第 2習 翳3 回 声■;鳳χi     入諜憬 翳 4 図 亭 5 閃 第 6 v
FIG. 1 is a circuit diagram of an embodiment of the present invention, and FIG. 2 is a circuit diagram of an embodiment of the present invention. FIG. 3 is an explanatory diagram showing the operation of FIG. 1, FIG. 6 is a circuit diagram of another embodiment of the present invention, FIG. 1 is a circuit diagram of a conventional example, and FIGS. 4 and 5 are the diagrams shown in FIG. It is an explanatory diagram showing operation of. 1...Transistor base bias IZ6'
X, 2...Power supply, 3...Constant current source, 4
, 5... Signal sources whose phases are shifted by 180° from each other,
6... Constant current source forming a differential amplifier, 7, 8...
... Constant current source, 9.10 ... Resistor, 11,
12... Coupling capacitor, 13.14 Old...
Emitter resistance, 15...Resistance, 16.17)
Transistor, 18, 19...Transistor, 2
0.21 Old... Load resistance, 22.23... Output terminal, 24, 25... Transistor, 26.
27...Transistor, 28...Transistor, 29,30,33.38...Transistor, 31,32,36,39...Resistor, 3
4...Transistor, 35...Resistor,
37...Variable voltage source. Fig. 1 Fig. 2 Xi'an 3 Round ■; Feng χi Infiltration 憬翳 4 Zuting 5 Sendai 6 v

Claims (1)

【特許請求の範囲】[Claims] 差動増幅器を構成する第1、第2のトランジスタを有し
、この第1、第2のトランジスタのエミッタには各々同
じ値を有する第1、第2の抵抗を介して第1の定電流源
に接続され、第二の差動増幅器を成すエミッタ同士が接
続された第3、第4のトランジスタを有し、前記第3の
トランジスタのベースは前記第1のトランジスタのベー
スに接続され、前記第3のトランジスタのコレクタは前
記第1のトランジスタのコレクタに接続され、前記第4
のトランジスタのベースは前記第2のトランジスタのベ
ースに接続され、前記第4のトランジスタのコレクタは
前記第2のトランジスタのコレクタに接続され、前記第
1、第3のトランジスタのコレクタと第2、第4のコレ
クタの少なくとも一方に出力を取り出すことを目的とし
た負荷あるいは負荷回路を備え、前記第3、第4のトラ
ンジスタのエミッタ同士の接続点と前記第1の定電流源
とが第2の抵抗を介して接続され、前記第3、第4のエ
ミッタの接続点に前記第1の電流源と等しい電流の第2
の電流源が接続され、前記第1、第2の電流源の電流値
を電気的に制御し変化させる手段を有していることを特
徴とする可変利得増幅器。
It has first and second transistors forming a differential amplifier, and a first constant current source is connected to the emitters of the first and second transistors through first and second resistors having the same value, respectively. and has third and fourth transistors whose emitters are connected to each other forming a second differential amplifier, the base of the third transistor is connected to the base of the first transistor, and the base of the third transistor is connected to the base of the first transistor. The collector of the third transistor is connected to the collector of the first transistor, and the collector of the fourth transistor is connected to the collector of the first transistor.
The base of the transistor is connected to the base of the second transistor, the collector of the fourth transistor is connected to the collector of the second transistor, and the collectors of the first and third transistors are connected to the base of the second transistor. A load or a load circuit for the purpose of taking out an output is provided on at least one of the collectors of the fourth transistor, and a connection point between the emitters of the third and fourth transistors and the first constant current source are connected to a second resistor. and a second current source having a current equal to that of the first current source is connected to the connection point of the third and fourth emitters.
A variable gain amplifier characterized in that a current source is connected to the variable gain amplifier, and the variable gain amplifier has means for electrically controlling and changing the current values of the first and second current sources.
JP11970387A 1987-05-15 1987-05-15 Variable gain amplifier Expired - Lifetime JPH0612860B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11970387A JPH0612860B2 (en) 1987-05-15 1987-05-15 Variable gain amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11970387A JPH0612860B2 (en) 1987-05-15 1987-05-15 Variable gain amplifier

Publications (2)

Publication Number Publication Date
JPS63284913A true JPS63284913A (en) 1988-11-22
JPH0612860B2 JPH0612860B2 (en) 1994-02-16

Family

ID=14767992

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11970387A Expired - Lifetime JPH0612860B2 (en) 1987-05-15 1987-05-15 Variable gain amplifier

Country Status (1)

Country Link
JP (1) JPH0612860B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008135909A (en) * 2006-11-28 2008-06-12 Nippon Telegr & Teleph Corp <Ntt> Variable gain circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008135909A (en) * 2006-11-28 2008-06-12 Nippon Telegr & Teleph Corp <Ntt> Variable gain circuit

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Publication number Publication date
JPH0612860B2 (en) 1994-02-16

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