JPH0519323B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a muting circuit that suppresses the level of an input signal and performs output muting.

Conventionally, in audio equipment, a muting circuit selects an attenuator element added to an amplifier using an external changeover switch to obtain a desired muting characteristic. In this case, since the changeover switch is a mechanical switch, it is susceptible to noise and has low reliability.

Further, as shown in FIG. 1, a muting circuit may be configured. That is, a variable resistor 4 is connected to the signal source 2, an amplifier 8 is connected to the movable end of the variable resistor 4 via a coupling capacitor 6, and an output signal is connected to the output side of the amplifier 8 via a capacitor 10. A terminal 12 is formed. In this case, the input signal level can be set to a desired level by adjusting the variable resistor 4, and the level-adjusted input signal can be taken out from the output terminal 12 via the amplifier 8.

In this case, the muting characteristic is the variable resistance 4
However, using such a variable resistor 4 has the disadvantage that the input signal level fluctuates and the muting characteristics become unstable.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a muting circuit that stabilizes the muting characteristics.

That is, the muting circuit of the present invention connects an input terminal 18 that receives an input signal, and a series circuit consisting of resistors 22, 24 and a capacitor 26 between this input terminal and a reference potential point, and a level setting circuit 20 for setting an arbitrary muting level; and a first circuit having a common emitter.
and a first current mirror circuit (transistors 38, 40) is connected to the emitter side of the second (transistors 34, 36), and the input signal is applied to the base of the first transistor through the input terminal, A feedback signal is applied to the base of the second transistor from the output side, and the first differential amplifier 14 passes or amplifies the input signal, and the third and fourth transistors (transistors 42, 42, 44) on the emitter side.
current mirror circuit (transistors 46, 4
8), and the input signal set to the mutating level is applied to the base of the third transistor through the level setting circuit, and a feedback signal is applied from the output side to the base of the fourth transistor. a second differential amplifier 16 that passes or amplifies the input signal set to the muting level; a switch (switch 30) that switches the operation of the first and second differential amplifiers; A constant current source 6 that uses a common emitter and supplies operating current to the emitter side.
6 is connected to the fifth and sixth (transistor 6
2, 64) is installed, a high-level or low-level DC voltage is selectively applied to the base of the fifth transistor of the differential circuit by the switch, and the sixth A DC voltage lower than the high level DC voltage and higher than the low level DC voltage is set in the transistor, and the fifth transistor is selectively switched to a conductive state by switching the switch. When the first differential amplifier
An operating current is supplied through the current mirror circuit, and when the sixth transistor is switched to a conductive state, the operating current is supplied to the second differential amplifier through the second current mirror circuit. a switching control circuit 28 that selectively switches the first or second differential amplifier to an operating state; a collector side of a first transistor of the first differential amplifier; a third current mirror circuit (transistors 51, 56) installed as a common active load on the collector side of the transistor No. 3; a collector side of the second transistor of the first differential amplifier; A fourth current mirror circuit (transistors 52, 54) installed as a common active load on the collector side of the fourth transistor of the amplifier,
The present invention is characterized in that it includes an output circuit output amplifier 53 that combines and extracts the respective outputs taken out through the third and fourth current mirror circuits.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 shows an embodiment of the muting circuit of the invention. In the figure, this muting circuit includes first and second differential amplifiers 14 and 16.
A level setting circuit 20 is connected to the non-inverting input terminal (+) of each differential amplifier 14, 16 to set the level of the input signal applied to the input terminal 18 for each differential amplifier 14, 16. There is. The level setting circuit 20 inputs the input signal applied through the input terminal 18 to the differential amplifier 14 without causing a level change in the input signal, suppresses the level, and sets the input signal to a muting level. and applies that input signal to the differential amplifier 16. That is, the input terminal 18 is connected to the resistor 2
The non-inverting input terminal (+) of the differential amplifier 14 is connected to the input terminal 18 side of the level setting circuit 20. The non-inverting input terminal (+) of is connected between resistors 22 and 24.

Each differential amplifier 14, 16 has a switching control circuit 28
It is configured such that its operation can be selectively switched in response to control input from the controller. A switching control signal is given to the switching control circuit 28 based on potential changes caused by opening and closing of the switching switch 30, and is composed of other electronic switches (not shown).

Further, the output sides of each differential amplifier 14 and 16 are connected in common to form an output terminal 32, and are connected to an inverting input terminal (-) of each differential amplifier 14 and 16 to form a feedback circuit. It is configured.
That is, since each output is fully fed back, the amplification gain Av of each differential amplifier 14, 16 is set to Av=1.

The operation will be explained based on the above configuration. As the changeover switch 30 opens and closes, the changeover control circuit 28
A control input is applied to each differential amplifier 14, 16 from the differential amplifier 14, 16, and the operation of the differential amplifiers 14, 16 is selectively switched. As in this embodiment, each differential amplifier 1
When the amplification gain of 4,16 is set to Av=1,
The resistance values of resistors 22 and 24 are R ₂₂ , R ₂₄ ,
Assuming that the input signal is Vin, when the differential amplifier 14 is in operation, its output Vo ₁ is given by Vo ₁ = (R ₂₂ + R ₂₄ )·Vin/(R ₂₂ + R ₂₄ )...(1), Also, when the differential amplifier 16 is in operation, the amplification gain obtained on the differential amplifier 4 side
Gvc ₂ is given by Vo ₂ = R ₂₄ · Vin/(R ₂₂ + R ₂₄ ) (2).

As is clear from such input/output characteristics, when the differential amplifier 14 is in operation, the input-output characteristics are such that the amplification gain Av=1, so the input signal level can be taken out from the output terminal 32 without changing the input signal level. Furthermore, when the differential amplifier 16 is in operation, an output at a level lower than the input signal level is obtained, and a muting characteristic is provided.

In this way, the input signal level can be switched by switching the differential amplifiers 14 and 16 using the switching control circuit 28, and the resistance values R ₂₂ and R 24 of the resistors 22 and ₂₄ of the level setting circuit 20 can be set arbitrarily. By setting the value of , the output level of the differential amplifier 16 can be set to an arbitrary value.

Furthermore, in this embodiment, two types of levels are set using the differential amplifiers 14 and 16, but by installing a plurality of differential amplifiers, three or more levels can be set and the muting characteristics can be finely adjusted. .

Furthermore, as is clear from the embodiment, since the operation of the differential amplifiers 14 and 16 is electronically switched by the switching control circuit 28, there is no need to set a mechanical switch inside the level setting circuit 20, and A variable resistor for level adjustment can be eliminated, the reliability of level switching can be improved, and the influence of noise can be eliminated. Furthermore, since a mechanical switch can be omitted, the configuration can be simplified and made more compact.

FIG. 3 shows a specific embodiment of the muting circuit of the present invention, and the same parts as those in the circuit shown in FIG. 1 are given the same reference numerals. In the figure, the differential amplifier 14 includes first and second amplifiers with a common emitter.
A first current mirror circuit consisting of transistors 38 and 40 as an active load is connected to a differential pair consisting of transistors 34 and 36, and the differential amplifier 16 has a first current mirror circuit having a common emitter. A second current mirror circuit comprising transistors 46 and 48 as an active load is connected to a differential pair comprising third and fourth transistors 42 and 44. That is, transistor 3
4 and 36 have their emitters connected in common, and a transistor 38 is connected between this emitter and a terminal 47 for connection to a reference potential point (GND), and a transistor 40 having a diode configuration is connected to the base of this transistor 38. The base collector is connected
A control signal is applied to this base collector from a switching control circuit 28. Also, transistor 4
The emitters of No. 2 and 44 are connected in common, and a transistor 46 is connected between this emitter and a reference potential point, and the base and collector of a diode-configured transistor 48 are connected to the base of this transistor 46. - A control input is given to the collector from the switching control circuit 28. The input terminal 18 is formed in the transistor 34, and the resistors 22, 24 and the capacitor 26 of the level setting circuit 20 are connected between the transistor 34 and a bias terminal 49 to which a DC bias is applied. The reason why a constant DC bias voltage is applied to the bias input terminal 49 is to avoid this because if the DC bias voltage is not applied, the capacitor 26 will not operate while being charged and will also be subject to transient phenomena during charging and discharging. It's for a reason. Further, the capacitor 26 is necessary for DC cut in order to extract the offset voltage. In particular, when mass producing ICs, offsets may occur depending on the product.
It is necessary to provide a capacitor 26.

Further, a diode-configured transistor 51 is connected between the collectors of the transistors 34 and 42 and a power supply terminal 50, and the transistors 36 and 44
A diode-configured transistor 52 is connected between the collector of the power supply terminal 50 and the power supply terminal 50 . In this embodiment, an output amplifier 53 as an output circuit for taking out the outputs of the differential amplifiers 14 and 16 is installed on the output side of the differential amplifiers 14 and 16, and the base of the transistor 52 is the base of the transistor 54 of the output amplifier 53. connected to the transistor 51
The base of is connected to the base of transistor 56. In the output amplifier 53, the emitters of the transistors 54 and 56 are connected to the power supply terminal 50, and a diode-configured transistor 58 is connected between the collector of the transistor 54 and the reference potential point. A transistor 60 is connected to the potential point.
are connected, and the bases of each transistor 58, 60 are commonly connected. The commonly connected collectors of the transistors 56 and 60 form an output terminal 32.

That is, a third current mirror circuit that uses the transistors 51 and 56 to take out the output from the transistors 34 and 42 side of the differential amplifiers 14 and 16 also uses the transistors 52 and 54 to take out the output from the transistors 34 and 42 side of the differential amplifiers 14 and 16.
A fourth current mirror circuit is configured to take out the output from the transistors 36 and 44 side.

The switching control circuit 28 includes fifth and sixth transistors 62 and 64 having a common emitter.
A constant current source 66 is connected between the emitters of transistors 62 and 64 of this differential circuit and a reference potential point, and a diode configuration is connected between the transistor 62 and the power supply line. A transistor 68 is connected, and this transistor 6
The base of the transistor 8 is connected to the base of a transistor 70, which is connected to the power supply line and the base and collector of the transistor 40. A diode-configured transistor 71 is connected between the collector of one transistor 64 and the power supply line, and the base of the transistor 72 is commonly connected to the base of this transistor 71. connected to the base collector of

A constant bias is set to the base of the transistor 64 from a voltage dividing point of a resistor 74 and diodes 76 and 78 connected between the power supply line and a reference potential point. The base of the transistor 62 is connected to the power supply line via a resistor 80, and a changeover switch 3 is connected between the base and the reference potential point.
0 is inserted. That is, a high level or low level DC voltage is applied to the base of the transistor 62 by switching the changeover switch 30, and a low level DC voltage lower than the high level DC voltage is applied to the base of the transistor 64. A DC voltage higher than the above DC voltage is applied, and the transistors 62 and 64 are selectively turned on by switching the level of the DC voltage by the changeover switch 30.

The operation will be explained based on the above configuration. A signal shown in FIG. 4A is applied to the input terminal 18, and FIG. 4B shows changes in the base potential of the transistor 62 as the changeover switch 30 is turned on and off. With this change in base potential, the operations of the transistors 62 and 64 are selectively switched,
Changes in the base potential of the transistor 38 are shown in Figure 4C.
At the same time, the base potential of transistor 48 is switched as shown in FIG. 4D. As a result, the operations of the differential amplifiers 14 and 16 are selectively switched, and the input signals at the level set by the level setting circuit 20 are individually applied to the output terminal 32, and the differential amplifiers 14 and 16 are Output terminal 32 according to operation switching of amplifiers 14 and 16
That is, from the differential amplifier 14 to the differential amplifier 16
When the operation is switched to , the output is continuously switched between the waveform E ₁ generated when the differential amplifier 14 operates and the waveform E ₂ generated when the differential amplifier 16 operates.

In this way, the switching between the differential amplifiers 14 and 16 can be performed by the switching control circuit 28, and the reliability of level switching can be improved. Furthermore, in terms of circuit configuration, the differential amplifiers 14 and 16, the switching control circuit 28, and the output amplifier 53 are integrally formed by an integrated circuit, and external components are eliminated.

Note that also in this embodiment, the differential amplifier 1
In addition to 4 and 16, a plurality of differential amplifiers can be installed and several types of levels can be set and selected.

As explained above, according to the present invention, the first
An input signal at a normal level is applied to the second differential amplifier, an input signal suppressed to the mutating level is applied to the second differential amplifier through a level setting circuit, and when non-mutating, the first differential amplifier is selectively input. By switching the differential amplifier to the operating state and selectively switching the second differential amplifier to the operating state during muting, it is possible to obtain a normal output during non-mutating and a muting level output during muting.
When switching from non-mutating to muting or from mutating to non-muting,
without sudden level changes or discontinuities,
Since the output signal can be taken out, it is possible to avoid the generation of noise caused by muting switching or adjustment as in conventional circuits.Furthermore, since there is no need to use mechanical switches or variable resistors, the reliability of output signal level switching can be improved. It is possible to improve performance and simplify the circuit configuration.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional muting circuit, FIG. 2 is a block diagram showing an embodiment of the muting circuit of the present invention, and FIG. 3 is a circuit diagram showing a specific embodiment of the muting circuit of the present invention.
FIG. 4 is an explanatory diagram showing the operation timing and input/output waveforms. 14...First differential amplifier, 16...Second differential amplifier, 18...Input terminal, 20...Level setting circuit, 22, 24...Resistor, 26...Capacitor, 28...Switching control Circuit, 30... Selector switch, 34... First transistor, 36... Second
transistor, 38, 40... transistor (first current mirror circuit), 42... third transistor, 44... fourth transistor, 4
6, 48... Transistor (second current mirror circuit), 51, 56... Transistor (third current mirror circuit), 52, 54... Transistor (fourth current mirror circuit), 53... Output amplifier (Output circuit), 62...Fifth transistor, 64...Sixth transistor, 66... Constant current source.

Claims (1)

[Claims] 1. An input terminal that receives an input signal, and a series circuit consisting of a resistor and a capacitor connected between this input terminal and a reference potential point, and an arbitrary muting level set for the input signal. A first current mirror circuit is connected to the emitter sides of first and second transistors having a common emitter, and the input signal is applied to the base of the first transistor through the input terminal. At the same time, a feedback signal is applied to the base of the second transistor from the output side, a first differential amplifier that passes or amplifies the input signal, and third and fourth transistors having a common emitter. A second current mirror circuit is connected to the emitter side, and the input signal set to the muting level is applied to the base of the third transistor through the level setting circuit, and the input signal set to the muting level is applied to the base of the fourth transistor. a second differential amplifier to which a feedback signal is applied from the output side and which passes or amplifies the input signal set to the muting level; a switch which switches the operation of the first and second differential amplifiers; , the fifth and the sixth, which have a common emitter and are connected to a constant current source that supplies an operating current to the emitter side.
A differential circuit consisting of transistors is installed, and a high-level or low-level DC voltage is selectively applied to the base of the fifth transistor of the differential circuit by the switch, and When a DC voltage of a level lower than the high level DC voltage and higher than the low level DC voltage is applied, and the fifth transistor is selectively switched to a conductive state by switching the switch, the first differential amplifier;
An operating current is supplied through the current mirror circuit, and when the sixth transistor is switched to a conductive state, the operating current is supplied to the second differential amplifier through the second current mirror circuit. a switching control circuit that selectively switches the first or second differential amplifier to an operating state by; a collector side of a first transistor of the first differential amplifier; a third current mirror circuit installed as a common active load on the collector side of the transistor; a collector side of the second transistor of the first differential amplifier;
A fourth transistor installed as a common active load on the collector side of the fourth transistor of the second differential amplifier.
What is claimed is: 1. A muting circuit comprising: a current mirror circuit; and an output circuit that synthesizes and extracts each output taken out through the third and fourth current mirror circuits.