JPS63284844A - High density integrated element with connector terminal - Google Patents

High density integrated element with connector terminal

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Publication number
JPS63284844A
JPS63284844A JP11976387A JP11976387A JPS63284844A JP S63284844 A JPS63284844 A JP S63284844A JP 11976387 A JP11976387 A JP 11976387A JP 11976387 A JP11976387 A JP 11976387A JP S63284844 A JPS63284844 A JP S63284844A
Authority
JP
Japan
Prior art keywords
connector
package
lsi
board
connector terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11976387A
Other languages
Japanese (ja)
Inventor
Mitsu Takao
高尾 密
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11976387A priority Critical patent/JPS63284844A/en
Publication of JPS63284844A publication Critical patent/JPS63284844A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To make a lot of LSi chips mountable on one sheet of a substrate, by mounting connector terminals on an upper plane of a package and connecting any connector terminals to leads disposed on a lower or side plane of the package. CONSTITUTION:Conductive pins 11-2 piercing a package 11-1 are disposed on lead mounting positions and other positions of a package in which semiconductor chips are housed to be projected in fixed dimensions from both upper and lower planes of the package. Unillustrated semiconductor chips are connected to some pins 11-2. Leads 11-2a connected to a substrate and connector terminals 11-2b connected to cables are disposed on the lower plane of the package 11-1 and on the upper plane of it, respectively. Namely LSi chips 11 with connector terminals are mounted on the whole main surface of the substrate 12. The connector terminals 11-2b for the LSi chips 11, disposed on terminal edges on the insertion side of the terminals, are connected to connectors 13-1 of a back panel 13 by using cables 14 fitted with cable connectors 14-1, 14-2 on both their ends. Any LSi chips 11 on a front side are connected to this unit by using cables 15 fitted with the cable connectors 14-1, so that mounting density can be upgraded.

Description

【発明の詳細な説明】 (概要〕 半導体チップを収納したパッケージに、導電性の良い貫
通ピンを指定位置で上下両面より突出させて配列し、そ
の一部のピンと半導体チップとを接続してパッケージの
下面にリードを、上面にコネクタ端子を配設して従来の
プリント板コネクタの機能も具備した高密度集積素子。
[Detailed Description of the Invention] (Summary) Penetrating pins with good conductivity are arranged in specified positions in a package containing a semiconductor chip so as to protrude from both the upper and lower surfaces, and some of the pins are connected to the semiconductor chip to package the package. A high-density integrated device with leads on the bottom side and connector terminals on the top side, which also functions as a conventional printed board connector.

〔産業上の利用分野〕[Industrial application field]

本発明は各種電子機器の構成に広く使用される高密度集
積素子に関するものである。
The present invention relates to high-density integrated devices widely used in the construction of various electronic devices.

特に、中・大型電子機器に搭載するプリント板は多数個
の高密度集積素子(以下LSiと略称する)を実装する
ため大きな基板が必要となり、且つLSiの実装レイア
ウトと基板の配線パターン設計が複雑化している。
In particular, printed circuit boards installed in medium-sized and large-sized electronic devices require large boards to mount a large number of high-density integrated devices (hereinafter referred to as LSi), and the LSi mounting layout and board wiring pattern design are complicated. It has become

そのため、基板の小型化と配線パターン等の設計が容易
となる実装方法が可能なコネクタ端子付き高密度集積素
子が要求されている。
Therefore, there is a need for a high-density integrated element with connector terminals that can be mounted using a mounting method that facilitates miniaturization of the board and easy design of wiring patterns and the like.

〔従来の技術〕[Conventional technology]

従来広く使用されているLSiは、第5図に示すように
プラスチック、セラミック等の絶縁体で封止された半導
体チップのり一部1−2aが、(a)図に示すようにパ
ッケージ1−1の下側から平行に出るピングリッドアレ
イパッケージ、中)図に示す四方の側面から平らに出る
フラットパッケージ、(C)の底面図に示すように四方
の側面から出て下面となる面に3字形に形成したリード
レスチップキャリア、および、図示しないが両側面から
下方へ配列したデュアルインパッケージがある。
As shown in FIG. 5, in the LSi that has been widely used in the past, a semiconductor chip part 1-2a sealed with an insulator such as plastic or ceramic is assembled into a package 1-1 as shown in FIG. A pin grid array package that comes out in parallel from the bottom of the , (middle) a flat package that comes out flat from the four sides shown in the figure, and a 3-shaped package that comes out from the bottom of the four sides as shown in the bottom view of (C). There is also a leadless chip carrier formed on the chip carrier, and a dual-in package (not shown) arranged downward from both sides.

そして実装方法は第6図に示すように、基板2主面の所
定位置に上記LSilをそれぞれ実装して、挿入方向の
前後側縁にバックパネル3およびケーブル4とに接続す
るプリント板コネクタ2−1を実装し、必要により改造
ワイヤ5でLSi間の接続回路を修正してプリント板を
形成する。
As shown in FIG. 6, the mounting method is to mount each of the LSils at predetermined positions on the main surface of the board 2, and connect the printed board connector 2 to the back panel 3 and cable 4 at the front and rear edges in the insertion direction. 1 is mounted, and if necessary, the connection circuit between the LSis is modified using a modified wire 5 to form a printed board.

そして上記プリント板の一方に配設したプリント板コネ
クタ2−1をバックパネル3のコネクタ3−1に挿入し
て接続し、他方のプリント板コネクタ2−1にケーブル
コネクタ4−1を結合している。
Then, the printed board connector 2-1 arranged on one of the printed boards is inserted and connected to the connector 3-1 of the back panel 3, and the cable connector 4-1 is connected to the other printed board connector 2-1. There is.

〔発明が解決しようとする問題点3 以上説明の従来のLSiで問題となるのは、基板に実装
したLSiとバックパネルおよび、ケーブルを接続する
プリント板コネクタを、基板の挿入方向前後両側縁に実
装しているために、(1)プリント板コネクタの実装領
域および基板内のコネクタとLSi間の配線領域“S”
が、基板の前後両側縁に配設されてLSiを実装するエ
リアに対して、コネクタ実装およびコネクタとLSi間
の配線領域だけ大きな基板が必要となる。
[Problem to be Solved by the Invention 3] The problem with the conventional LSi described above is that the printed board connectors for connecting the LSi mounted on the board, the back panel, and the cable are placed on both front and rear edges in the insertion direction of the board. (1) The mounting area of the printed board connector and the wiring area "S" between the connector and the LSi in the board.
However, a larger board is required for the connector mounting area and the wiring area between the connector and the LSi compared to the area provided on both front and rear edges of the board for mounting the LSi.

(2)実装したLSiとプリント板コネクタ間の配線パ
ターンの長さにより信号の伝送時間が異なるので、コネ
クタと特定のLSi間の配線を等長髭線する場合におい
て基板のLSi実装設計および配線パターン設計が複雑
となる。
(2) Since the signal transmission time differs depending on the length of the wiring pattern between the mounted LSi and the printed circuit board connector, the LSi mounting design of the board and the wiring pattern should be considered when the wiring between the connector and a specific LSi is wired with equal length. The design becomes complicated.

(3)ケーブルと接続するプリント板コネクタの位置が
基板の前面側に限定されているので、接続する他のユニ
ットの配置設計が複雑となる。また特殊電源を特徴とす
る特殊LSiとその電源供給用の配線との接続が困難で
ある。また、特殊電源を必要とするLSiをコネクタの
近くに限定実装するような制限をうける場合がある。
(3) Since the position of the printed board connector connected to the cable is limited to the front side of the board, the layout design of other units to be connected becomes complicated. Furthermore, it is difficult to connect a special LSi that features a special power source to its power supply wiring. In addition, there may be restrictions such as mounting an LSi that requires a special power supply only near the connector.

(4)基板の配線回路を必要により修正する場合にはそ
の配線パターンを切断して高密度実装したLSiの間に
細い改造ワイヤを配線し、改造ワイヤの両端をそれぞれ
LSiのリードまたは基板上の改造パッドに半田付けを
行うために、改造作業は作業者の熟練と多(の工数を必
要とする、等の問題点がある。
(4) When modifying the wiring circuit of the board as necessary, cut the wiring pattern, wire a thin modified wire between the LSis mounted in high density, and connect both ends of the modified wire to the leads of the LSi or the board. In order to solder the modified pad, the modification work requires the skill of the operator and a large number of man-hours.

そのため、装置の大型化につながるとともに設計・製造
コストを高騰させる原因となっている。
This leads to an increase in the size of the device and causes an increase in design and manufacturing costs.

本発明は以上のような状況から1枚の基板により多くの
LSiが実装でき、且つ任意のLSiとケーブルを直接
接続が可能となって、コネクタを任意の位置に配設でき
る自由度が大きくなり設計および製造コストを低減させ
るコネクタ端子付きLSiの提供を目的としたものであ
る。
In view of the above-mentioned circumstances, the present invention makes it possible to mount a large number of LSis on a single board, and to directly connect any LSi to a cable, increasing the degree of freedom in arranging connectors in any position. The object of the present invention is to provide an LSi with connector terminals that reduces design and manufacturing costs.

〔問題点を解決するための手段〕[Means for solving problems]

上記問題点は第1図に示すように、半導体チップを収納
したパッケージのリードを配設する位置および他の任意
の位置に、パッケージ11−1を貫通する導電性の良い
ピン11−2を上下両面より一定寸法突出させて配列し
、その一部のピン11−2と図示しない半導体チップと
を接続して、パッケージ11−1の下面に基板と接続す
るり−ド11−2 aと上面にケーブルと接続するコネ
クタ端子11−2 bを配設した本発明のコネクタ端子
付きLSiにより解決される。
As shown in Fig. 1, the above-mentioned problem is caused by placing pins 11-2, which have good conductivity and penetrating through the package 11-1, above and below the position where the leads of the package containing the semiconductor chip are arranged and at any other arbitrary position. The pins 11-2 are arranged so as to protrude from both sides by a certain dimension, and some of the pins 11-2 are connected to a semiconductor chip (not shown), and connected to the substrate on the lower surface of the package 11-1. This problem is solved by the LSi with a connector terminal of the present invention, which is provided with a connector terminal 11-2b for connection to a cable.

〔作用〕[Effect]

即ち本発明においては、導電性の良いピン11−2を貫
通して一部のピン11−2と半導体チップと接続したコ
ネクタ端子11−2 bをパッケージ11−1の上面に
設け、基板12と接続するリード11−2 aを下面に
配設して半導体チップと接続しない貫通ピン11−2を
、他のLSillに電源および信号供給用、あるいは信
号出力するための電源または信号用端子、接続したコネ
クタ端子11−2 bを信号用または電源供給用端子と
することにより従来のコネクタ機能を具備したLSiが
形成される。
That is, in the present invention, the connector terminal 11-2b is provided on the upper surface of the package 11-1 and is connected to some of the pins 11-2 and the semiconductor chip by penetrating the pins 11-2 having good conductivity. Connecting lead 11-2 The through pin 11-2, which has the lead a on the bottom surface and is not connected to the semiconductor chip, is connected to another LSill as a power supply or signal terminal for supplying power and signals, or for outputting signals. By using the connector terminal 11-2b as a signal or power supply terminal, an LSi having a conventional connector function is formed.

そのコネクタ端子付きLSillを第2図の斜視図に示
すように基板12の全主面に実装して、その挿入方向側
端縁に配列したLSillのコネクタ端子IL2bとバ
ックパネル13のコネクタ13−1を、両端にケーブル
コネクタ14−1.14−2を取着したケーブル14で
接続し、前面側の任意のLSillと図示しないユニッ
トをケーブルコネクタ14−1を取着したケーブル15
で接続することにより、(1)プリント板コネクタの実
装領域およびコネクタとLSi間の配vA領域が不要と
なり、LSillの実装領域が大きくなって基板の小型
化が可能となるとともに実装密度が向上する。
The LSill with connector terminals is mounted on the entire main surface of the board 12 as shown in the perspective view of FIG. are connected by a cable 14 with cable connectors 14-1 and 14-2 attached to both ends, and a cable 15 with a cable connector 14-1 attached to an arbitrary LSill on the front side and a unit (not shown).
(1) The mounting area of the printed board connector and the distribution area between the connector and the LSi become unnecessary, and the mounting area of the LSill increases, making it possible to downsize the board and improve the mounting density. .

(2)伝送される信号の遅延が問題となるLSillに
は直接そのコネクタ端子11−2 bに、基板12の配
線パターンに対して単位長当たり約1/2の遅延時間と
なるケーブル14で接続できるため、任意の位置にLS
illを実装できて基板12の実装設計および配線パタ
ーン設計が容易となる。
(2) Connect directly to the connector terminal 11-2b of the LSill where the delay in transmitted signals is a problem with the cable 14 that has a delay time of approximately 1/2 per unit length with respect to the wiring pattern of the board 12. LS can be placed in any position.
ill can be mounted, making mounting design and wiring pattern design of the board 12 easier.

(3)基板12の任意の方向から任意の位置に実装した
LSill上面のコネクタ端子11−2 bと接続でき
るため、コネクタ実装位置の自由度が大きく接続   
 ゛する他のユニット位置が制限されないのでその配置
設計が容易となる。また特殊電源を特徴とする特殊LS
illのコネクタ端子11−2 bに、図示しない電源
と接続したケーブル15のケーブルコネクタ14−1を
結合することにより特殊電源が供給できるので接続が容
易となり、従来の方法のように特殊電源を使用するLS
iの実装値をコネクタ近くに限定する必要がなくなる。
(3) Since it can be connected to the connector terminal 11-2b on the top surface of the LSill mounted from any direction to any position on the board 12, there is a large degree of freedom in the connector mounting position.
Since the positions of the other units are not restricted, the layout design becomes easy. Also, a special LS featuring a special power supply.
A special power supply can be supplied by connecting the cable connector 14-1 of the cable 15, which is connected to a power supply (not shown), to the connector terminal 11-2b of the illumination terminal 11-2b, making the connection easy, and the special power supply can be used as in the conventional method. LS to do
There is no need to limit the mounting value of i near the connector.

(4)基板12の配線回路を修正する場合は、その配線
パターンを切断してそれぞれのLSill上面に配列し
たコネクタ端子11−2 b間を改造ワイヤ16で配線
するか、または両端にケーブルコネクタ14−1を取着
したケーブルで接続できるので改造作業が容易となる、 等基板12の装置の小型化と装置製造コストの低減が可
能となる。
(4) When modifying the wiring circuit of the board 12, cut the wiring pattern and wire the modified wires 16 between the connector terminals 11-2b arranged on the top surface of each LSill, or connect the cable connectors 14 at both ends. Since it can be connected with the cable attached to -1, modification work is facilitated, and it is possible to downsize the device of the board 12 and reduce the device manufacturing cost.

〔実施例〕〔Example〕

以下第1図乃至第4図について本発明の詳細な説明する
The present invention will be described in detail below with reference to FIGS. 1 to 4.

第1図は第1実施例によるピンアレイグリッドパッケー
ジのコネクタ端子付きLSiを斜視図で示す。
FIG. 1 shows a perspective view of an LSi with connector terminals in a pin array grid package according to a first embodiment.

図に示すように、導電性の良い金属細線2例えばニッケ
ルめっき硬銅線よりなる直径0.2 n X長さ約12
mmのピン11−2を、半導体チップを収納したパッケ
ージ11−1の従来リードを配設する位置および他の任
意の位置に貫通して、そのピン11−2をパッケージ1
1−1の下面より約5鶴突出したり一部1l−2aと、
上面より4fi突出したコネクタ端子1l−2bを形成
する。
As shown in the figure, a thin metal wire 2 with good conductivity is made of, for example, a nickel-plated hard copper wire, with a diameter of 0.2 n and a length of about 12
A pin 11-2 of mm is passed through the conventional lead arrangement position of the package 11-1 containing a semiconductor chip and any other arbitrary position, and the pin 11-2 is inserted into the package 11-1.
Approximately 5 cranes protrude from the bottom surface of 1-1, and some 1l-2a,
Connector terminals 1l-2b are formed that protrude by 4 fi from the top surface.

そして、上記リードを配設する位置に貫通したピン11
−2と図示しない半導体チップとを接続してそのピン1
1−2を信号用および電源用端子とし、他の任意の位置
に貫通したピン11−2は無接続で他のLSillへの
電源および信号供給、信号出力するための端子してコネ
クタの機能を具備したコネクタ端子付きLSillを形
成している。
A pin 11 is inserted through the position where the lead is placed.
-2 and a semiconductor chip (not shown) to connect its pin 1.
1-2 is used as a signal and power supply terminal, and pin 11-2, which passes through any other position, functions as a terminal for supplying power and signals to other LSills and outputting signals without connection. An LSill with a connector terminal is formed.

その実装方法は第2図の斜視図に示すように、基板12
の全主面に上記LSillを指定位置に実装して、一方
の挿入方向側端縁に配列したLSillのコネクタ端子
1l−2bとバックパネル13に配設したコネクタ13
−1を、フラットケーブルの一方に離着工具で低挿脱力
となるケーブルコネクタ14−1を取着して他方にケー
ブルコネクタ14−2を配したケーブル14で接続する
The mounting method is as shown in the perspective view of FIG.
The LSills are mounted at designated positions on the entire main surface of the LSill, and the connector terminals 1l-2b of the LSills are arranged on one edge in the insertion direction, and the connector 13 is arranged on the back panel 13.
-1 is connected by a cable 14 in which a cable connector 14-1 with a low insertion/removal force is attached to one side of the flat cable using a detaching tool, and a cable connector 14-2 is arranged on the other side.

そして、基板の配線回路を必要により修正する場合には
、配線パターンを切断してLSillのそれぞれコネク
タ端子1l−2b間を細い改造ワイヤ16で接続し、前
面側に実装した任意のLSillに配設したコネクタ端
子1l−2bに低挿脱力のケーブルコネクタ14−1を
結合して、ケーブル15で他の図示しないユニットと接
続することにより、基板12の小型化と設計および製造
コストの低減が可能となる。
When modifying the wiring circuit of the board as necessary, cut the wiring pattern, connect the connector terminals 1l-2b of each LSill with a thin modified wire 16, and connect it to any LSill mounted on the front side. By connecting the cable connector 14-1 with a low insertion/removal force to the connector terminal 1l-2b and connecting it to another unit (not shown) using the cable 15, it is possible to downsize the board 12 and reduce design and manufacturing costs. Become.

また、パッケージ11に貫通するピン11−2を、基板
12の配線回路修正に必要な数の改造用端子あるいはG
ND端子だけに限定しても良い。
In addition, the pins 11-2 penetrating the package 11 are connected to the number of modification terminals or G
It may be limited to only the ND terminal.

なお、半導体チップを具備しないパッケージ11にピン
11−2を貫通して、リード1l−2aとコネクタ端子
1l−2bを形成した上記と同一構造のコネクタ端子付
きパッケージを形成することにより、従来と同一機能の
多ピンコネクタとなって実装位置も任意となる。
Note that by forming a package with a connector terminal having the same structure as above in which the pin 11-2 is passed through the package 11 which does not include a semiconductor chip and the leads 1l-2a and the connector terminal 1l-2b are formed, the package 11 is the same as the conventional one. It is a functional multi-pin connector and can be mounted in any position.

つぎに、四方の側面からリードが平らに出るフラットパ
ッケージ、あるいは下面にU字形に形成したリードレス
チップキャリアにおいては、第3図の第2実施例に示す
ように、パッケージ1−1の上面より一定寸法を突出さ
せた導電性の良いコネクタ端子2l−2bを配列し、任
意のコネクタ端子2l−2bと側面より突出したり一部
1−2aとを接続するコネクタ端子付きLSiにおいて
も、上記実装方法により基板の小型化およびコストの低
減が図れる。
Next, in a flat package in which the leads are flat from all four sides, or in a leadless chip carrier formed in a U-shape on the bottom surface, as shown in the second embodiment of FIG. The above mounting method can also be applied to an LSi with a connector terminal in which connector terminals 2l-2b with good conductivity that protrude a certain dimension are arranged and any connector terminal 2l-2b protrudes from the side surface or connects a part 1-2a. This makes it possible to downsize the board and reduce costs.

更に、第4図の第3実施例に示すように、コネクタ部の
クロストーフを防止あるいは減少させるために、信号ピ
ン31−2 aとGNDピン3l−2bを上面視千鳥に
配列して、コネクタ部のクロストーフを防止あるいは減
少させる方法は第1および第2実施例に適用できる。
Furthermore, as shown in the third embodiment of FIG. 4, in order to prevent or reduce crosstorf in the connector section, the signal pins 31-2a and the GND pins 3l-2b are arranged in a staggered manner when viewed from the top. The method for preventing or reducing crosstorf in the parts can be applied to the first and second embodiments.

〔発明の効果〕 以上説明したように本発明によれば極めて簡単な構造の
LSiを使用することにより、コネクタの実装領域とコ
ネクタとLSiの配線領域が減少して基板の小型化が図
れるとともに伝送信号の遅延時間が短縮が可能となり、
且つ設計および製造コストの低減が可能となる等の利点
があり、著しい経済的及び、信軌性向上の効果が期待で
き工業的には極めて有用なものである。
[Effects of the Invention] As explained above, according to the present invention, by using an LSi with an extremely simple structure, the mounting area of the connector and the wiring area between the connector and the LSi are reduced, and the size of the board can be reduced, and the transmission speed can be improved. Signal delay time can be shortened,
It also has the advantage of being able to reduce design and manufacturing costs, and can be expected to have significant economic and reliability effects, making it extremely useful industrially.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第1実施例によるコネクタ端子付きL
Siを示す斜視図、 第2図は本実施例のコネクタ端子付きLSiの実装方法
を示す斜視図、 第3図は第2実施例を示す断面図、 第4図は第3実施例を示す平面図、 第5図は従来のLSiを示す斜視図、 第6図は従来の実装方法を示す斜視図である。 図において、 11はt、s i。 1−1.11−1はパッケージ、 11−2はピン、 1−2a、1l−2aはリード、 11−2 b 、 2l−2bはコネクタ端子、12は
基板、 13はバックパネル 13−1.14−1.14−2はコネクタ、14、15
はケーブル、 16は改造ワイヤ、 3l−2aは信号ピン、 31−2 bはGNDピン、 第1図 第2図 つr2−季一方龜例銘ずrケ面の 第3図 才3の弊地fJを釘平面図 第4図 (Cン            <b)       
    (C)徒車、lLS;色末f糾僅の 第5図 従1突釘法&釘軒硯g 第6図
FIG. 1 shows an L with connector terminals according to a first embodiment of the present invention.
Fig. 2 is a perspective view showing the mounting method of the LSi with connector terminals of this embodiment, Fig. 3 is a sectional view showing the second embodiment, and Fig. 4 is a plan view showing the third embodiment. 5 is a perspective view showing a conventional LSi, and FIG. 6 is a perspective view showing a conventional mounting method. In the figure, 11 is t, s i. 1-1.11-1 is a package, 11-2 is a pin, 1-2a, 1l-2a are leads, 11-2b, 2l-2b are connector terminals, 12 is a board, 13 is a back panel 13-1. 14-1.14-2 is a connector, 14, 15
is the cable, 16 is the modified wire, 3l-2a is the signal pin, 31-2b is the GND pin. Figure 4: Nail fJ plan view (C<b)
(C) Passenger car, lLS; Fig. 5 with a slight color finish.

Claims (3)

【特許請求の範囲】[Claims] (1)半導体チップをパッケージに収納した高密度集積
素子であって、上記パッケージ(11−1)の上面に少
なくとも1個のコネクタ端子(11−2b)を備え、任
意の該コネクタ端子(11−2b)と下面、又は側面に
配設したリード(11−2a)と接続してなることを特
徴とするコネクタ端子付き高密度集積素子。
(1) A high-density integrated device in which a semiconductor chip is housed in a package, which includes at least one connector terminal (11-2b) on the top surface of the package (11-1), and any of the connector terminals (11-2b). 2b) and a lead (11-2a) disposed on the bottom or side surface thereof.A high-density integrated device with a connector terminal.
(2)上記コネクタ端子(11−2b)が、GND端子
と改造用端子で構成されてなることを特徴とする特許請
求の範囲第1項記載のコネクタ端子付き高密度集積素子
(2) A high-density integrated device with a connector terminal according to claim 1, wherein the connector terminal (11-2b) is composed of a GND terminal and a terminal for modification.
(3)上記コネクタ端子(11−2b)の配置が、信号
ピン(31−2a)とGNDピン(31−2b)を千鳥
に配列されてなることを特徴とする特許請求の範囲第1
項記載のコネクタ端子付き高密度集積素子。
(3) The arrangement of the connector terminal (11-2b) is characterized in that the signal pin (31-2a) and the GND pin (31-2b) are arranged in a staggered manner.
High-density integrated device with connector terminals as described in .
JP11976387A 1987-05-15 1987-05-15 High density integrated element with connector terminal Pending JPS63284844A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11976387A JPS63284844A (en) 1987-05-15 1987-05-15 High density integrated element with connector terminal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11976387A JPS63284844A (en) 1987-05-15 1987-05-15 High density integrated element with connector terminal

Publications (1)

Publication Number Publication Date
JPS63284844A true JPS63284844A (en) 1988-11-22

Family

ID=14769575

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11976387A Pending JPS63284844A (en) 1987-05-15 1987-05-15 High density integrated element with connector terminal

Country Status (1)

Country Link
JP (1) JPS63284844A (en)

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