JPS587841A - Mounting device for integrated circuit - Google Patents

Mounting device for integrated circuit

Info

Publication number
JPS587841A
JPS587841A JP56104768A JP10476881A JPS587841A JP S587841 A JPS587841 A JP S587841A JP 56104768 A JP56104768 A JP 56104768A JP 10476881 A JP10476881 A JP 10476881A JP S587841 A JPS587841 A JP S587841A
Authority
JP
Japan
Prior art keywords
terminals
package
integrated circuit
terminal
mounting device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56104768A
Other languages
Japanese (ja)
Inventor
Toshio Kondo
利夫 近藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP56104768A priority Critical patent/JPS587841A/en
Publication of JPS587841A publication Critical patent/JPS587841A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To reduce the size of an integrated circuit mounting device in a package for containing an integrated circuit in which the bottom terminal is inserted into a through hole of a printed circuit board by mutually connecting through terminals provided at the upper surface end or the like, thereby reducing the number of terminals of the bottom surface. CONSTITUTION:A terminal 2 formed on the bottom of a package 1 containing an integrated circuit is inserted and mounted into a through hole of a printed circuit board 4, a terminal 3 is provided also at the upper surface end of each package, and the terminals of the adjacent packages are connected via connecting wires such as flat cables or the like having connectors 6 engaged with the terminals. Since the number of the terminals on the bottom surface can be reduced from the number of the terminals provided on the upper surface, the size of the package can be reduced.

Description

【発明の詳細な説明】 本発明は、多端子の集積回路の実装装置に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a mounting device for a multi-terminal integrated circuit.

大規榔集積回路は、一般に多端子であるため、実装の容
易な１００ミルピツチの標準的なプラグインパッケージ
を用いていたのではパッケージが大きくならざるを得な
いために実装密度が上がらなかった。そこで従来、パッ
ケージに端子ビンを突設しないで、底面に電極のみを配
設するようにしてそのピッチを狭めることによりパッケ
ージの小型化を計るようにしたチップキャリア方式、あ
るいはまたパッケージを用いずに集積回路チップを多数
直接セラミック基板に実装する方式等が試みられてきた
。しかしながらチップキャリア方式は、パッケージと基
板の膨張係数の一致が必要であるため、一般にプラグイ
ン形式の比較的小型なセラミック基板のバッファ°を介
して実装しなければならぬため、実装コストが著しく高
くなるという欠点があった。一方またマルチチップ方式
では、集積回路チップをセラミック基板に搭載した後、
各チップのテストを行なう必要があり、またそのテスト
の結果不良チップであることが明らかになったときの交
換が、ワイヤボンデングしているので極めて困難であっ
た。Since integrated circuits generally have multiple terminals, if a standard plug-in package of 100 mil pitch, which is easy to mount, was used, the package would have to be large, and the packaging density could not be increased. Therefore, conventional chip carrier methods have been used to reduce the size of the package by arranging only electrodes on the bottom of the package and narrowing the pitch without protruding terminal bins from the package, or alternatively, by not using a package. Attempts have been made to directly mount a large number of integrated circuit chips onto a ceramic substrate. However, with the chip carrier method, the expansion coefficients of the package and the board must match, so it must be mounted via a plug-in buffer on a relatively small ceramic board, resulting in extremely high mounting costs. There was a drawback. On the other hand, in the multi-chip method, after mounting an integrated circuit chip on a ceramic substrate,
It is necessary to test each chip, and when the test results reveal that the chip is defective, it is extremely difficult to replace it because wire bonding is used.

本発明は上記゛の点にかんがみ、パッケージとプリント
配線基板に直接実装するものにおいて低いコストで実装
密度を向上し得るようにした集積回路実装装置を提供す
るものであって以下図面について詳細に説明する。In view of the above point, the present invention provides an integrated circuit mounting device that can improve mounting density at low cost in devices that are directly mounted on packages and printed wiring boards. do.

第１図および第２図は本発明の一実施例を示し、１は集
積回路を収容したパッケージであって、プリント配線基
板４上に列設されてお、す、底面にはビン状端子２が縦
横列に配列されると共に上面端縁部にも端子３を列設し
ている。底面から突設の端子２はプリント配線基板４の
プリント配線にそのスルーホールを挿通されて接続され
ている。上面端縁の端子３は隣接するパッケージ１の上
面の対向端縁に突設の端子３と、両端に端子３に嵌合す
るコネクタ６を有するフラットケーブルあるいはフレキ
シブル基板等よシ構成される接続線５によりこれら隣接
するパッケージ間の配線の一部または全部を接続される
。従って上面端縁から突設した端子３の数だけ底面から
の突設端子２の数を減らすことができ、パッケージのサ
イズを小さくできる。1 and 2 show an embodiment of the present invention, in which 1 is a package containing an integrated circuit, which is arranged in rows on a printed wiring board 4, and 2 bottle-shaped terminals 2 on the bottom. are arranged in rows and columns, and terminals 3 are also arranged in rows on the edge of the top surface. The terminal 2 protruding from the bottom surface is connected to the printed wiring of the printed wiring board 4 by being inserted through the through hole. The terminal 3 on the top edge is a connection line made of a flat cable or a flexible board, etc., which has a terminal 3 projecting from the opposite edge of the top surface of the adjacent package 1, and a connector 6 that fits into the terminal 3 at both ends. 5 connects some or all of the wiring between these adjacent packages. Therefore, the number of terminals 2 protruding from the bottom surface can be reduced by the number of terminals 3 protruding from the edge of the top surface, and the size of the package can be reduced.

第６図は他の実施例を示し、この場合はパッケージ１の
底面から突設した端子２の他にパッケージ１の側面より
端子３′を突設し、一方プリント配線基板４表面の各隣
接するパッケージ１．１間に、両端に電極部を形成した
印刷配線７を設け、その電極部に端子３′を折曲し七半
田付は等により接続し、各隣接パッケージの端子３′、
３′同志を接続するようにしたものである。FIG. 6 shows another embodiment, in which in addition to the terminals 2 protruding from the bottom of the package 1, terminals 3' are protruded from the side of the package 1, while each adjacent terminal on the surface of the printed wiring board 4 A printed wiring 7 with electrode parts formed at both ends is provided between the packages 1.1, and a terminal 3' is bent and connected to the electrode part by soldering, etc., and the terminal 3' of each adjacent package is connected.
3' are connected to each other.

上記の各実施例ではパッケージ１をプリント配線基板４
上に横一列に配設した場合について示しだが、パッケー
ジ１を縦横の行列方向に配設した場合は、パッケージ１
の底面以外に設ける端子３゜３′を前後左右に隣接する
各パッケージ側に設け、それらの各隣接対向する側の端
子３あるいはゴ同志を接続するようにしたものにする。In each of the above embodiments, the package 1 is a printed wiring board 4.
The figure above shows the case where packages 1 are arranged horizontally in a row, but if packages 1 are arranged in rows and columns in the vertical and horizontal directions, package 1
Terminals 3.degree. 3' provided on a surface other than the bottom surface of the package are provided on each package side adjacent to each other in the front, rear, left, and right directions, and the terminals 3 or 3' on each adjacent and opposing side are connected to each other.

以上のように本発明によれば、各パッケージの底面と底
面以外の面に端子を配設し、底面突設端子はプリント配
線基板に挿通して該基板の配線に接続し、底面以外の面
から突設の端子間の接続で隣接パッケージ間の配線の一
部または全部を行なうようにしたものであるから、底面
以外の面から突設の端子数だけ底面突設端子数を低減す
るとと　　　　゛ができパッケージの寸法を小さくする
ことができる。また底面突設端子の数を減らせるのでプ
リント配線基板の端子を挿通するスルーホールを経由す
ることが必要なパッケージ間の接続配線数を低減して該
基板の配線のバタンレイアウト設計を容易にすることが
できるので、これらのことから集積回路のプリント配線
基板上への実装密度を極めて容易簡単に従って低いコス
トで向上させることができる。特にアレイプロセッサ用
集積回路のように隣接集積回路間の接続端子数が、それ
以外の数と同程度あるいはそれ以上のものの場合には、
総端子数の５０％程度をパッケージの底面以外の面から
出すことが可能となるので、高密度実装化に著しい効果
を発揮し得る。As described above, according to the present invention, terminals are disposed on the bottom and surfaces other than the bottom of each package, and the terminals protruding from the bottom are inserted into the printed wiring board and connected to the wiring of the board, and the terminals are connected to the wiring on the printed wiring board. Since some or all of the wiring between adjacent packages is performed by connecting terminals protruding from the bottom, it is possible to reduce the number of terminals protruding from the bottom by the number of terminals protruding from surfaces other than the bottom. This allows the package dimensions to be reduced. In addition, since the number of terminals protruding from the bottom can be reduced, the number of interconnections between packages that must pass through through holes for inserting the terminals of the printed wiring board can be reduced, making it easier to design the layout of the wiring on the board. Therefore, it is possible to improve the mounting density of integrated circuits on a printed wiring board extremely easily and at low cost. In particular, when the number of connection terminals between adjacent integrated circuits is equal to or greater than that of other integrated circuits, such as an integrated circuit for an array processor,
Approximately 50% of the total number of terminals can be exposed from surfaces other than the bottom surface of the package, which can have a significant effect on high-density packaging.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例の斜視図、第２図は一部を断
面で示す同側面図、第５図は他の実施例の一部を断面で
示す側面図である。 １・・・パッケージ、２・・・底面突設端子、３，３・
、。 底面以外の面からの突設端子、４・・・プリント配線基
板FIG. 1 is a perspective view of one embodiment of the present invention, FIG. 2 is a partially sectional side view of the same, and FIG. 5 is a partially sectional side view of another embodiment. 1... Package, 2... Bottom protruding terminal, 3, 3.
,. Terminals protruding from surfaces other than the bottom, 4...Printed wiring board

Claims (1)

【特許請求の範囲】[Claims] 集積回路収容の各パッケージの、底面に端子を突設する
と共に底面以外の面にも端子を突設し、これら各パッケ
ージは上記底面突設端子がプリント配線基板に挿通され
該基板の配線に接続されて該基板上に列設され、これら
列設の各隣接パッケージ間の配線の一部あるいは全部を
上記の底面以外の面より突設の互いに対向する端子間で
接続してなる集積回路実装装置。Each package housing an integrated circuit has terminals protruding from the bottom surface as well as terminals protruding from surfaces other than the bottom surface, and the terminals protruding from the bottom surface of each package are inserted into a printed wiring board and connected to the wiring of the board. an integrated circuit mounting device in which a part or all of the wiring between adjacent packages arranged in the row is connected between mutually opposing terminals protruding from a surface other than the bottom surface. .
JP56104768A 1981-07-05 1981-07-05 Mounting device for integrated circuit Pending JPS587841A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56104768A JPS587841A (en) 1981-07-05 1981-07-05 Mounting device for integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56104768A JPS587841A (en) 1981-07-05 1981-07-05 Mounting device for integrated circuit

Publications (1)

Publication Number Publication Date
JPS587841A true JPS587841A (en) 1983-01-17

Family

ID=14389649

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56104768A Pending JPS587841A (en) 1981-07-05 1981-07-05 Mounting device for integrated circuit

Country Status (1)

Country Link
JP (1) JPS587841A (en)

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