JPH06112624A - Surface mounting method - Google Patents

Surface mounting method

Info

Publication number
JPH06112624A
JPH06112624A JP25805892A JP25805892A JPH06112624A JP H06112624 A JPH06112624 A JP H06112624A JP 25805892 A JP25805892 A JP 25805892A JP 25805892 A JP25805892 A JP 25805892A JP H06112624 A JPH06112624 A JP H06112624A
Authority
JP
Japan
Prior art keywords
soj
package
surface mounting
terminal row
mounting method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25805892A
Other languages
Japanese (ja)
Inventor
Masayuki Inoue
雅之 井上
Akinori Sohara
明典 曽原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP25805892A priority Critical patent/JPH06112624A/en
Publication of JPH06112624A publication Critical patent/JPH06112624A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/145Arrangements wherein electric components are disposed between and simultaneously connected to two planar printed circuit boards, e.g. Cordwood modules
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To improve reliability and to realize compactness and a low cost by overlapping and fixing a plurality of packages to have their front and rear faced with each other and by connecting a terminal row exposed in the same direction through one or more printed boards. CONSTITUTION:A module printed board 104 whereto cream solder is applied is prepared for a PAD 103 corresponding to a terminal row 102 on one side of an SOJ (Small Outline J-Lead) package (IC) 101. A Y-axis of the SOJ package (IC) 101 is arranged in a position corresponding to the PAD 103 fitting to a vertical direction of a surface of the module printed board 104. Similarly, a plurality of SOJ packages (IC) 105 to 111 are fixed with the front and the rear thereof overlapping each other in a Z-axis direction. A printed board 113 whereto cream solder is similarly applied is arranged also in another terminal row 112 which is opposite to the terminal row 102 on the one side of the SOJ package. Soldering is carried out by making it pass through a furnace and a module is completed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、表面実装用ICの実装
方法で、特に Small Outline J-Lead (以下、SOJと
称す)および Plastic Lead Chip Carrier (以下、PL
CCと称す)と呼ばれるパッケージの表面実装方法に関
するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting an IC for surface mounting, particularly Small Outline J-Lead (hereinafter referred to as SOJ) and Plastic Lead Chip Carrier (hereinafter referred to as PL).
The present invention relates to a surface mounting method of a package called CC).

【0002】[0002]

【従来の技術】図5は、従来の表面実装用ICの実装方
法の一例を示したものである。表面実装は一般的に、図
5に示すような形で実装される。すなわち基板301表面
に対してICパッケージ302〜309の表面(通常メーカー
の捺印が施してある面)を上にして実装される。ここで
はSOJパッケージの例を示している。同様の実装方法
がPLCC等の、所謂表面実装ICで行われる。このI
Cパッケージ302〜309およびこの実装方法は、これらI
Cパッケージ302〜309を使用する電子機器の小型化を進
めるには非常に重要な、かつ有用なやり方である。すな
わち、パッケージそのものも小型化しており、またDI
P(Dual Inline Package)ICに比べ基板の両面にIC
を実装することができ、基板の小型化にさらに貢献でき
る。
2. Description of the Related Art FIG. 5 shows an example of a conventional surface mounting IC mounting method. Surface mounting is generally implemented as shown in FIG. That is, the IC packages 302 to 309 are mounted with the surface (the surface on which the manufacturer's marking is applied) facing upward with respect to the surface of the substrate 301. Here, an example of the SOJ package is shown. A similar mounting method is performed by a so-called surface mount IC such as PLCC. This I
The C packages 302 to 309 and this mounting method are
This is a very important and useful way to miniaturize electronic devices using the C packages 302 to 309. In other words, the package itself has become smaller, and the DI
ICs on both sides of the board compared to P (Dual Inline Package) ICs
Can be mounted, which can further contribute to downsizing of the board.

【0003】この方法を使用している典型的な例として
パーソナルコンピュータやワークステーション等に使用
されるDRAM(Dynamic RAM)モジュールが提案されて
いる。この方法を用いることで、ICの実装に関して従
来DIPIC(Dual InlinePackage IC)を使用する場合
に比べ、基板の両面を使用することができ、約半分の基
板面積で基板作成が可能である。
As a typical example of using this method, a DRAM (Dynamic RAM) module used in a personal computer, a workstation, etc. has been proposed. By using this method, both sides of the substrate can be used as compared with the case where a conventional DIPIC (Dual Inline Package IC) is used for mounting the IC, and the substrate can be formed with about half the substrate area.

【0004】しかし、従来はこれが限界でDIPICの
半分以上の基板面積削減が望めない。そこで提案されて
いるのが、MCM(Multi Chip Module)法である。MC
Mは図6に示すような形状をしており、これは1パッケ
ージ401内に複数のベアチップ 402〜405と呼ばれる所謂
ICチップそのものを複数実装し、ミクロンオーダのパ
ターン406をパッケージ内のセラミック基板407上に引く
ことにより、今まで複数のパッケージを実装していたI
Cチップを、一つのパッケージにまとめ基板面積を小さ
くするという技術である。しかしこの方法は、まだ研究
段階であり、実使用上、パッケージ信頼性,コスト等ま
だまだ解決すべき問題が多数ある。
However, in the past, this is the limit, and it is not possible to expect a reduction in the substrate area more than half that of the DIPIC. Therefore, the MCM (Multi Chip Module) method is proposed. MC
The M has a shape as shown in FIG. 6, in which a plurality of so-called IC chips called bare chips 402 to 405 are mounted in one package 401, and a micron-order pattern 406 is formed on a ceramic substrate 407 in the package. By pulling up, I have implemented multiple packages until now. I
This is a technique for reducing the substrate area by combining C chips into one package. However, this method is still in the research stage, and in practical use, there are still many problems to be solved such as package reliability and cost.

【0005】[0005]

【発明が解決しようとする課題】しかしながら上記した
ように、現状の技術ではせいぜい従来のDIPICで作
成していた基板の面積の半分程度の大きさまでしか小さ
くならず、更なる小型化が望まれているが、それに対し
有効かつ簡単に実現できる方法はいまだない。本発明
は、上記従来の問題を解決するものであり、信頼性が高
く小型で低コストの表面実装方法を提供することを目的
とするものである。
However, as described above, in the present technology, the size of the substrate can be reduced to about half of the area of the substrate formed by the conventional DIPIC, and further miniaturization is desired. However, there is still no effective and easy way to achieve it. The present invention solves the above conventional problems, and an object of the present invention is to provide a highly reliable, compact, and low-cost surface mounting method.

【0006】[0006]

【課題を解決するための手段】本発明は上記目的を達成
するために、PLCCおよびSOJパッケージについて
のみであるが、複数のパッケージを表面(通常メーカー
の捺印がある側)とその裏側とを重ねて固定し、同一方
向に出ている端子列(SOJの場合二辺、PLCCの場
合四辺)を1枚以上のプリント基板でつなぐ(以下、つな
いだ状態をモジュールと呼ぶ)実装方法を使用する。モ
ジュールの各プリント基板(SOJの場合2枚、PLC
Cの場合4枚)からは他の基板と接続するためのカード
エッジ状もしくはピン状の端子があり、それを利用して
他の基板に実装するようにしたものである。
In order to achieve the above-mentioned object, the present invention is only for PLCC and SOJ packages, but a plurality of packages are superposed on the surface (the side having the marking of the manufacturer) and the back side thereof. A mounting method is used in which terminal rows (two sides in the case of SOJ, four sides in the case of PLCC) that are exposed in the same direction are connected by one or more printed circuit boards (hereinafter, the connected state is called a module). Each printed circuit board of the module (2 sheets for SOJ, PLC
There are card-edge-shaped or pin-shaped terminals for connecting to another board from 4) in the case of C), and these terminals are used to mount on another board.

【0007】[0007]

【実施例】本発明の一実施例であるSOJの実装方法に
ついて、図1,2を用いて説明する。まず、座標軸を明
確にするために図2のような形で方向を決める。すなわ
ち、一辺の端子列方向をX軸、相対する端子列への法線
方向をY軸、X軸とY軸に垂直な方向をZ軸とする。
EXAMPLE An SOJ mounting method according to an example of the present invention will be described with reference to FIGS. First, in order to clarify the coordinate axes, the direction is determined in the form as shown in FIG. That is, the terminal row direction of one side is the X axis, the normal direction to the opposing terminal row is the Y axis, and the direction perpendicular to the X axis and the Y axis is the Z axis.

【0008】図1でさらに詳細に本発明の内容を示す。
ここで101,105〜111はICのSOJパッケージを示
し、102,112はSOJパッケージ(IC)101の端子列(S
OJパッケージ一辺の端子列)、103は端子列102に対応
したプリント基板上の配線パターン(通常PADと呼ば
れ、以下PADと称す)であり、104,113はPAD103や
基板配線パターン117,118を含むモジュール用プリント
基板である。また、119,120はモジュール用プリント基
板104,113を他の基板116とを繋ぐために配置されてい
るピンタイプの端子群114,115に対応した穴(通常ラン
ドと呼ばれ、以下ランドと称す)である。ピンタイプの
端子群114,115とPAD103等は配線パターン117,118
で電気的に接続されている。
FIG. 1 shows the content of the present invention in more detail.
Here, 101, 105 to 111 are IC SOJ packages, and 102 and 112 are terminal arrays (S) of the SOJ package (IC) 101.
OJ package one side terminal row), 103 is a wiring pattern (usually referred to as PAD, hereinafter referred to as PAD) on the printed circuit board corresponding to the terminal row 102, 104 and 113 are the PAD 103 and the board wiring patterns 117 and 118. It is a printed circuit board for modules including. 119 and 120 are holes corresponding to pin type terminal groups 114 and 115 arranged to connect the module printed circuit boards 104 and 113 to another board 116 (usually called lands, hereinafter referred to as lands). ). The pin-type terminal groups 114 and 115 and the PAD 103 and the like have wiring patterns 117 and 118.
It is electrically connected with.

【0009】まずSOJパッケージ(IC)101の一辺の
端子列102(図1ではSOJパッケージ101の向う側)に対
応したPAD103にクリーム半田を塗布したモジュール
用プリント基板104を用意し、PAD103に対応した位置
にSOJパッケージ(IC)101のY軸をモジュール用プ
リント基板104の面に垂直方向に合わせて配置する。同
様に複数のSOJパッケージ(IC)105〜111までを、各
々のSOJパッケージ(IC)101,105〜111表面(通常メ
ーカーの捺印がある側)とその裏側とを、つまりZ軸方
向に重ねて固定する。さらにSOJパッケージの一辺の
端子列102に相対するもう一方の端子列112(SOJパッ
ケージの一辺の端子列)にも、同様にクリーム半田を塗
布したプリント基板113を配置し、これを炉に通すこと
で半田付けを行い、モジュールが完成する。このモジュ
ール用プリント基板104,113の端には、パターンエッジ
タイプの端子群、もしくはピンタイプの端子群114,115
が用意されており、他の基板116とランド119,120を利
用して容易に接続可能となっている。
First, a module printed circuit board 104 is prepared by applying cream solder to a PAD 103 corresponding to a terminal row 102 (on the side opposite to the SOJ package 101 in FIG. 1) on one side of the SOJ package (IC) 101, and a position corresponding to the PAD 103 is prepared. Then, the Y axis of the SOJ package (IC) 101 is aligned with the surface of the module printed board 104 in the vertical direction. Similarly, a plurality of SOJ packages (IC) 105 to 111 are superposed on the surface of each SOJ package (IC) 101, 105 to 111 (the side on which the manufacturer's marking is provided) and the back side thereof, that is, in the Z-axis direction. Fix it. Further, a printed circuit board 113 to which cream solder is similarly applied is arranged also on the other terminal row 112 (terminal row on one side of the SOJ package) facing the terminal row 102 on one side of the SOJ package, and this is passed through a furnace. Solder to complete the module. Pattern edge type terminal groups or pin type terminal groups 114, 115 are provided at the ends of the module printed circuit boards 104, 113.
Are prepared and can be easily connected to each other by using another board 116 and lands 119 and 120.

【0010】さらに、各SOJパッケージICの間隔を
開けることで、換気により冷却効果が上がることは明白
である。なお、実施例ではSOJパッケージICについ
て述べたが、本発明は図3に示すようなPLCCパッケ
ージICについても、同様の効果があることは明白であ
る。このような構成のモジュールを用いれば、他の基板
116の面積を大幅に削減できる。本実施例では、他の基
板116のSOJパッケージ(IC)101の部分において約1
/7の基板面積の削減が実施できた(図4に図示)。
Further, it is apparent that the cooling effect is enhanced by ventilation by opening the spaces between the SOJ package ICs. Although the SOJ package IC has been described in the embodiment, it is obvious that the present invention has the same effect also in the PLCC package IC as shown in FIG. If you use a module with such a configuration,
The area of 116 can be reduced significantly. In this embodiment, about 1 in the SOJ package (IC) 101 portion of the other substrate 116.
The substrate area was reduced by / 7 (illustrated in FIG. 4).

【0011】[0011]

【発明の効果】今回の発明での実施例においては、PL
CCおよびSOJパッケージについてのみであるが、チ
ップを重ねて固定し、端子部分を基板でつなぎ、その基
板からメイン基板と接続するための端子を用い、三次元
的に実装する手段を用いることにより、SOJ部分のみ
の基板面積を1/7程度小さくすることができるという
効果を有する。
In the embodiment of the present invention, the PL
As for the CC and SOJ packages only, by stacking and fixing the chips, connecting the terminal portions with the substrate, using terminals for connecting the substrate to the main substrate, and using a means for three-dimensionally mounting, The effect is that the substrate area of only the SOJ portion can be reduced by about 1/7.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例における表面実装方法を用い
た基板の分解斜視図である。
FIG. 1 is an exploded perspective view of a substrate using a surface mounting method according to an embodiment of the present invention.

【図2】SOJパッケージの方向を示す図である。FIG. 2 is a diagram showing a direction of an SOJ package.

【図3】本発明をPLCCパッケージに適応した実施例
を示した図である。
FIG. 3 is a diagram showing an embodiment in which the present invention is applied to a PLCC package.

【図4】本発明の一実施例の実装方法と、従来の実装方
法と従来のモジュール方式での実装方法での基板占有面
積の違いを示した図である。
FIG. 4 is a diagram showing a difference in board occupying area between a mounting method according to an embodiment of the present invention, a conventional mounting method, and a conventional module-type mounting method.

【図5】従来のDRAMモジュールを示す図である。FIG. 5 is a diagram showing a conventional DRAM module.

【図6】従来のマルチチップモジュール(MCM)を示す
図である。
FIG. 6 is a diagram showing a conventional multi-chip module (MCM).

【符号の説明】[Explanation of symbols]

101,105〜111…SOJパッケージ、 102,112…SO
Jパッケージの一辺の端子列、 103…プリント基板上
の配線パターン(PAD)、 104,113…モジュール用プ
リント基板、114,115…ピンタイプの端子群、 116…
他の基板、 117,118…基板配線パターン、 119,120
…穴(ランド)、 301…基板、 302〜309…ICパッケ
ージ、 401…パッケージ、 402〜405…ベアチップ、
406…パターン、 407…セラミック基板。
101,105-111 ... SOJ package, 102,112 ... SO
Terminal line on one side of J package, 103 ... Wiring pattern (PAD) on printed circuit board, 104, 113 ... Module printed circuit board, 114, 115 ... Pin type terminal group, 116 ...
Other boards, 117, 118 ... Board wiring patterns, 119, 120
… Hole (land), 301… Substrate, 302-309… IC package, 401… Package, 402–405… Bare chip,
406 ... Pattern, 407 ... Ceramic substrate.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 表面実装用集積回路(表面実装用IC)の
表面実装方法であって、該ICの両側面にある全端子と
接する面をXY面とし、その垂直方向をZ軸とすると、
該ICを実装する少なくとも一枚以上のプリント基板は
一辺の端子列に全て接触し、かつZ軸に平行に配置さ
れ、残りの一つまたは三つの端子列にも各々少なくとも
一枚以上のプリント基板をZ軸に平行に配し、該ICの
表(XY平面であり、かつ通常メーカーの捺印がある面)
と裏を重ね合わせた形状で該IC群を実装することを特
徴とする表面実装方法。
1. A surface mounting method for a surface mounting integrated circuit (IC for surface mounting), wherein a surface in contact with all terminals on both side surfaces of the IC is an XY plane, and a direction perpendicular to the XY plane is Z axis.
At least one or more printed circuit boards on which the ICs are mounted are all in contact with the terminal row on one side and arranged parallel to the Z-axis, and at least one or more printed circuit boards are provided for the remaining one or three terminal rows. Is arranged parallel to the Z-axis, and the front side of the IC (the XY plane and the surface with the marking of the manufacturer)
A surface mounting method, wherein the IC group is mounted in a shape in which the back and the back are overlapped.
【請求項2】 前記プリント基板は、他の基板に実装で
きるように、カードエッジ状もしくはピン状に端子が配
されていることを特徴とする請求項1記載の表面実装方
法。
2. The surface mounting method according to claim 1, wherein the printed circuit board has terminals arranged in a card edge shape or a pin shape so as to be mounted on another board.
【請求項3】 換気のために前記IC群の間隔を開けた
ことを特徴とする請求項1記載の表面実装方法。
3. The surface mounting method according to claim 1, wherein an interval between the IC groups is opened for ventilation.
JP25805892A 1992-09-28 1992-09-28 Surface mounting method Pending JPH06112624A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25805892A JPH06112624A (en) 1992-09-28 1992-09-28 Surface mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25805892A JPH06112624A (en) 1992-09-28 1992-09-28 Surface mounting method

Publications (1)

Publication Number Publication Date
JPH06112624A true JPH06112624A (en) 1994-04-22

Family

ID=17314953

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25805892A Pending JPH06112624A (en) 1992-09-28 1992-09-28 Surface mounting method

Country Status (1)

Country Link
JP (1) JPH06112624A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0729753A1 (en) * 1995-02-01 1996-09-04 Suntory Limited Agents for treatment or prevention of hypertension and related symptons and disorders; their preparation and use

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0729753A1 (en) * 1995-02-01 1996-09-04 Suntory Limited Agents for treatment or prevention of hypertension and related symptons and disorders; their preparation and use

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