JPS63281070A - Continuity test system - Google Patents

Abstract

PURPOSE:To test all kinds of terminal interface (I/F) cards which appear newly by providing a dedicated detector corresponding to a dedicated test signal generator in a terminal interface I/F card. CONSTITUTION:A common-use pattern generator 17 outputs a common-use pattern signal to the I/F card 2 under the command of a central arithmetic unit 5. Similarly, the dedicated test signal generator 26 generates a test signal under the command of the central arithmetic device 5 and internal circuits 13 and 14 of the I/F card 2 are energized on with the test signal to perform detection by a dedicated detector 27. A gate circuit 29 is controlled with the detection signal and the common-use pattern signal is returned to the side of a test card 4 and detected by the common-use pattern detector 17. Then the continuity between transmission lines 11 and 12 between the card 4 and I/F card 2 and internal circuits 13 and 14 in the interface is tested. Consequently, all kinds of terminal I/F cards which appear newly are tested.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention is a continuity test method for terminal interface (I/F) cards such as voice terminals and data terminals [Prior Art] Continuity test is shown in Figure 4.

This is done using the method shown in FIG. That is, in Fig. 4, 1 is the pass line, 2 is the terminal 1/F card, 3 is the terminal,
4 is a test (TEST) card, and 5 is a control central processing unit (hereinafter referred to as CPU).

A plurality of terminal 1/F cards 2 2a to 2n are provided, and corresponding terminals 3a to 3n are connected to each terminal 1/F card 2.

For example, the terminal 3a is a voice terminal, and the terminal 3n is a data terminal. Therefore, terminal I/F card 2a and terminal 1/
The F cards 2n have different data formats and different hardware configurations.

A test signal generator 6 and a detector 7 are provided in the test card 4, and each terminal I/F card 2 is connected to the path line 1 by a bus.

Next, the operation will be explained.

First, to conduct a continuity test on the terminal 1/F card 2a for audio terminals, the test signal generator 6 of the test card 4 generates two audible frequencies according to a test instruction from the CPU 5, and performs predetermined modulation processing. and transmits it to the terminal I/F card 2a. Also, according to the RLB instruction from CPU5,
The terminal 1/F card 2a forms a closed circuit that connects its own internal circuits in series. Next, the test signal from the test signal generator 6 passes through an internal circuit in the terminal 1/F card 2a, is turned back, and is received by the detector 7 of the test card 4. Here, depending on whether the transmitted signal and the received signal match, it is determined whether the continuity function of the terminal 1/F card 2a is good or bad, and the result is notified to the CPU 5.

On the other hand, to test the data terminal 1/F card 2n,
Digital data is then generated from the test signal generator 6, and a returned signal is detected by the detector 7 to determine whether the signals match or do not match.

FIG. 5 shows the configuration of a terminal 1/F power continuity test in a remote system, in which 10a and 10b are line interfaces (hereinafter referred to as CT cards), and 11 is a transmission line such as a high-speed digital line.

The CPU 5 in station y is connected to a terminal in remote station Z via CT cards 10a, 10b and transmission line 11! The CPU 8 in station Z is instructed to return the /F card 2a by an RLB request, and a test is performed in the same manner as above.

[Problem that the invention seeks to solve]

In the conventional test method, test signals to be transmitted from the test card are selected and transmitted depending on the type of terminal I/F card. There are various types of terminal ■/F cards with different data formats, such as synchronous data terminal I/F cards, start-stop data terminal I/F cards, and 32
These include a Kbps audio terminal 1/F card, a terminal 1/F card, and a 16 Kbps audio terminal 1/F card. Therefore, the test signal must be prepared accordingly on the test card side. The conventional test method has the disadvantage that the test card must be provided with a signal generator for all these terminal I/F cards, making the circuit large and expensive. Furthermore, it is difficult and impossible to increase the circuit configuration in the test card every time a new terminal I/F card appears. Although there is a method of increasing the number of test cards themselves, there is a limit to this method due to the limited capacity of the housing, and there is also the problem of high costs.

This invention was made in view of the above circumstances, and even if a terminal 1/F card with a new function appears, there is no need to construct a new circuit to handle the test card, and there is no need to increase the number of test cards themselves. The purpose is to provide a continuity test method that can test all types of terminal I/F cards.

[Means for solving problems]

In this invention, a central processing unit 5 for control, a test card 4 for conducting a continuity test, a common pattern generator 17 and a common pattern detector 16 provided in this test card 4 are provided.
, a terminal interface card 2 on the side to be tested for continuity, and a gate to which outputs from a dedicated test signal generator 26 in a predetermined data format, a dedicated detector 27, and a common pattern generator 17 provided in this interface card 2 are provided. A circuit 29 outputs a common pattern signal from the common pattern generator 17 to the interface card 2 in response to a command from the central processing unit 5, and the central processing unit 5
A test signal is generated from the dedicated test signal generator 26 according to a command from the interface card 2, and this test signal is energized to the internal circuit 13.14 of the interface card 2 to output the test signal to the dedicated detector 2.
7, and this detection signal controls the gate circuit 29 to return the common pattern signal to the test card 4 side, where it is detected by the common pattern detector 17, and the transmission line 11 between the test card 4 and the interface card 2 is detected. 12 and internal circuits 13 and 14 in the interface were tested for energization.

In another aspect of the present invention, the test card 4 and the main central processing unit 5 are provided on the main station side y, and the interface card 2 and the slave central processing unit 8 are provided on the other station side Z connected by the transmission path 11. A power supply test is carried out with the interface card 2 in the partner station Z via the transmission line 11 in response to a command from the main central processing unit 5.

[Effect]

Dedicated test signal generators 26 and corresponding dedicated detectors 2 are provided in the interface cards 2 with different data formats, respectively.
7 in advance, the internal energization test inside the interface card 2 is self-diagnosed, and if the energization result is normal, the common pattern signal is returned by the gate circuit 29, and the continuity test of the transmission path is performed on the test card side. The test was conducted independently in two stages.

In addition, in this invention, the interface card 2 of the partner station 2 located at a remote location from the main station y is tested for continuity by a remote command, and the energization test via the transmission line 11 is also performed.

〔Example〕

The present invention will be explained below based on the drawings. FIG. 1 is a diagram showing an embodiment of the continuity test method of the present invention. In the figure, 1 is a pass line, 2 is a terminal 1/F card, 3 is a terminal, 4 is a test (TEST) card, 5 is a central processing unit (CPU5), and 10 is a line interface card (CT card). The terminal I/F card 2 is connected to the pass line 1 via a bus 12. The terminal 1/F cards 2 to be tested for continuity are various terminal 1/F cards 2a to 2n.
These are connected to corresponding various terminals 3a to 3n, respectively. Here, the terminal 3a is, for example, an audio terminal, and the terminal 3n is a data terminal, and their hardware configurations are different. Therefore, the corresponding terminal I/F card 2a and terminal I/F card 2n have different hardware configurations. Each terminal I/F card 2 is connected to the path line 1 via a bus 12, respectively.

The test card 4 is provided with a common pattern generator 7 and a common pattern detector 6 as common test signals, and 20 and 21 are unidirectional buffer gates. C.P.
U5 controls opening and closing of these buffers 20 and 21, and also controls the operation of the test card 4. On the other hand, the audio terminal ■/F card 2a includes a transmission processing section 13 and a reception processing section 14. Selector switch 31.32.33゜3
4 internal circuits are provided.

Further, a test signal generator 26 dedicated to audio and a detector 37 dedicated to the test signal generator 26 are provided in the terminal T/F card 2a.

The selector switch 33 selectively switches between the test signal generator 26 and the audio terminal 3a and connects them to the transmission processing section 13 according to a command from the CPU 5. Selector switch 34
In response to a command from the CPU 5, the detector 27 and the terminal 3a are selectively switched and connected to the reception processing section 14.

22, 23, 24, and 25 are unidirectional puffer gates, and between the transmission processing section 13 and the buffer gate 22 there are three selector switches, and between the reception processing section 14 and the buffer gate 23 there are three selector switches. A selector switch 32 is provided respectively. The selector switch 32 selectively switches between the buffer gate 23 and the transmission processing section 13 and connects it to the reception processing section 14 . 29 is an AND gate serving as a gate circuit, to which the test OK signal of the dedicated detector 27 is input as gate control, and the signal from the common pattern generator 17 is given as the other input. The selector switch 31 consists of two select sections, one of which selectively switches between the reception processing section 14 and the buffer gate 22 and is connected to the transmission processing section 13. The other select section selectively switches the AND gate 29 and the transmission processing section 13 to select the bus 12. It is connected to the shared pattern detector 16 via the pass line 1.

Reference numeral 10 is a CT card for communication control, which is connected to a transmission path such as a high-speed digital line. Similarly, the data terminal 1/F card 2n includes a transmission processing section 13. Reception processing unit 1
4. Unidirectional buffers 22 to 25, selector switch 31
~34. A circuit corresponding to the AND gate 29 is provided, and in this case, a test signal generator dedicated to digital data and a corresponding dedicated detector are provided. In this way, there are various terminals with dedicated test signal generators and corresponding dedicated detectors according to their functions and types! /F card is provided in advance.

Next, the operation will be explained.

The CPU 5 instructs the test card 4 to notify the test target card address and to start the test. Then, the common pattern generator 17 sends a common PN pattern for all 1/F cards to the target terminal I/F card via the buffer gate 21.
Output to the F card 2a.

Next, the CPU 5 issues a return test instruction to the terminal I/F card 2a. Based on this instruction, the selector switch 33 first selects the dedicated test signal generator 26, and from there the two audible frequencies are modulated for the test. The signal is given to the transmission processing section 13. Then, the two circuits of the selector switch 31 select another selector switch 32 and the AND gate 29, respectively, and the selector switch 32 selects the transmission processing section 13, so the test signal is given to the reception processing section 14, and a predetermined reception processing is performed. will be held. Next, the selector switch 34 selects the dedicated detector 27, and the test signal after receiving processing is applied to the dedicated detector 27. Here, it is determined whether the test signal output from the dedicated test signal generator 26 and the input test signal match, and if they match, a test OK signal is given to the AND gate 29.

The AND gate is opened by this OK signal, the PN pattern signal passes through the antgelt 29, and the selector switch 31. Buffer gate 22. It is provided to a shared pattern detector 16 within test card 4 via bus 12 and spreader gate 20.

In the common pattern detector 16, when the transmitted PN pattern signal returns,
It is checked to see if it matches the PN pattern signal transmitted from the shared pattern generator 17, and if there is no error, the test result is determined to be normal and the CPU 5 is notified. If there is an error or the PN pattern signal does not return from the terminal I/F card 2a within a certain period of time, the test result is notified to the CPU 5 as an error.

Next, the CPU 5 reads the test result from the test card 4, performs analysis processing, and issues a return test cancellation instruction to the terminal 1/F card 2a. Then the selector switch 31,
32.33.34 corresponds to buffer gate 22.23
, 24, and 25, respectively, and the terminal 3a is connected to the Tejas line 1 via the terminal I/F card 2a. Also CPU5
gives a test cancellation instruction to the test card 4, stops generation of the PN pattern, and ends the test of one channel.

Next, when performing a return test on the data terminal 1/F card 2n, it is performed in the same manner as described above, but in this case, the dedicated test signal generator in the terminal 1/F card generates digital data,
The dedicated detector performs uninterrupted detection of digital data. Of course, the CPU 5 and the test card 4 are exactly the same, and the terminals 1/1 with different functions and data formats are used.
Testing is also possible with F card 2n.

FIG. 2 shows a general form of loopback test of the local terminal I/F card, in which the CPU 5 issues a test instruction to the test card 4 and a loopback test instruction to the terminal 1/F card 2. If the self-diagnosis is OK, the AND gate 29 is opened, the PN pattern passes through the AND gate 29, a match is detected by the shared pattern detector 16, and the CPU 5 is notified of the normal (abnormal) test result.

FIG. 3 shows an embodiment of the remote loopback test of the present invention. The test card 4 on the command side of the main station y is a target terminal I/F card 2b for testing that is connected to the CT card 10 of the remote partner station Z via the CT card 10a and a transmission line 11 such as a high-speed digital line. Also, the main CPU on the command side
5 and the slave CPU 8 on the target terminal 1/F card 2 side are connected via a transmission path 11, respectively. Therefore, the main CPU5
gives a test instruction to the test card 4 of the master station y and the slave CPU 5b of the partner station y, and the slave CPU 8 of the partner station tests the target terminal 1/
A return test instruction is given to F card 2. Target device 1/
If the self-diagnosis of the F card 2 is OK, the AND gate 29 opens, and the PN pattern transmitted from the command side y through the transmission line 11 is turned back by the AND gate 29, and the common pattern detector 16 on the command side detects an error and a mismatch. Detected. In this way, the various terminal 1/F cards of the partner station Z can be easily tested remotely from the main station, and their states can be inspected. In this way, continuity/operation tests within the terminal 1/F card and continuity tests including pass lines and transmission line circuits can be accurately and easily performed. Remote terminal I/
The effort and time required to test the F card is reduced, and costs can be reduced.

〔Effect of the invention〕

As explained above, according to the present invention, there is provided a central processing unit for control, a test card for conducting a continuity test, a common pattern generator and a common pattern detector provided in this test card, and a test card for conducting a continuity test. It is equipped with a terminal interface card, a dedicated test signal generator in a predetermined data format provided in this interface card, a dedicated detector, and a gate circuit to which outputs from the common pattern generator are given, and which is equipped with A common pattern signal is output from the common pattern generator to the interface card, a test signal is generated from the dedicated test signal generator based on a command from the central processing unit, and this test signal is used to energize the internal circuit of the interface card. The detection signal is detected by the detector, and the gate circuit is controlled by this detection signal, and the common pattern signal is returned to the test card side.The common pattern signal is detected by the common pattern detector, and the internal circuit in the transmission path and interface between the test card and the interface card is detected. Since the current continuity test is performed, the continuity test can be performed using the same test card even for interface cards with various data formats.

Even if an interface card with a new function appears, it can be tested using the same test card, reducing costs. Furthermore, each interface card is equipped with a self-diagnosis function, which enables early detection of failures and improves system availability.

In another aspect of the present invention, the test card 4 and the main central processing unit 5 are provided on the main station side y, and the interface card 2 and the slave central processing unit 8 are provided on the other station side Z connected by the transmission path 11. Since the energization test of the interface card 2 is performed via the transmission line 11 in response to a command from the main central processing unit 5, the energization test of the transmission line 11 can also be performed, and there is no need to go out of your way to travel to a remote location. It becomes possible to perform a power supply test on the interface card 2 of the partner station Z without any trouble, which is convenient and also enables diagnostic management of equipment including the partner station side. Therefore, there is no need for an operator to go to a remote station, further increasing the cost reduction benefits.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a continuity test device to which the present invention is applied, FIG. 2 is a block diagram showing the local test operation of the present invention, and FIG. 3 is a block diagram showing the remote operation of the present invention.
FIG. 4 is a professional vine diagram of a conventional continuity test device, and FIG. 5 is a block diagram showing a conventional remote operation. 2...Terminal interface card, 3...Terminal,
4...Test card, 5.8...CPU, 10...
・CT card, 11... Transmission line, 13.14... Internal circuit, 16... Shared pattern detector, 17... Shared pattern generator, 26... Dedicated test signal generator,
27... Dedicated detector, 29... AND circuit. Agent: Masu Oiwa A (and 2 other people) Procedural amendments: Procedural amendment, Showa year, month, day, continuity test method 3, relationship with the case of the person making the amendment Patent applicant address: 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Moriya Shiki 4, Agent Address 2-2-3-5 Marunouchi, Chiyoda-ku, Tokyo
, the entire text of the specification to be amended. 6. Contents of amendment The entire text of the specification will be amended as shown in the attached sheet. The above specification (Konushi 11-1, name of the invention, continuity test method 2, scope of claims (1), central processing unit for control, test card for conducting continuity test, and common pattern provided in this test card) A generator and a common pattern detector, a terminal interface card for continuity testing, a dedicated test signal generator in a predetermined data format provided in this interface card, and outputs from the dedicated detector and the common pattern generator. outputting a common pattern signal from the common pattern generator to the interface card according to a command from the central processing unit, and outputting a test signal from the dedicated test signal generator according to a command from the central processing unit. A signal is generated, this test signal is detected by the dedicated detector by energizing the internal circuit of the interface card, and the detection signal controls the gate circuit to return the common pattern signal to the test card. Continuity test method that detects with a common pattern detector and tests the transmission line between the test card and the interface card and the internal circuit in the interface. (2) Main central processing unit for control provided on the main station side. A test card that performs a continuity test with the device, a common pattern generator and a common pattern detector provided in this test card, and a control device provided on the partner station side connected to the main station via a transmission path. A secondary central processing unit and a terminal interface card for continuity testing, a dedicated test signal generator in a predetermined data format provided in this interface card, a dedicated detector, and a gate circuit that is gate-controlled by the output of this dedicated detector. outputting a common pattern signal from the common pattern generator in response to a command from the main central processing unit, inputting this common pattern signal to the gate circuit of the interface card via the transmission path, and A test signal is generated from the dedicated test signal generator based on a command given from the central processing unit to the slave central processing unit via the transmission path, and the test signal is energized in the internal circuit of the interface card to The detection signal is used to control the gate circuit to return the common pattern signal to the test card via the transmission path, the returned common pattern signal is detected by the common pattern detector, and the common pattern signal is detected by the common pattern detector. A continuity test method in which a transmission line between a test card on the main station side and an interface card on the partner station side and a conduction test in the interface card are conducted. 3. Detailed description of the invention [Industrial application field] This invention is a continuity test method for terminal interface (1/F) cards such as voice terminals and data terminals [Prior art] Continuity test is shown in Figure 4. This is done using the method shown in FIG. That is, in FIG. 4, 1 is a pass line, 2 is a terminal I/F card, 3 is a terminal,
4 is a test (TEST) card, and 5 is a control central processing unit (hereinafter referred to as CPU). A plurality of terminal 1/F cards 2 2a to 2n are provided, and corresponding terminals 3a to 3n are connected to each terminal 1/F card 2. For example, the terminal 3a is a voice terminal, and the terminal 3n is a data terminal. Therefore, terminal 1/F card 2a and terminal I/F card 2a
The F cards 2n have different data formats and different hardware configurations. A test signal generator 6 and a detector 7 are provided in the test card 4, and each terminal I/F card 2 is connected to the path line 1 by a bus. Next, the operation will be explained. First, in order to perform a continuity test on the terminal I/F card 2a for an audio terminal, the test signal generator 6 of the test card 4 generates two audible frequencies according to a test instruction from the CPU 5, and performs predetermined modulation processing. and transmits it to the terminal I/F card 2a. Also, according to the RLB instruction from CPU5,
The terminal 1/F card 2a forms a closed circuit that connects its own internal circuits in series. Next, the test signal from the test signal generator 6 passes through an internal circuit in the terminal 1/F card 2a, is turned back, and is received by the detector 7 of the test card 4. Here, depending on whether the transmitted signal and the received signal match, it is determined whether the continuity function of the terminal I/F card 2a is good or bad, and the result is notified to the CPU 5. On the other hand, to test the data terminal 1/F card 2n,
Digital data is then generated from the test signal generator 6, and a returned signal is detected by the detector 7 to determine whether the signals match or do not match. FIG. 5 shows the configuration of a terminal 1/F power continuity test in a remote system, in which 10a and 10b are line interface cards (hereinafter referred to as CT cards), and 11 is a transmission line such as a high-speed digital line. The CPU 5 in station Y is a CT card 10a. 10b and the terminal 1/ at the remote station Z via the transmission line 11.
F card 2a is returned to C in station Z by RLB request.
Instruct the PU8 and perform the test in the same manner as above. [Problems to be Solved by the Invention] In the conventional test method, test signals to be transmitted from the test card are selected and transmitted depending on the type of terminal 1/F card. There are various types of terminal ■/F cards with different data formats, such as synchronous data terminal 1/F cards, start-stop data terminal I/F cards, and 32
Kbps voice terminal 1/F card and l 5 Kbps
This is a voice terminal I/F card, etc. Therefore, the test signal must be prepared accordingly on the test card side. The conventional test method has the disadvantage that the test card must be provided with a signal generator for all these terminal 1/F cards, making the circuit large and expensive. Furthermore, it is difficult and impossible to increase the circuit configuration in the test card every time a new terminal I/F card appears. Although there is a method of increasing the number of test cards themselves, there is a limit to this method due to the limited capacity of the housing, and there is also the problem of high costs. This invention was made in view of the above circumstances, and even if a terminal I/F card with a new function appears, there is no need to increase or configure a new circuit to handle the test card, and there is no need to increase the number of test cards themselves. The purpose of this invention is to provide a continuity test method that can test all types of terminal 1/F cards. [Means for solving the problem] In the present invention, a central processing unit for control 5, a test card 4 for conducting a continuity test, a common pattern generator 17 and a common pattern detector provided in this test card 4 are provided. 16
, a terminal interface card 2 on the side to be tested for continuity, and a gate to which outputs from a dedicated test signal generator 26 in a predetermined data format, a dedicated detector 27, and a common pattern generator 17 provided in this interface card 2 are provided. A circuit 29 outputs a common pattern signal from the common pattern generator 17 to the interface card 2 in response to a command from the central processing unit 5, and the central processing unit 5
A test signal is generated from the dedicated test signal generator 26 according to a command from the interface card 2, and this test signal is energized to the internal circuit 13.14 of the interface card 2 to output the test signal to the dedicated detector 2.
7, and this detection signal controls the gate circuit 29 to return the common pattern signal to the test card 4 side, where it is detected by the common pattern detector 17, and the transmission line 11 between the test card 4 and the interface card 2 is detected. 12 and internal circuits 13 and 14 in the interface were tested for energization. In another aspect of the present invention, the test card 4 and the main central processing unit 5 are provided on the main station side y, and the interface card 2 and the slave central processing unit 8 are provided on the other station side Z connected by the transmission path 11. A power supply test is carried out with the interface card 2 in the partner station Z via the transmission line 11 in response to a command from the main central processing unit 5. [Function] Dedicated test signal generators 26 and corresponding dedicated detectors 2 are provided in the interface cards 2 with various data formats.
7 in advance, the internal energization test inside the interface card 2 is self-diagnosed, and if the energization result is normal, the common pattern signal is returned by the gate circuit 29, and the continuity test of the transmission path is performed on the test card side. The test was conducted independently in two stages. Further, in this invention, the interface card 2 of the partner station Z located at a remote location from the main station side y is subjected to a continuity test by a remote command, and an energization test via the transmission path 11 is also conducted. [Example] The present invention will be described below based on the drawings. FIG. 1 is a diagram showing an embodiment of the continuity test method of the present invention. In the figure, 1 is a pass line, 2 is a terminal I/F card, 3 is a terminal, 4 is a test (TEST) card, 5 is a central processing unit (CPU), and 10 is a line interface card (CT card). The terminal I/F card 2 is connected to the path line 1 by a bus 12. The terminal I/F cards 2 to be tested for continuity are various terminal 1/F cards 2a~
2n, which are connected to corresponding various terminals 3a to 3n, respectively. Here, the terminal 3a is, for example, an audio terminal, and the terminal 3n is a data terminal, and their hardware configurations are different. Therefore, the corresponding terminal I/F card 2a and terminal I/F card 2n have different hardware configurations. Each terminal 1/F card 2
are connected to the path line 1 via a bus 12, respectively. The test card 4 is provided with a common pattern generator 7 and a common pattern detector 6 as common test signals, and 20 and 21 are unidirectional buffer gates. C.P.
U5 controls the opening and closing of these buffer gates 20 and 21, and also controls the operation of the test card 4. On the other hand, the audio terminal ■/F card 2a includes a transmission processing section 13 and a reception processing section 14. Selector switch 31.32,33゜3
4 internal circuits are provided. Further, a test signal generator 26 dedicated to audio and a detector 37 dedicated to the test signal generator 26 are provided in the terminal I/F card 2a. The selector switch 33 selectively switches between the test signal generator 26 and the audio terminal 3a and connects them to the transmission processing section 13 according to a command from the CPU 5. Selector switch 34
In response to a command from the CPU 5, the detector 27 and the terminal 3a are selectively switched and connected to the reception processing section 14. 22, 23, 24, and 25 are unidirectional buffer gates, with a selector switch 31 between the transmission processing section 3 and the buffer gate 22, and a selector switch 31 between the reception processing section 4 and the buffer gate 23. A selector switch 32 is provided respectively. The selector switch 32 selectively switches between the buffer gate 23 and the transmission processing section 13 and connects it to the reception processing section 14 . 29 is an AND gate serving as a gate circuit, to which the test OK signal of the dedicated detector 27 is input as gate control, and the signal from the common pattern generator 17 is given as the other input. The selector switch 31 consists of two select sections, one of which selectively switches between the reception processing section 14 and the buffer gate 22 and connects to the transmission processing section 13 . The other select section selectively switches the AND gate 29 and the transmission processing section 13 to select the bus 12. Shared pattern detector 1 via path line 1
Connect to 6. Reference numeral 10 is a CT card for communication control, which is connected to a transmission path such as a high-speed digital line. Similarly, the data terminal 1/F card 2n includes a transmission processing section 13. Reception processing unit 1
4. Unidirectional buffers 22 to 25, selector switch 31
~34. A circuit corresponding to the AND gate 29 is provided, and in this case, a test signal generator dedicated to digital data and a corresponding dedicated detector are provided. In this way, dedicated test signal generators and corresponding dedicated detectors according to functions and types are provided in advance in various terminal I/F cards. Next, the operation will be explained. The cpus instructs the test card 4 to notify the test target card address and to start the test. Then, the common pattern generator 17 sends a common PN pattern to all I/F cards to the target terminal 1/1 through the buffer gate 21.
Output to the F card 2a. Next, the CPU 5 issues a return test instruction to the terminal 1/F card 2a. In response to this instruction, the selector switch 33 first selects the dedicated test signal generator 26, from which a test signal in which two audible frequencies have been modulated is provided to the transmission processing section 13. Then, the two circuits of the selector switch 31 select another selector switch 32 and the AND gate 29, respectively, and the selector switch 32 selects the transmission processing section 13, so the test signal is given to the reception processing section 14, and a predetermined reception processing is performed. will be held. Next, the selector switch 34 selects the dedicated detector 27, and the test signal after receiving processing is applied to the dedicated detector 27. Here, it is determined whether the test signal output from the dedicated test signal generator 26 and the input test signal match, and if they match, a test OK signal is given to the AND gate 29. The AND gate is opened by this test OK signal,
The PN pattern signal passes through AND gate 29 and selector switch 31 . It is applied via buffer gate 22, bus 12 and buffer gate 20 to a shared pattern detector 16 within test card 4. Shared pattern detector 16
Then, when the transmitted PN pattern signal returns, the common pattern generator 17
It is checked to see if it matches the PN pattern signal transmitted from the PN pattern signal, and if there is no error, the test result is determined to be normal and the CPU 5 is notified. If there is an error or the PN pattern signal does not return from the terminal I/F card 2a within a certain period of time, the test result is notified to the CPU 5 as an error. Next, the CPU 5 reads the test results from the test card 4, performs analysis processing, and issues a return test cancellation instruction to the terminal I/F card 2a. Then, the selector switch 31,
32, 33.34 correspond to buffer gates 22, 23
．． 24 and 25 respectively, and the terminal 3a is connected to the path line 1 via the terminal I/F card 2a. Also CPU5
gives a test cancellation instruction to the test card 4, stops generation of the PN pattern, and ends the test of one channel. Next, when performing a return test on the data terminal I/F card 2n, it is performed in the same manner as described above, but in this case, the dedicated test signal generator in the terminal 1/F card generates a digital signal, and the dedicated detector detects digital data. Detects inconsistencies. Of course, the CPU 5 and the test card 4 are exactly the same, and the test can be performed even with terminal I/F cards 2n having different functions and data formats. FIG. 2 shows a general form of the local terminal 1/F card loop test, in which the CPU 5 issues a test instruction to the test card 4, a loop test instruction to the terminal 1/F card 2, and If the self-diagnosis is OK, the AND gate 29 is opened, the PN pattern passes through the AND gate 29, a match is detected by the shared pattern detector 16, and the CPU 5 is notified of the normal (abnormal) test result. FIG. 3 shows an embodiment of the remote loopback test of the present invention. The test card 4 on the command side of the main station y is a target terminal I/F card for testing that is connected to the CT card 10b of the remote partner station Z via the CT card 10a and a transmission line 11 such as a high-speed digital line. 2b and also the main C on the command side
The PU 5 and the slave CPU 8 on the target terminal 1/F card 2b side are connected via transmission paths 11, respectively. Therefore, Lord C
PU5 is the test card 4 of the master station y and the slave CPU of the partner station Z.
8, and the slave CPU 8 of the partner station issues a return test instruction to the target terminal I/F card 2b. If the self-diagnosis of the target terminal 1/F card 2b is OK, the AND gate 29 opens and the P transmitted from the command side y through the transmission path 11
The N pattern is folded back by the AND gate 29, and the common pattern detector 16 on the command side detects a failure or failure. In this way, the various terminal I/F cards of the partner station Z can be easily tested remotely from the main station, and their states can be inspected. In this way, continuity/operation tests within the terminal I/F card and continuity tests including pass lines and transmission line circuits can be accurately and easily performed. The effort and time required to test the remote terminal 1/F card is reduced, and costs can be reduced. [Effects of the Invention] As described above, according to the present invention, a central processing unit for control, a test card for conducting a continuity test, a common pattern generator and a common pattern detector provided in this test card, A terminal 1/F card on the side to be tested for continuity, a dedicated test signal generator in a predetermined data format provided in this terminal I/F card, a dedicated detector, and a gate circuit to which outputs from the common pattern generator are provided. The common pattern generator outputs a common pattern signal to the terminal 1/F card according to a command from the central processing unit, and the dedicated test signal generator generates a test signal according to a command from the central processing unit. is detected by the dedicated detector by energizing the internal circuit of the terminal 1/F card, and this detection signal controls the gate circuit to return the common pattern signal to the test card side, where it is detected by the common pattern detector and detected by the test card. Since the power supply test is performed on the transmission path between the terminal I/F card and the terminal I/F card, and the internal circuit inside the terminal 1/F card, the same test card can be used for terminal 1/F cards with various data formats. A continuity test can be performed. Even if a terminal 1/F card with a new function appears, it can be tested using the same test card, thereby reducing costs. In addition, each terminal I/F card is equipped with a self-diagnosis function, which enables early detection of failures and improves system availability. In another aspect of the present invention, a test card 4 and a main central processing unit 5 are provided on the main station side y, and a terminal 1/F card 2 and a slave central processing unit are provided on the other station side Z connected by the transmission line 11. A device 8 is provided, and the transmission path 1 is
Since the terminal I/F card 2 is tested for power through the terminal I/F card 1, the power test for the transmission line 11 can also be performed, and the terminal I/F card 2 of the other station Z can be tested without having to travel to a remote location.
It becomes possible to conduct a power test on the F card 2, which is convenient and also enables diagnostic management of equipment including the partner station. Therefore, there is no need for an operator to go to a remote station.
The cost reduction benefits will further increase. 4. Brief description of the drawings Fig. 1 is a block diagram of a continuity test device to which the present invention is applied, Fig. 2 is a block diagram showing the local test operation of the present invention, and Fig. 3 is a block diagram showing the remote operation of the present invention. Block diagram shown,
FIG. 4 is a block diagram of a conventional continuity test device, and FIG. 5 is a block diagram showing a conventional remote operation. 2...Terminal interface card, 3...Terminal,
4...Test card, 5,8...CPU, 10...
・CT card, 11... Transmission line, 13.14... Internal circuit, 16... Shared pattern detector, 17... Shared pattern generator, 26... Dedicated test signal generator,
27... Dedicated detector, 29... AND circuit.

Claims (2)

[Claims] (1) A central processing unit for control, a test card for conducting a continuity test, a common pattern generator and a common pattern detector provided in this test card, a terminal interface card for continuity testing, and this interface card. a dedicated test signal generator in a predetermined data format, a dedicated detector, and a gate circuit to which outputs from the shared pattern generator are given; A pattern signal is output to the interface card, a test signal is generated from the dedicated test signal generator according to a command from the central processing unit, and this test signal is energized to the internal circuit of the interface card to output the test signal to the dedicated detector. This detection signal controls the gate circuit to return the common pattern signal to the test card, and detects it with the common pattern detector to control the transmission path and interface between the test card and the interface card. A continuity test method that tests the internal circuitry of the device. (2) A test card that performs a continuity test with the control main central processing unit installed on the main station side, a shared pattern generator and a shared pattern detector installed in this test card, and a transmission line for the main station. A slave central processing unit for control and a terminal interface card for continuity testing provided on the partner station side connected via the interface card, and a dedicated test signal generator and dedicated detector in a predetermined data format provided within this interface card. and a gate circuit that is gate-controlled by the output of the dedicated detector, outputs a common pattern signal from the common pattern generator in response to a command from the main central processing unit, and transmits the common pattern signal via the transmission path. is input to the gate circuit of the interface card, and a test signal is generated from the dedicated test signal generator based on a command also given from the main central processing unit to the slave central processing unit via the transmission line, and the test signal is generated from the dedicated test signal generator. The signal is detected by the dedicated detector by energizing the internal circuit of the interface card, and the detection signal controls the gate circuit to return the common pattern signal to the test card via the transmission path, and the return common pattern signal is returned to the test card via the transmission path. A continuity test method in which a pattern signal is detected by the common pattern detector and a conduction test is performed on the transmission path between the test card on the main station side and the interface card on the partner station side and in the interface card. .