JPH0572616B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a continuity test method for terminal interface (I/F) cards such as voice terminals and data terminals.

[Conventional technology]

The conventional continuity test for terminal I/F cards is shown in Figure 4.
This is done using the method shown in FIG. That is, in FIG. 4, 1 is a bus line, 2 is a terminal I/F card, 3 is a terminal, 4 is a test (TEST) card, and 5 is a terminal I/F card.
is a control central processing unit (hereinafter referred to as CPU). A plurality of terminal I/F cards 2 2a to 2n are provided, and corresponding terminals 3a to 3n are connected to each terminal I/F card 2. For example, the terminal 3a is a voice terminal, and the terminal 3n is a data terminal. Therefore, the terminal I/F card 2a and the terminal I/F card 2n have different data formats and different hardware configurations. A test signal generator 6 and a detector 7 are provided in the test card 4, and each terminal I/F card 2 is connected to the bus line 1 by a bus.

Next, the operation will be explained.

First, in order to perform a continuity test on the terminal I/F card 2a for an audio terminal, the test signal generator 6 of the test card 4 generates two audible frequencies according to a test instruction from the CPU 5, and performs predetermined modulation processing. and transmits it to the terminal I/F card 2a. or
In response to the RLB instruction from the CPU 5, the terminal I/F card 2a forms a closed circuit that connects its own internal circuits in series. Next, the test signal from the test signal generator 6 passes through an internal circuit in the terminal I/F card 2a, is turned back, and is received by the detector 7 of the test card 4. Here, depending on whether the transmitted signal and the received signal match, it is determined whether the continuity function of the terminal I/F card 2a is good or bad, and the CPU 5
tell.

On the other hand, in order to test the data terminal I/F card 2n, digital data is generated from the test signal generator 6, and a return signal is detected by the detector 7 to determine whether it matches or does not match.

Figure 5 shows the terminal I/F in the remote system.
The configuration of the card continuity test is shown, 10a, 10b
is a line interface card (hereinafter referred to as CT card)
11 is a transmission line such as a high-speed digital line. CPU5 in station Y uses CT cards 10a, 10
The CPU 8 in the station Z is instructed to turn back the terminal I/F card 2a in the remote station Z via the transmission line 11 and the transmission line 11, and the test is performed in the same manner as above.

[Problem that the invention seeks to solve]

In the conventional test method, test signals to be transmitted from the test card are selected and transmitted depending on the type of terminal I/F card. There are various types of terminal I/F cards with different data formats, such as synchronous data terminal I/F cards,
These include a start-stop data terminal I/F card, a 32Kbps voice terminal I/F card, and a 16Kbps voice terminal I/F card. Therefore, test signals must be prepared accordingly on the test card side. The conventional test method has the disadvantage that the test card must be equipped with a signal generator for all these terminal I/F cards, making the circuit large and expensive. Furthermore, it is difficult and impossible to increase the circuit configuration in the test card every time a new terminal I/F card appears.
Although there is a method of increasing the number of test cards themselves, there is a limit to this method due to the limited capacity of the housing, and there is also the problem of high costs.

This invention was made in view of the above circumstances, and even if a terminal I/F card with a new function appears, there is no need to increase or configure a new circuit to handle the test card, and there is no need to increase the number of test cards themselves. The purpose is to provide a continuity test method that can test all types of terminal I/F cards.

[Means for solving problems]

In this invention, the control central processing unit 5
, a test card 4 for conducting a continuity test, a common pattern generator 17 and a common pattern detector 16 provided in this test card 4, an interface card 2 for a terminal on the continuity test side, and this interface card 2. A dedicated test signal generator 26 in a predetermined data format provided in the internal circuit, a dedicated detector 27, and a gate circuit 29 to which outputs from the shared pattern generator 17 are given are provided. output the common pattern signal from the device 17 to the interface card 2,
Similarly, a test signal is generated from the dedicated test signal generator 26 according to a command from the central processing unit 5, and this test signal is detected by the dedicated detector 27 by energizing the internal circuits 13 and 14 of the interface card 2. The gate circuit 29 is controlled by the detection signal, and the common pattern signal is returned to the test card 4 side and detected by the common pattern detector 17, and the transmission lines 11, 12 and the interface between the test card 4 and the interface card 2 are detected. Internal circuit 1
3 and 14 were conducted.

In another invention of this invention, the main station side y
A test card 4 and a main central processing unit 5 are provided at the main central processing unit 5, and an interface card 2 and a slave central processing unit 8 are provided at the other station side Z connected by the transmission line 11. An energization test with the interface card 2 in the partner station Z is performed via the line 11.

[Effect]

A dedicated test signal generator 26 and a corresponding dedicated detector 27 are provided in advance in each interface card 2 with different data formats, and the internal energization test inside the interface card 2 is self-diagnosed, and if the energization result is normal, the signal can be shared. The pattern signal is returned by the gate circuit 29, and the continuity test of the transmission path is performed on the test card side, so that the continuity test is performed independently in two stages.

Further, in this invention, the interface card 2 of the partner station Z located at a remote location from the main station side y is tested for continuity by a remote command, and the energization test via the transmission path 11 is also performed. .

〔Example〕

The present invention will be explained below based on the drawings. FIG. 1 is a diagram showing an embodiment of the continuity test method of the present invention. In the figure, 1 is a bus line, 2 is a terminal I/F card, 3 is a terminal, 4 is a test (TEST) card, 5 is a central processing unit (CPU), and 10 is a line interface card (CT card). , the terminal I/F card 2 is connected to the bus line 1 by a bus 12. The terminal I/F card 2 to be tested for continuity consists of various terminal I/F cards 2a to 2n, which are connected to corresponding various terminals 3a to 3n, respectively. Here, the terminal 3a is, for example, an audio terminal, and the terminal 3n is a data terminal, and their hardware configurations are different. Therefore, the corresponding terminal I/F card 2a and terminal I/F card 2n have different hardware configurations. Each terminal I/F card 2
are connected to bus line 1 via bus 12, respectively.

The test card 4 is provided with a common pattern generator 7 and a common pattern detector 6 as common test signals, and 20 and 21 are unidirectional buffer gates. The CPU 5 controls the opening and closing of these buffer gates 20 and 21, and also controls the test card 4.
control the operation of On the other hand, the audio terminal I/F card 2a includes a transmission processing section 13, a reception processing section 14, selector switches 31, 32, 33,
Internal circuits such as 34 are provided.

Further, a test signal generator 26 dedicated to audio and a detector 37 dedicated to the test signal generator 26 are provided in the terminal I/F card 2a. Selector switch 33 is CPU5
The transmission processing unit 13 selectively switches between the test signal generator 26 and the audio terminal 3a according to a command from the transmission processing unit 13.
Connect to. The selector switch 34 selectively switches between the detector 27 and the terminal 3a and connects them to the reception processing section 14 according to a command from the CPU 5.

22, 23, 24, and 25 are unidirectional buffer gates, and a selector switch 31 is provided between the transmission processing section 13 and the buffer gate 22, and a selector switch 32 is provided between the reception processing section 14 and the buffer gate 23. are provided for each. The selector switch 32 selectively switches between the buffer gate 23 and the transmission processing section 13 and connects it to the reception processing section 14 . 29 is an AND gate as a gate circuit, the test OK signal of the dedicated detector 27 is input as gate control, and the shared pattern generator 1
The signal from 7 is given as the other input. The selector switch 31 consists of two select sections, one of which selectively switches between the reception processing section 14 and the buffer gate 22 and connects it to the transmission processing section 13. The other select section selectively switches between the AND gate 29 and the transmission processing section 13 and connects it to the shared pattern detector 16 via the bus 12 and bus line 1.

10 is a CT card for communication control,
Connected to transmission lines such as high-speed digital lines. Similarly, the data terminal I/F card 2n includes a transmission processing section 13, a reception processing section 14, and unidirectional buffers 22 to 2n.
25, selector switches 31 to 34 and a circuit corresponding to an AND gate 29 are provided, and in this case, a test signal generator dedicated to digital data and a dedicated detector corresponding thereto are provided. In this way, dedicated test signal generators and corresponding dedicated detectors according to functions and types are provided in advance in various terminal I/F cards.

Next, the operation will be explained.

The CPU 5 instructs the test card 4 to notify the test target card address and to start the test. Then, the common pattern generator 17 outputs a PN pattern common to all I/F cards to the target terminal I/F card 2a, for example, via the buffer gate 21.

Next, the CPU 5 issues a return test instruction to the terminal I/F card 2a. Based on this instruction, the selector switch 33 first selects the dedicated test signal generator 26, from which a test signal in which two audible frequencies have been modulated is sent to the transmission processing section 26.
given to 3. Then, the two circuits of the selector switch 31 select another selector switch 32 and the AND gate 29, respectively, and the selector switch 32 selects the transmission processing section 13, so the test signal is given to the reception processing section 14, and a predetermined reception processing is performed. will be held. Next, the selector switch 34 is connected to the dedicated detector 27.
Select the test signal after reception processing or the dedicated detector 2
7 is given. Here, it is determined whether the test signal output from the dedicated test signal generator 26 and the input test signal match or not, and if they match, a test OK signal is given to the AND gate 29.
The AND gate is opened by this test OK signal, and the PN pattern signal passes through the AND gate 29, selector switch 31, and buffer gate 2.
2, to a shared pattern detector 16 in test card 4 via bus 12 and buffer gate 20. When the transmitted PN pattern signal is returned, the shared pattern detector 16 checks whether it matches the PN pattern signal transmitted from the shared pattern generator 17 for a certain period of time or a certain bit length, and checks if there is no error. Accept the test result as normal.
Notify CPU5. If there is an error or the PN pattern signal does not return from the terminal I/F card 2a within a certain period of time, the test result will be treated as an error.
Notify CPU5.

Next, the CPU 5 reads the test results from the test card 4, performs analysis processing, and issues a return test cancellation instruction to the terminal I/F card 2a. Then, the selector switches 31, 32, 33, and 34 select the buffer gates 22, 23, 24, and 25, respectively, and the terminal 3a is connected to the bus line 1 via the terminal I/F card 2a. Further, the CPU 5 gives a test cancellation instruction to the test card 4, stops generation of the PN pattern, and ends the test of one channel.

Next, when performing a return test on the data terminal I/F card 2n, it is performed in the same manner as described above, but in this case, the dedicated test signal generator in the terminal I/F card generates digital data, and the dedicated detector generates digital data. Detects matches and mismatches. Of course,
The CPU 5 and the test card 4 are exactly the same, and it is possible to test terminal I/F cards 2n with different functions and different data formats.

FIG. 2 shows a general form of loopback test for the local terminal I/F card, in which the CPU 5 issues a test instruction to the test card 4 and a loopback test instruction to the terminal I/F card 2. If the self-diagnosis at is OK, the AND gate 29 opens, the PN pattern passes through this AND gate 29, and the shared pattern detector 16 detects a match.
The CPU 5 is notified of the normal (abnormal) test result.

FIG. 3 shows an embodiment of the remote loopback test of the present invention. The test card 4 on the command side of the main station y is connected to the CT of the remote partner station Z via the CT card 10a and the transmission path 11 such as a high-speed digital line.
The target terminal I/F card 2b for testing that is connected to the card 10b, and the main CPU 5 on the command side and the slave CPU 8 on the target terminal I/F card 2b side are connected via transmission lines 11, respectively. . Therefore, the Lord
The CPU 5 issues test instructions to the test card 4 of the master station y and the slave CPU 8 of the partner station Z, and
8 issues a return test instruction to the target terminal I/F card 2b. If the self-diagnosis of the target terminal I/F card 2b is OK, the AND gate 29 opens and the command side
The PN pattern transmitted through the transmission path 11 is returned by the AND gate 29, and the shared pattern detector 16 on the command side detects whether it matches or does not match. In this way, the various terminal I/F cards of the partner station Z can be easily tested remotely from the main station, and their states can be inspected. In this way, continuity/operation tests within the terminal I/F card and continuity tests including bus lines and transmission lines can be accurately and easily performed. The effort and time required to test remote terminal I/F cards is reduced, and costs can be reduced.

[Effects of the Invention] As described above, according to the present invention, a central processing unit for control, a test card for conducting a continuity test, a common pattern generator and a common pattern detector provided in this test card, A terminal I/F card on the side to be tested for continuity, a dedicated test signal generator in a predetermined data format provided in this terminal I/F card, a dedicated detector, and a gate circuit to which outputs from the common pattern generator are provided. The common pattern generator outputs a common pattern signal to the terminal I/F card according to a command from the central processing unit, and the dedicated test signal generator generates a test signal according to a command from the central processing unit. is detected by a dedicated detector by energizing the internal circuit of the terminal I/F card, and this detection signal controls the gate circuit to return the common pattern signal to the test card side, where it is detected by the common pattern detector and detected by the test card. Since the power supply test is performed on the transmission path between the terminal I/F card and the internal circuit within the terminal I/F card, the same test card can be used for terminal I/F cards with various data formats. A continuity test can be performed. Even if a terminal I/F card with a new function appears, it can be tested using the same test card, thereby reducing costs. In addition, each terminal I/F card is equipped with a self-diagnosis function, which enables early detection of failures and improves system availability. or,
In another invention of this invention, a test card 4 and a main central processing unit 5 are provided on the main station side y, and a transmission line 1
Terminal I/F card 2 is connected to the other station Z connected with 1.
and a slave central processing unit 8, and a main central processing unit 5.
According to the command from the terminal I/
Since the F card 2 is tested for power, the transmission line 11 can also be tested for power, and the terminal I/I of the other station Z can be tested without going to a remote location.
It becomes possible to conduct a power test on the F card 2, which is convenient and also enables diagnostic management of equipment including the partner station. Therefore, there is no need for an operator to go to a remote station, further increasing the cost reduction benefits.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a continuity test device to which the present invention is applied, FIG. 2 is a block diagram showing the local test operation of the present invention, FIG. 3 is a block diagram showing the remote operation of the present invention, and FIG. 5 is a block diagram of a conventional continuity test device, and FIG. 5 is a block diagram showing a conventional remote operation. 2...Terminal interface card, 3...Terminal, 4...Test card, 5, 8...CPU, 1
0...CT card, 11...Transmission line, 13, 14
...Internal circuit, 16...Shared pattern detector, 1
7... Common pattern generator, 26... Dedicated test signal generator, 27... Dedicated detector, 29... AND circuit.

Claims (1)

[Claims] 1. A central processing unit for control, a test card for conducting a continuity test, a common pattern generator and a common pattern detector provided in this test card, and a terminal interface card for conducting a continuity test. and a dedicated test signal generator in a predetermined data format provided in the interface card, a dedicated detector, and a gate circuit to which outputs from the common pattern generator are given, A common pattern signal is output from the common pattern generator to the interface card, a test signal is generated from the dedicated test signal generator according to a command from the central processing unit, and this test signal is transmitted to the internal circuit of the interface card. Electrification is applied and detected by the dedicated detector, this detection signal controls the gate circuit, and the common pattern signal is returned to the test card side and detected by the common pattern detector to connect the test card and the interface. A continuity test method that tests the transmission path between the card and internal circuits within the interface. 2. A test card that performs a continuity test with the control central processing unit provided on the main station side, a shared pattern generator and a shared pattern detector provided in this test card, and a A slave central processing unit for control and a terminal interface card for continuity testing provided on the side of the connected partner station, a dedicated test signal generator with a predetermined data format provided in this interface card, a dedicated detector, and a gate circuit that is gate-controlled by the output of the dedicated detector, outputs a common pattern signal from the common pattern generator in response to a command from the central processing unit, and transmits this common pattern signal to the generating a test signal from the dedicated test signal generator based on a command input to a gate circuit of the interface card and also given from the central processing unit to the slave central processing unit via the transmission line;
The test signal is detected by the dedicated detector by energizing the internal circuit of the interface card, the detection signal controls the gate circuit, and the common pattern signal is returned to the test card via the transmission line; This return common pattern signal is detected by the common pattern detector to perform a power test on the transmission path between the test card on the main station side and the interface card on the partner station side and in the interface card. Continuity test method.