JPS5810896B2 - Line interface self-diagnosis circuit method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a line interface self-diagnosis circuit system, and more particularly to a line interface self-diagnosis circuit system that can perform self-diagnosis without affecting external circuits.

In the data processing system, as shown in FIG. 1, a terminal control device 2 is connected to a central processing unit 1, and channels 3, 4, 5, and 6 of each terminal are connected to this terminal control device 2. ing.

The channels 3°4.5 and 6 are connected in series.

Each channel 3, 4, 5, and 6 includes a transmission/reception right control circuit unit that controls which channel to transmit/receive data between the terminal control device and the terminal control device when transmitting/receiving data. A data transfer circuit unit is provided to perform the data transfer.

Conventionally, when operating such a data processing system, each part is provided with a self-diagnosis circuit to perform a simple check before actually starting operation.

The line interfaces of each channel are also self-checked, but in the conventional self-checking method, the checks must be performed with the connections to other channels connected in series disconnected. I checked with the drivers and receivers in the data transfer circuit and transmission/reception right control circuit removed.

Therefore, since the above line interface check is performed with the connection between the channel connected to the subsequent stage and the terminal control device disconnected, it has a very negative effect on each subsequent stage device, and furthermore, each driver and receiver Since the check c was omitted, there were problems such as insufficient checking.

Therefore, an object of the present invention is to provide a line interface self-diagnosis circuit system that improves such problems. Therefore, in the line interface self-diagnosis circuit system of the present invention, a plurality of terminal devices are connected in series with each other, and at least two In a data transmission system in which information is exchanged with a preceding and/or subsequent device via an information transfer path, a receiver and a driver are provided on the information transfer path for the preceding and subsequent devices. 1. A second information path, first and second bypass means for bypassing the first and second information paths, and receivers that connect the output ends of the drivers of the first and second information paths to corresponding receivers; A connection circuit connected to an input end of the information path, and an opening/closing means for opening and closing between the receiver and the driver of the first or second information path are provided, and the bypass means is closed at the time of self-diagnosis, and the first and second information passages are closed. The second information passage is opened from the front and rear devices, and predetermined pattern data is transferred to the first and second information passages with the opening and closing means opening between the receiver and the driver of the first or second information passage. The information path is passed through each driver and receiver of the second information path, and each driver and receiver is diagnosed based on the receiver output of the opened and closed information path.

An embodiment of the present invention will be described below with reference to FIGS. 2 and 3.

FIG. 2 shows a circuit configuration diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of its operation.

I in the figure is a data transfer circuit section or a transmission/reception right control circuit section,
■ is a loop check mechanism, I is a receiver, 8 is a driver, 9 is a driver, 10 is a receiver, 11 is an AND circuit,
12 is an OR circuit, RA to RA4 are contacts controlled by check relays (not shown), and ral to ra8
and rbl to rb4 are contacts controlled by a line bypass relay (not shown), 13 is a receiver, 14 is a driver, 15 is a receiver, 16 is a driver, 17 and 18
is an inverter, and Sl to S4 are contacts for forming a loop circuit.

The data transfer circuit section or transmission/reception right control circuit section I includes a receiver 7, drivers 8 and 9, a receiver 10, and contacts ra1 to r.
a3. Consists of rb1 to rb4, input/output terminals A,
B, C, and D are connected to external circuits, that is, other front-end and rear-end terminal devices or control devices such as terminal controllers.

Now, in order to operate the line interface in FIG. 2, a power supply (not shown) is turned on and brought into operation.

Then, the check relay is operated to close contacts RAl to RA4 to close the loop circuit of receiver 7 - driver 8 - receiver 10 - driver 9 - receiver 7.

1, and a logic "0", for example, is applied to the terminal Y of the OR circuit 12 as a self-diagnosis signal, so that the logic "0" is transmitted to the driver 9.

At this time, logic "0" is applied to the AND circuit 110 control element 2 as a loop check control signal to keep the AND circuit 11 in a non-conductive state.

How the logic "0" transmitted to the driver 9 acts as a self-diagnosis check signal will be explained with reference to FIG.

FIG. 3 explains the logic of each part of the line interface, and the receiver 7 in FIG. 2 is replaced by 13 in FIG.
Driver 8 corresponds to 14, receiver 10 corresponds to 15, driver 9 corresponds to 16, and relay contact RA1 in FIG.
RA4 to RA4 correspond to contacts S1 to S4 in FIG.

In FIG. 3, it is assumed that these contacts S1 to S4 are in a closed state, and the OR circuit 12 and AND circuit 11 in FIG. 2 are omitted.

In FIG. 3, it is assumed that logic "0" is applied from the input side of the driver 160 as the input signal R8O.

As a result, on the output side of the driver 16, a "-" voltage is generated at the terminal 1SC1, and a "+" voltage is generated at the terminal 1SC2.

And contact S1. Since S2 is closed, receiver 1
On the 30 input side, a "-" voltage is transmitted to the terminal 1RC1, and a "+" voltage is transmitted to the terminal 1RC2.

As a result, a logic "0" is output from the receiver 13, and a logic "1" is output to the output side of the inverter 17 as an output signal *C8i.
" is output.

Thus, the output signal C8O of inverter 18 is logic "0".
Therefore, on the output side of the driver 14, "
-" voltage is generated, and a "+" voltage is generated at terminal 08C2.

and contact S3. Since S4 is closed, receiver 1
On the input side of 5, a "-" voltage is transmitted to the terminal 0RC1, and a "+" voltage is transmitted to the terminal 0RC2.

This causes the receiver 15 to output a logic "0".

That is, if there is no abnormality in each part constituting the loop circuit as described above, the signal R8O applied to the driver 16 and the receiver 1
The same signal R8i obtained from 5 is obtained.

Therefore, in FIG. 2, if there is no abnormality in the loop circuit described above, the signal applied to the terminal Y of the OR circuit 12 and the signal obtained from the receiver 10 are the same.

As described above, logic "0" is applied to the control terminal Z of the AND circuit 110 and the AND circuit 11 is in a non-conducting state, so the output signal of the receiver 10 is taken out from the terminal X and sent to the terminal Y. The state of the loop circuit can be determined by comparing it with the signal applied to the loop circuit.

Therefore, if the results of the comparison are not the same, an abnormality has occurred in some part of the loop circuit, which will be investigated.

If the results of the comparison are the same, there is no abnormality, so the contacts RAl to RA4, which had been closed by the check relay, are opened.

Then, by controlling the circuit bypass relay to close the contacts ral to ra8 and open the contacts rbl to rb4, the input/output terminals A and C and B and D become conductive, respectively.

Of course, at this time, logic "1" is applied to the control terminal 2 of the AND circuit.

The AND circuit 11 is in a conductive state.

In this way, it can be operated correctly as a line interface.

As is clear from the above explanation, the loop check mechanism ■ shown by the dotted line in Figure 2 is operated to diagnose the function of each part that makes up the line interface, that is, the function of each part including each receiver and driver. 2, the bypass relay opens contacts ral to ra8 and closes contacts rbl to rb4.

Therefore, the above loop circuit has input/output terminals A, C and B.

It is open from D, and both input/output terminals AC and BD are closed.

Therefore, since the input/output terminals AC and BD are connected even during diagnosis of the loop circuit, other devices connected before and after the input/output terminals AC are not affected in any way.

Furthermore, since the loop circuit diagnosis is performed in a state where it is separated from other devices, it can be performed without any adverse effect on other devices.

As described above, according to the present invention, it is possible to perform self-diagnosis of the line interface as a whole, including its driver and receiver, so that the self-diagnosis results are extremely accurate.

Therefore, as shown in FIG. 1, when many channels 3 to 6 are connected in series to the terminal control device 2, if a fault occurs in the line interface of one of the channels, all This effectively accomplishes the necessity of rigorously diagnosing the line interface due to channel unavailability.

Moreover, self-diagnosis can be performed without any negative effect on other channels, so if an abnormality is detected,
Since you can easily diagnose just that channel,
A very efficient data processing device can be obtained.

In the above description, each contact point has been explained as being mechanically controlled by a relay or the like, but of course it can be constructed by using semiconductor elements or by other means.

[Brief explanation of the drawing]

FIG. 1 is a schematic explanatory diagram of a data processing system, FIG. 2 is a circuit configuration diagram of an embodiment of the present invention, and FIG. 3 is an explanatory diagram of its operation. In the figure, ■ indicates the data transfer circuit section or the transmission/reception right control circuit section;
■ is a loop check mechanism, 1 is a central processing unit, 2 is a terminal control device, 3 to 6 are channels, γ is a receiver, 8 and 9 are decouplers, 10 is a receiver, 11 is an AND circuit, 12 is an OR circuit , 13 is a receiver, 14 is a driver, 15 is a receiver, 16 is a driver, 17.18
is an inverter, RAl to RA are contacts controlled by a check relay (not shown), ral to ra8 and rbl to rb4 are contacts controlled by a line bypass relay (not shown), and Sl to S4 are contacts for forming a loop circuit. Each is shown below.

Claims (1)

[Claims] 1. In a data transmission system in which a plurality of terminal devices are connected in series to each other and exchange information with preceding and/or subsequent devices through at least two information transfer paths,
For front and rear devices, first and second information paths having a receiver and a driver in the information transfer path, and first and second bypasses that bypass the first and second information paths. means, and a connecting circuit for connecting the output ends of the drivers of the first and second information paths to the input ends of the corresponding receivers;
An opening/closing means for opening and closing between the receiver and the driver of the first or second information passage is provided, and at the time of self-diagnosis, the bypass means is closed and the first and second information passage is connected to the front and rear sides. At the same time, with the opening/closing means opening between the receiver and driver of the first or second information passage, predetermined pattern data is transmitted to each driver and receiver of the first or second information passage. Via,
1. A line interface self-diagnosis circuit system, characterized in that each driver and receiver are diagnosed based on receiver outputs of opened and closed information passages.