JPS63278149A - State holding circuit scanning system - Google Patents

Abstract

PURPOSE:To efficiently and rationally constitute an electronic circuit of large scale by mixing a parallel and serial scan systems in one electronic circuit according to the condition of the quantity of a hardware such as a signal line or a gate line. CONSTITUTION:A scan distribution circuit is provided for the interface circuit of a scan circuit corresponding to respective state holding circuits. In order to apply a scan address to the state holding circuit according to the parallel scan system, a serial/parallel converting circuit is disposed. The address information of serial data steps a shifter counter 10 to decode the value in a decoder 11 and form a parallel scanning address. According to a scan circuit selecting signal formed in a decoder 12, one group of the state holding circuit groups is selected to be scanned. When the selected scan circuit is a serial scan circuit, the address information of inputted serial data is inputted to the relevant serial scan circuit without being converted.

Description

[Detailed Description of the Invention] [Summary] In complex digital circuits, as a method for searching for failures and depacking software, it is necessary to use state-holding circuits such as latches in major parts of the circuit. It is possible to set data and output the contents of the state holding circuit at a certain point in time to track the movement of the data set in the state holding circuit, or to stop the clock at a certain point and output the contents of the state holding circuit at that time. By investigating the contents, we analyze the operation and identify the location of the failure.

Normally, there are many such state-holding circuits, so by assigning an address to each state-holding circuit and specifying or scanning a specific one, it is possible to sequentially select the name state-holding circuit. Made.

Conventionally, there are two ways to give such an address value: one is to give it as parallel data (parallel scan circuit), and the other is to give it as serial data and convert it into parallel data (serial scan circuit).

When the number of state holding circuits is very large, the number of bits of the address becomes large in the method of giving addresses as parallel data, and the number of input lines increases.
Furthermore, in a system in which addresses are given as serial data, the amount of hardware for serial/parallel conversion of addresses is large.

The purpose of the present invention is to configure rational hardware according to hardware conditions (such as whether there is enough room for signal lines or sufficient logic circuits).
Discloses a circuit configuration in which a parallel scan circuit and a serial scan circuit can be mixed depending on the hardware environmental conditions, and an address can be given in either parallel data or serial data format. ing.

[Field of Industrial Application] The present invention relates to how to give a scan address during a scan operation to read or write state information of a state holding circuit in an electronic circuit having a plurality of state holding circuits called latches. It is. Recent information processing devices have a built-in circuit called a scan circuit for diagnosing electronic circuits, etc., but as integrated circuits have become larger, the number of state-holding circuits that must be scanned has also increased. There is a need for a way to reduce the amount of circuitry and the number of signal lines.

[Prior Art] Since a scan circuit is intended to set the state of a state-holding circuit in an electronic circuit and read the state, it is necessary to specify which state-holding circuit to scan. .

To do this, it is necessary to assign a unique number to each state holding circuit and give it as an address.

The most commonly used method for providing scan addresses is a method called parallel scan.

FIG. 3 is a diagram showing an example of a parallel scan method, and as shown in the figure, address signal lines 51 are prepared as many as the number of bits that can express a scan address, and scan addresses are given to them in parallel. by 53
This method specifies which state-holding circuit to scan among the state-holding circuits shown in . In addition to requiring the address decoder 52 in this method, for example, when scanning 256 state holding circuits, at least 8 scans and
Requires address signal line.

On the other hand, in recent years, a method called serial scan has also been adopted.

FIG. 4 is a diagram showing an example of a serial scan method. In this method, as shown in the figure, a scan address is given serially through a single signal line 54, and the scan address is held. In this method, the signals are sequentially held in a dedicated state holding circuit 55, and a parallel scan address is obtained from there by an address decoder 56, and one of the state holding circuits 57 to be scanned is designated. In this method, it is necessary to prepare as many state holding circuits dedicated to holding scan addresses as the number of bits that can express the scan address. In addition, by providing a counting function to the state holding circuit dedicated to holding scan addresses, multiple state holding circuits specified by consecutive scan addresses can be sequentially operated without serially resetting the scan address each time. Can be scanned.

[Problems to be solved by the invention] In recent years, the number of points to be scanned has increased as the scale of integrated circuits has increased, and in the conventional parallel scan method, many address signals are required to provide scan addresses. It requires a line. The serial scan method requires fewer signal lines for scanning, but
Because of the serial/parallel conversion of addresses, there was a problem in that the amount of material increased.

In view of these conventional problems, the present invention makes it possible to mix the parallel scan method and the serial scan method in one electronic circuit according to the limitations of physical quantity and signal lines. Furthermore, the purpose of the present invention is to provide a circuit configuration system in which the scan address given to the electronic circuit can be either parallel or serial.

[Means for Solving the Problems] According to the present invention, the above objects are achieved by the means described in the claims. That is, the present invention is a circuit configured to scan a plurality of circuits that hold state information, write state information to these circuits, or read out stored state information, and convert address values into parallel data. A parallel scan circuit that selects a circuit that holds the state information of the corresponding address by giving it as It is equipped with a serial scan circuit that selects the circuit to be
means for separating address information into scan circuit address information and address information for a serial scan circuit; said means for generating and outputting parallel address information from said address information when said address information is serial data; , means for generating and outputting serial address information from the applied address information when it is parallel data.

[Function] The present invention uses the parallel scan method for the state holding circuit group in parts such as gates where there is margin for signal lines but not for quantity of materials such as gates; For the state holding circuit group where there is no room for signal lines, use
By using the scan method and using a parallel-to-serial conversion circuit when the scan addresses given to both groups are given in parallel, and a serial-to-parallel conversion circuit when they are given in serial, all The scan address is distributed to the state holding circuit.

Therefore, according to the present invention, the parallel scan method and the serial scan method can be mixed in one electronic circuit depending on the physical quantity limitations and the signal line limitations.

The scan address given to the electronic circuit may be either parallel or serial.

[Embodiment] FIG. 1 is a block diagram of an embodiment of the present invention, in which 1 is a scan distribution circuit, 2 is a serial-to-parallel conversion circuit,
3-5 are parallel scan circuits, 6-8 are serial scan circuits.
9 represents a scan circuit and a state holding circuit.

In the same figure, parallel scan circuits 3 to 5 are respectively similar to those described above based on FIG.
Further, the serial scan circuits 6-8 are similar to those described above with reference to FIG. In this embodiment, as shown in the figure, there are six groups of state holding circuits, and there are scan circuits corresponding to each group. The parallel scan method is used for state holding circuit groups 1 to 3, and the parallel scan method is used for state holding circuit groups 1 to 3.
6, a serial scan method is adopted. The scan interface for all these state holding circuits is based on a serial scan method.

A scan distribution circuit 1 is provided for interfacing with scan circuits corresponding to each state holding circuit group. Further, a serial-to-parallel conversion circuit 2 is provided in order to provide a scan address to a state holding circuit using a parallel scan method.

FIG. 2 is a diagram showing an example of the configuration of the above-mentioned scan distribution circuit and serial/parallel conversion circuit, where ]0 is a shifter counter, 11.1.2 is a decoder, 13 is a selector, and 14 is an AND circuit. represents.

In the figure, address information given as serial data increments a shifter counter 10, and the value of the shifter counter is decoded by a decoder 11 to generate a scan address for parallel scan.

Further, one group among the state holding circuit groups is selected to be scanned by a scan circuit selection signal generated by the decoder 12.

When the scan circuit selected by the scan circuit selection signal is a serial scan circuit, the address information based on the input serial data is input to the corresponding serial scan circuit without being converted.

In this embodiment, a configuration is shown in which address information is given as serial data. However, when address information is given as parallel data, it is directly given to the parallel scan circuit, and parallel/serial data processing is performed. It is sufficient to adopt a configuration in which the conversion is performed and the converted signal is supplied to the serial scan circuit.

Parallel/serial conversion in this case can be easily realized using a shift register or the like.

[Effects of the Invention] As explained above, according to the present invention, parallel scanning can be performed in one electronic circuit according to the limitations on the number of signal lines and the amount of hardware such as gates = 11-. Although it is possible to mix the serial scan method and the serial scan method, it is possible to efficiently and rationally configure large-scale electronic circuits. Another advantage is that the addresses given for scanning can be either parallel or serial.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing an example of the configuration of a scan distribution circuit and a serial-to-parallel conversion circuit, FIG. 3 is a diagram showing an example of a parallel scan system, and FIG. FIG. 4 is a diagram showing an example of the serial scan method.

Claims (1)

[Scope of Claims] A circuit configured to scan a plurality of circuits that hold state information and write state information to these circuits or read out stored state information, and which writes address values in parallel. A parallel scan circuit that selects a circuit that holds the state information of the corresponding address by giving it as data, and a parallel scan circuit that generates the address value as parallel data from the given serial data, thereby storing the state information of the corresponding address. a serial scan circuit for selecting a circuit to hold; means for separating the given address information into address information for the parallel scan circuit and address information for the serial scan circuit; and means for separating the given address information into address information for the parallel scan circuit and address information for the serial scan circuit; means for generating and outputting parallel address information from this when is serial data; and means for generating and outputting serial address information from this when the given address information is parallel data. Features a state-holding circuit scanning method.