JPS63276913A - Scan path - Google Patents

Abstract

PURPOSE:To prevent racing of data by providing a required number of stages of inverters retarding a signal passing therethrough between flip-flops forming a scan path so as to avoid the effect of clock skew. CONSTITUTION:Inverters 3, 4 comprising MOSFETs are provided between shift flip-flops 1, 2 comprising MOSFETs. Through the constitution above, a signal at a node D1b is changed with a delay more than a signal at a node D1a. Thus, even in the presence of clock skew retarding a clock signal T2 more than a clock signal T1, since the change in the data at the node D1b is delayed, a data d1 is sent to the node D2 and no racing is caused.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application] The present invention relates to a scan path that makes it possible to improve data racing due to clock skew.

[Conventional technology]

FIG. 3 is a block diagram showing the configuration of a scan path in a conventional logic circuit.

In this figure, 1 and 2 are shift flip-flops composed of MOS transistors, 5 is a scan signal line, D, , D, , D2 is a node of the scan signal line 5, 31 is a scan input pin, ' rt, t clock input pins, SO are skim mold "d", "l IFT2
is a clock signal, which forms a scan path in shift flip-flops 1 and 2 here.

Only the minimum input/output pins required to perform the operation are shown.

FIG. 4 is a diagram showing the configuration of input/output pins of the shift flip-flop 1, for example.

In this figure, the same symbols as in FIG. 3 indicate the same parts,
DI is data input pin, NM is normal operation mode pin, S
M is the scan operation mode pin, N is the data output pin, and this shift flip-flop is in the normal operation mode,
The clock input pin T is used in both scan operation modes.

In the scan path shown in FIG. 3, the shift flip-flops 1.about.2 are connected in series by the scan signal line 5 to form a shift register.

In the scan mode, the data of each flip-flop is transferred to the shift flip-flop 1 connected by the scan signal line 5.
, transmitted between the two.

FIG. 5 is a timing chart 1- for explaining the operation of a conventional scan path.

In this figure, the same symbols as in FIG. 3 indicate the same parts,
do, d, , d, t, to the node D0. Node D1.
This is initial data of node D2.

The output of each shift flip-flop 1, 2 changes in synchronization with the rising edge of the clock signal T, ,'1''2, and node D1
Data d0 is transmitted to node D, and data d1 is transmitted to node D. In this way, data d0 to d2 are transmitted through the shift flip-flops 1 and 2 one stage at a time in synchronization with the clock signals TI and T.

[Problems to be Solved by the Invention] In the conventional scan path as described above, if the clock signals 'rI and 'I'2 shown in FIG. 3 change at the same timing, the data transmission on the scan path is correct. However, if the timings of the clock signals ゛l'□ and T2 are shifted, data transmission will not be carried out correctly.

For example, as shown in FIG. 6, clock signals T, ,T,
If there is a clock skew in the node D1, data racing occurs in which the data d0 set in the node D1 is transmitted all the way to the node D2 at once. Such data racing due to lock skew is particularly likely to occur in the scan path where the shift 1 flip-flop constitutes a shift register, and in order to prevent data racing due to lock skew, clock signal 1
There is a problem in that the clock circuit needs to be designed with high precision so that the clock skew of ゜'r2 is small.

The present invention was made to solve this problem, and aims to obtain a scan path in which data racing is less likely to occur (and without using a highly precisely designed clock circuit).

[Means for solving problems]

The scan path according to the present invention is provided with an inverter that delays a passing signal between flip-flops forming the scan path.

[Effect]

In this invention, the data transmitted to the next stage flip-flop is delayed by the inverter, so that the influence of clock skew does not occur.

〔Example〕

FIG. 1 is a block diagram showing the configuration of an embodiment of the scan path of the present invention.

In this figure, the same symbols as in FIG. 3 indicate the same parts,
Inverters 3 and 4 are composed of Mo5t transistors, and the gate length of the constituent transistors is larger than the minimum gate length, producing the effect of delaying the passing signal. D.
, , Dlb are nodes of the scan signal line 5.

Further, FIG. 2 is a timing chart for explaining the operation of the scan path of the present invention, and is a timing chart for explaining the operation of the scan path of the present invention. D
l,, Dlb, data do in D2.

The state of transmission of d, d2 is shown.

That is, in the scan path of the present invention, between the shift flip-flops 1 and 2, nodes l), .

The signal at node Dts changes later than the signal at node Dts.

Therefore, as shown in FIG. 2, the clock signal llI2
Even if there is a clock skew that lags behind the clock signal T, data changes at nodes D and b are delayed, so data d1 is transmitted to node D, and racing does not occur.

In addition, in the above embodiment, a scan path is explained in which the scan terminal and the data terminal are made up of the shift 1 to flip-flop in which they are independent.17 However, the present invention is not limited to this, and the terminals may be shared. It can also be applied to scan paths constructed by other types of shift flip-flops, such as

In addition, in the above embodiment, a scan path was explained that was constituted by shift flip-flops that shared a clock signal for scan operation and normal operation.
It can also be applied to scanpaths constructed from phase clocks or other clock-type shift-free abflops that have independent scan clock pins and system clock pins.

Further, inverters may be inserted between all shift flip-flops in the scan path, or only between shift flip-flops with large clock skew.

〔Effect of the invention〕

As described above, this invention has the effect that it is not affected by clock skew and data racing can be prevented because an inverter is provided between the flip-flops constituting the scan path to delay the passing signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the scan path of the present invention, FIG. 2 is a timing chart for explaining the operation of the scan path of the present invention, and FIG. 3 shows the configuration of a conventional scan path. 4 is a pin layout diagram of a shift flip-flop, and FIG. 5 is a timing chart 1-1 for explaining the operation of a conventional scan path.
FIG. 6 is a timing chart for explaining data racing in a conventional scan path. In the figure, 1 and 2 are shift flip-flops, 3.4
is an inverter, 5 is a scan signal line, DI is a data input pin, SI is a scan input pin, NM is a normal operation mode pin, SM is a scan operation mode pin, 'r is a clock input pin, N is a data output pin, SO is This is a scan output pin. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 Figure 2 D = = = Hoko = Figure 4 Figure 5 Figure 6 D2 dz ' d* Procedural amendment (voluntary) 1. Display of case Patent application No. 62112905 Bow 2, title of invention scan t Representative Moriya Shiki 4, agent address Mitsubishi Electric Corporation, 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (7375) Masuo Oiwa, patent attorney (contact number 03 (213) 3421 Licensing Department) 5 , ? i
l Positive subject specification R, claims column and detailed description of the invention column 6, ? 111 Correct content (1) The claims in the specification are supplemented as shown in the attached sheet.I amend the statement I in which an inverter is provided as "Inverters that cause a delay are provided in more than the logically necessary number of stages." 2. Claim (I) In a scan bus constructed of 70 INIA machine trigger flipflops or mask slave flipflops, a passing signal is delayed between the clip floats constituting the scan bus. The park is like a pottery! (Fake Mataku-hai? A Zuro canvas that is characterized by the addition of JJ. (2) 7 Lttsuno'o: and the inverter is composed of M O8 transistors. The scan canvas according to claim No. +1), characterized in that:

Claims (2)

[Claims] (1) A scan path comprising a plurality of edge-triggered flip-flops or master-slave flip-flops, characterized in that an inverter for delaying a passing signal is provided between the flip-flops constituting the scan path. (2) The scan path according to claim (1), wherein the flip-flop and the inverter are constituted by MOS transistors.