JPS63276645A - キャッシュ・メモリ制御方式 - Google Patents

キャッシュ・メモリ制御方式

Info

Publication number
JPS63276645A
JPS63276645A JP62110867A JP11086787A JPS63276645A JP S63276645 A JPS63276645 A JP S63276645A JP 62110867 A JP62110867 A JP 62110867A JP 11086787 A JP11086787 A JP 11086787A JP S63276645 A JPS63276645 A JP S63276645A
Authority
JP
Japan
Prior art keywords
address
request
cache
main memory
cycle
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62110867A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0461384B2 (cs
Inventor
Atsushi Ike
敦 池
Hideki Osone
大曽根　秀樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62110867A priority Critical patent/JPS63276645A/ja
Publication of JPS63276645A publication Critical patent/JPS63276645A/ja
Publication of JPH0461384B2 publication Critical patent/JPH0461384B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)
  • Advance Control (AREA)
JP62110867A 1987-05-08 1987-05-08 キャッシュ・メモリ制御方式 Granted JPS63276645A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62110867A JPS63276645A (ja) 1987-05-08 1987-05-08 キャッシュ・メモリ制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62110867A JPS63276645A (ja) 1987-05-08 1987-05-08 キャッシュ・メモリ制御方式

Publications (2)

Publication Number Publication Date
JPS63276645A true JPS63276645A (ja) 1988-11-14
JPH0461384B2 JPH0461384B2 (cs) 1992-09-30

Family

ID=14546695

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62110867A Granted JPS63276645A (ja) 1987-05-08 1987-05-08 キャッシュ・メモリ制御方式

Country Status (1)

Country Link
JP (1) JPS63276645A (cs)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6219748B1 (en) 1998-05-11 2001-04-17 Netlogic Microsystems, Inc. Method and apparatus for implementing a learn instruction in a content addressable memory device
US6240485B1 (en) 1998-05-11 2001-05-29 Netlogic Microsystems, Inc. Method and apparatus for implementing a learn instruction in a depth cascaded content addressable memory system
US6697911B2 (en) 1997-10-30 2004-02-24 Netlogic Microsystems, Inc. Synchronous content addressable memory

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6697911B2 (en) 1997-10-30 2004-02-24 Netlogic Microsystems, Inc. Synchronous content addressable memory
US6961810B2 (en) 1997-10-30 2005-11-01 Netlogic Microsystems, Inc. Synchronous content addressable memory
US6219748B1 (en) 1998-05-11 2001-04-17 Netlogic Microsystems, Inc. Method and apparatus for implementing a learn instruction in a content addressable memory device
US6240485B1 (en) 1998-05-11 2001-05-29 Netlogic Microsystems, Inc. Method and apparatus for implementing a learn instruction in a depth cascaded content addressable memory system

Also Published As

Publication number Publication date
JPH0461384B2 (cs) 1992-09-30

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