JPS63273343A - Lead frame - Google Patents
Lead frameInfo
- Publication number
- JPS63273343A JPS63273343A JP62109312A JP10931287A JPS63273343A JP S63273343 A JPS63273343 A JP S63273343A JP 62109312 A JP62109312 A JP 62109312A JP 10931287 A JP10931287 A JP 10931287A JP S63273343 A JPS63273343 A JP S63273343A
- Authority
- JP
- Japan
- Prior art keywords
- frame
- lead
- lead frame
- die pad
- frames
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 claims abstract description 23
- 229920005989 resin Polymers 0.000 claims abstract description 23
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 238000000465 moulding Methods 0.000 claims abstract 4
- 238000007789 sealing Methods 0.000 claims description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の組み立てに用いるリードフレーム
に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a lead frame used for assembling semiconductor devices.
従来、この種リードフレームは第３図および第４図に示
すように構成されている。第３図は従来のリードフレー
ムを示す平面図、第４図は第３図中ＩＩ−ｎ断面図であ
る。これらの図において、符号１はリードフレームを示
し、このリードフレーム１は、フレーム位置決め穴２お
よびフレーム送シ穴３が穿設された一対のフレーム条帯
部４と、このフレーム条帯部４を連結する複数のフレー
ム枠部５と、これらのフレーム枠部５間に設けられたダ
イパッドリード６およびステッチリードＴとが一体に形
成されている。８は前記ダイパッドリード６に固着した
トランジスタチップ、９は金線またはアルミニウム線か
ら々るリードワイヤで、このリードワイヤ９は前記トラ
ンジスタチップ８の電１！（図示せず）と前記ステッチ
リード７とを接続している。１０は前記トランジスタテ
ップ８、リードワイヤ９、ダイパッドリード６の一部お
よびステッチリードＴの一部を樹脂封止したモールド樹
脂である。Conventionally, this type of lead frame has been constructed as shown in FIGS. 3 and 4. FIG. 3 is a plan view showing a conventional lead frame, and FIG. 4 is a sectional view taken along line II-n in FIG. In these figures, reference numeral 1 indicates a lead frame, and this lead frame 1 includes a pair of frame strips 4 in which frame positioning holes 2 and frame feed holes 3 are drilled, and this frame strips 4. A plurality of connected frame sections 5, die pad leads 6 and stitch leads T provided between these frame sections 5 are integrally formed. 8 is a transistor chip fixed to the die pad lead 6, 9 is a lead wire made of gold wire or aluminum wire, and this lead wire 9 is connected to the transistor chip 1! (not shown) and the stitch lead 7 are connected to each other. Reference numeral 10 denotes a molded resin in which the transistor tip 8, lead wire 9, part of the die pad lead 6, and part of the stitch lead T are sealed with resin.
このようにリードフレーム上に形成された半導体装置は
、次工程においてリードフレームごと搬送され、さらに
リール等に巻き取られていた。The semiconductor device formed on the lead frame in this manner is transported together with the lead frame in the next step, and is further wound up on a reel or the like.
しかるに従来のリードフレームでは、モールド樹脂封止
以降の工程におけるフレーム搬送時あるいはリール巻き
取シ時にモールド樹脂が外力を受けた場合、半導体装置
およびリードフレームが変形することがアシ、その品質
が低下するという問題がおった。このため、リードフレ
ームを慎重に取扱わなければならず、作業能率が著しく
低下するという問題もあった。However, in conventional lead frames, if the mold resin is subjected to external force during frame transportation or reel winding in the process after mold resin sealing, the semiconductor device and lead frame may be deformed, resulting in a decrease in quality. There was a problem. For this reason, the lead frame must be handled carefully, resulting in a problem that work efficiency is significantly reduced.
本発明に係るリードフレームは、フレーム枠部の幅寸法
を互いに隣り合うモールド樹脂の間隔と略々等しい寸法
をもって形成したものである。In the lead frame according to the present invention, the width of the frame portion is approximately equal to the interval between adjacent mold resins.
フレーム枠部がモールド樹脂に当接し、モールド樹脂を
支持する。The frame portion contacts the mold resin and supports the mold resin.
〔実施例〕
以下、本発明を図に示す実施例を用いて詳細に説明する
。第１図は本発明に係るリードフレームの平面図、第２
図は第１図中Ｉ−Ｉ断面図である。[Examples] Hereinafter, the present invention will be explained in detail using examples shown in the drawings. Fig. 1 is a plan view of a lead frame according to the present invention, Fig. 2 is a plan view of a lead frame according to the present invention;
The figure is a sectional view taken along line II in FIG.
これらの図において符号１２．１４〜２０で示すものは
前記従来例と同一部材であるが、ここにおいてさらに詳
細に説明する。これらの図において、符号１１はリード
フレームで、このリードフレーム１１には一対のフレー
ム条帯部１２ 、１２、フレーム枠部１３、ダイパッド
リード１４、ステッチリード１５が一体に形成されてい
る。すなわち、フレーム条帯部１２．１２は、等間隔お
いて複数個形成されたフレーム枠部１３によって連結さ
れると共に、ダイパッドリード１４およびこのダイパッ
ドリード１４の両側方に設けられたステッチリード１５
とを前記複数のフレーム枠部１３の間に配置するごとく
保持している。また、前記フレーム枠部１３はリードフ
レーム１１における幅方向中央部の幅寸法が他の部分よ
シ大きく形成され、この幅寸法は後述するモールド樹脂
の間隔と略々等しい寸法をもって形成されている。１６
はフレーム位置決め穴、１Ｔはリードフレーム送り装置
のヘッド（図示せず）が嵌入するフレーム送り穴である
。１８は前記ダイパッドリード１４に固着したトランジ
スタチップ、１９はこのトランジスタチップ１８の電極
（図示せず）と前記ステッチリード１５とを接続したリ
ードワイヤ、２０は前記トランジスタチップ１８、リー
ドワイヤ１９、ダイパッドリード１４の一部およびステ
ッチリード１５の一部を樹脂封止したモールド樹脂で、
このモールド樹脂２００両側部２０凰が前記フレーム枠
部１３に当接している。In these figures, reference numerals 12, 14 to 20 are the same members as in the prior art example, but they will be explained in more detail here. In these figures, reference numeral 11 denotes a lead frame, and a pair of frame strips 12, 12, a frame frame 13, a die pad lead 14, and a stitch lead 15 are integrally formed on this lead frame 11. That is, the frame strip portions 12.12 are connected by a plurality of frame portions 13 formed at equal intervals, and are connected by a die pad lead 14 and stitch leads 15 provided on both sides of the die pad lead 14.
are held so as to be arranged between the plurality of frame sections 13. Further, the frame portion 13 is formed so that the width dimension of the center portion in the width direction of the lead frame 11 is larger than that of the other portions, and this width dimension is formed to have a dimension that is approximately equal to the spacing between the molded resins, which will be described later. 16
1 is a frame positioning hole, and 1T is a frame feed hole into which a head (not shown) of a lead frame feed device is fitted. 18 is a transistor chip fixed to the die pad lead 14; 19 is a lead wire connecting an electrode (not shown) of this transistor chip 18 to the stitch lead 15; 20 is the transistor chip 18, the lead wire 19, and the die pad lead. A part of the stitch lead 14 and a part of the stitch lead 15 are sealed with a molded resin.
Both sides 20 of this molded resin 200 are in contact with the frame portion 13 .
したがって、リードフレーム１１上ンこ形成された半導
体装置は、モールド樹脂２０が両側方からフレーム枠部
１３によって支持されることによシ、外力を受けても変
形しにくくなる。Therefore, the semiconductor device formed on the lead frame 11 becomes difficult to deform even when subjected to external force because the mold resin 20 is supported by the frame portion 13 from both sides.
なお、フレーム枠部１３の形状は本実施例に示したもの
に限らず、互いに隣り合うモールド樹脂に当接する形状
であればどのように形成してもよい。Note that the shape of the frame frame portion 13 is not limited to that shown in this embodiment, and may be formed in any shape as long as it comes into contact with adjacent mold resins.
また、前記実施例ではトランジスタチップを使用したも
のを示したが、トランジスタチップの代わ）Ｋダイオー
ド、サイリスタ、ＩＣといった他の半導体チップを使用
しても同等の効果が得られる。Furthermore, although the above-mentioned embodiments use transistor chips, the same effect can be obtained by using other semiconductor chips such as K diodes, thyristors, and ICs instead of transistor chips.
さらにまた、本発明によれば、超小型の半導体装置を製
造するに当シ、フレーム枠部の形状を変えるだけでモー
ルド樹脂が支持されるため、各リードのパターンを変え
なくてもよいから、半導体チップを固着するダイボンダ
およびリードワイヤを接続するワイヤボンダを改造せず
に使用することができる。Furthermore, according to the present invention, when manufacturing ultra-small semiconductor devices, the mold resin is supported by simply changing the shape of the frame, so there is no need to change the pattern of each lead. The die bonder that fixes the semiconductor chip and the wire bonder that connects the lead wires can be used without modification.
以上説明したように本発明によれば、リードフレームに
おけるフレーム枠部の幅寸法を互いに隣り合うモールド
樹脂の間隔と略々等しい寸法をもって形成したため、フ
レーム枠部がモールド樹脂に当接し、篭−ルド樹脂を支
持するので、モールド樹脂が外力を受けても半導体装置
およびリードフレームが変形しに＜＜、その品質および
作業能率の向上をはかることができる。As explained above, according to the present invention, since the width dimension of the frame frame portion of the lead frame is formed to be approximately equal to the interval between adjacent mold resins, the frame frame portions are in contact with the mold resin, and the lead frame is Since the resin is supported, even if the mold resin receives external force, the semiconductor device and the lead frame will not be deformed, and the quality and work efficiency can be improved.
第１図は本発明に係るリードフレームの平面図、第２図
は第１図中Ｉ’−Ｉ断面図、第３図は従来のリードフレ
ームを示す平面図、第４図は第３図中■−■断面図であ
る。
１１＠・―・リードフレーム、１２１１・・・フレーム
条帯部、１３・・・・フレーム枠部、１４・−・・ダイ
パッドリード、１５１１１１１１−ステッチリード、１
Ｂ−＠・−トランジスタチップ、２０・−・・モールド
樹脂。FIG. 1 is a plan view of a lead frame according to the present invention, FIG. 2 is a sectional view taken along line I'-I in FIG. 1, FIG. 3 is a plan view showing a conventional lead frame, and FIG. ■-■ It is a sectional view. 11@---Lead frame, 1211---Frame stripe part, 13---Frame frame part, 14---Die pad lead, 15111111-Stitch lead, 1
B-@.-Transistor chip, 20.--Mold resin.
Claims (1)
する複数のフレーム枠部と、これらのフレーム枠部間に
設けられたダイパッドリードおよびステッチリードとが
一体に形成され、かつ前記ダイパッドリードに固着した
半導体チップをモールド樹脂によつて封止してなるリー
ドフレームにおいて、前記フレーム枠部の幅寸法を互い
に隣り合うモールド樹脂の間隔と略々等しい寸法をもつ
て形成したことを特徴とするリードフレーム。A pair of frame strip portions, a plurality of frame frame portions connecting the frame strip portions, and a die pad lead and a stitch lead provided between these frame frame portions are integrally formed, and the die pad lead is connected to the die pad lead. A lead frame formed by sealing a fixed semiconductor chip with a molding resin, characterized in that the width of the frame portion is approximately equal to the distance between adjacent molding resins. flame.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62109312A JPS63273343A (en) | 1987-04-30 | 1987-04-30 | Lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62109312A JPS63273343A (en) | 1987-04-30 | 1987-04-30 | Lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63273343A true JPS63273343A (en) | 1988-11-10 |
Family
ID=14507015
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62109312A Pending JPS63273343A (en) | 1987-04-30 | 1987-04-30 | Lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63273343A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57149740A (en) * | 1981-03-11 | 1982-09-16 | Toshiba Corp | Manufacture of resin sealing type semiconductor device |
-
1987
- 1987-04-30 JP JP62109312A patent/JPS63273343A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57149740A (en) * | 1981-03-11 | 1982-09-16 | Toshiba Corp | Manufacture of resin sealing type semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7019388B2 (en) | Semiconductor device | |
| JP2003332513A (en) | Semiconductor device and its manufacturing method | |
| KR100568225B1 (en) | Lead Frame and method for fabricating semiconductor package using the same | |
| JPS63273343A (en) | Lead frame | |
| JPH06104364A (en) | Lead frame and method and metallic mold for molding semiconductor chip using it | |
| JPS60136248A (en) | Manufacture of lead frame | |
| JPS621239A (en) | Semiconductor device | |
| KR0184108B1 (en) | Window taping method for manufacturing integrated circuit package and window tape | |
| KR200283436Y1 (en) | Semiconductor lead frame for cage | |
| KR960004872Y1 (en) | Lead frame structure of plastic quad flat package | |
| JPH03219663A (en) | Lead frame for semiconductor device | |
| KR200270526Y1 (en) | Leadframe of Semiconductor Package | |
| JPS61168947A (en) | Manufacture of semiconductor device and leadframe used in said device | |
| JPH02202046A (en) | Lead frame and manufacture of semiconductor device using same | |
| JPH03102859A (en) | Manufacturing method of semiconductor device | |
| JPH09260413A (en) | Semiconductor device and manufacture thereof | |
| JP2001035987A (en) | Semiconductor device and manufacture thereof | |
| JPH0284758A (en) | Resin sealed semiconductor device | |
| JPS63272062A (en) | Lead frame | |
| JPH0456334A (en) | Tab tape | |
| JPH01150347A (en) | Lead frame for manufacture of semiconductor device | |
| JP2004200719A (en) | Semiconductor device | |
| JPH0583178B2 (en) | ||
| JPH031562A (en) | Manufacture of lead frame | |
| JPH03165057A (en) | Lead frame |