JPS63271956A - Formation of element isolation of semiconductor device - Google Patents
Formation of element isolation of semiconductor deviceInfo
- Publication number
- JPS63271956A JPS63271956A JP10537287A JP10537287A JPS63271956A JP S63271956 A JPS63271956 A JP S63271956A JP 10537287 A JP10537287 A JP 10537287A JP 10537287 A JP10537287 A JP 10537287A JP S63271956 A JPS63271956 A JP S63271956A
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon
- silicon nitride
- nitride film
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 238000002955 isolation Methods 0.000 title claims abstract description 30
- 230000015572 biosynthetic process Effects 0.000 title description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 52
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 51
- 238000000034 method Methods 0.000 claims abstract description 43
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 43
- 230000003647 oxidation Effects 0.000 claims abstract description 29
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000005530 etching Methods 0.000 claims abstract description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 19
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 14
- 239000010703 silicon Substances 0.000 claims abstract description 14
- 230000001590 oxidative effect Effects 0.000 claims description 5
- 125000006850 spacer group Chemical group 0.000 claims description 3
- 230000007547 defect Effects 0.000 abstract description 10
- 230000000717 retained effect Effects 0.000 abstract 1
- 241000293849 Cordylanthus Species 0.000 description 12
- 150000004767 nitrides Chemical class 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 210000000988 bone and bone Anatomy 0.000 description 4
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229910000077 silane Inorganic materials 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 230000036417 physical growth Effects 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- VEDJZFSRVVQBIL-UHFFFAOYSA-N trisilane Chemical compound [SiH3][SiH2][SiH3] VEDJZFSRVVQBIL-UHFFFAOYSA-N 0.000 description 1
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体装置の素子分離形成方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for forming element isolation in a semiconductor device.
この発明は、バーズビークが小さく欠陥の少ない素子分
離形成方法に関するもので、半導体表面に薄い酸化膜を
形成した後、多結晶シリコン膜を成長させ、さらにシリ
コン窒化膜を積層させる。This invention relates to a device isolation formation method with small bird's beaks and few defects, in which a thin oxide film is formed on a semiconductor surface, a polycrystalline silicon film is grown, and a silicon nitride film is further laminated.
次に将来素子骨ｌＴｉ１ｌＷｌ域となる部分のシリコン
窒化膜、多結晶シリコン膜、シリコン酸化膜および半導
体基板を選択的にエツチングする。Next, the silicon nitride film, the polycrystalline silicon film, the silicon oxide film, and the semiconductor substrate are selectively etched in a portion that will become the device bone lTi1lwl region in the future.
次に、シリコン窒化膜を積層し、反応性ドライエツチン
グ等の異方性エツチング法を用い、このシリコン窒化膜
を異方性エツチングし、多結晶シリコン膜の側壁と上部
とにシリコン窒化膜を残し、他の領域のシリコン窒化膜
を完全に除去する。このシリコン窒化膜で被れた多結晶
シリコン膜をマスクにして、多結晶シリコン膜のない領
域を酸化し素子分離領域を形成する。次に活性領域とな
る部分に存在する窒化膜、多結晶シリコン膜および酸化
膜を順次除去する。Next, a silicon nitride film is laminated, and this silicon nitride film is anisotropically etched using an anisotropic etching method such as reactive dry etching, leaving a silicon nitride film on the sidewalls and top of the polycrystalline silicon film. , the silicon nitride film in other areas is completely removed. Using the polycrystalline silicon film covered with this silicon nitride film as a mask, regions where the polycrystalline silicon film is not present are oxidized to form element isolation regions. Next, the nitride film, polycrystalline silicon film, and oxide film existing in the portion that will become the active region are sequentially removed.
以上により厚い酸化膜で被れた素子分離３Ｍ域と半導体
表面が露出している活性領域が形成される。Through the above steps, an element isolation region 3M covered with a thick oxide film and an active region in which the semiconductor surface is exposed are formed.
この後、活性領域には半導体素子が作成される。After this, a semiconductor element is created in the active region.
半導体素子の素子分離とて従来から選択酸化法（ＬＯＣ
Ｏ３法）が使用されている。このり。Selective oxidation (LOC) has traditionally been used to isolate semiconductor devices.
O3 method) is used. This is it.
ＣＯ８法は次の様なものである。第２図ｆａｌに示す様
にシリコンなどの半導体表面１）を酸化し選択酸化時に
発生する応力を緩和するための緩衝用シリコン酸化膜１
２を形成し、さらに選択酸化時の酸化マスク用材料とし
てのシリコン窒化膜１３をＣＶＤ法にて積層する０次に
第２図（ｂｌに示す様に写真食刻法を用いレジスト１４
を所望の形状に形成し、このレジス１４をマスクとして
シリコン窒化膜１３をエツチングする。さらに第２図（
Ｃ１に示す様に酸化を行うとシリコン窒化膜のない領域
は酸化され厚い素子分離用の酸化膜１５が形成され、一
方シリコン窒化膜１３で被れていない領域は殆ど酸化さ
れない。The CO8 method is as follows. As shown in Figure 2 fal, a silicon oxide film 1 for buffering is used to oxidize a semiconductor surface 1) such as silicon and relieve stress generated during selective oxidation.
A silicon nitride film 13 is formed using the CVD method as a material for an oxidation mask during selective oxidation.As shown in FIG.
is formed into a desired shape, and the silicon nitride film 13 is etched using the resist 14 as a mask. Furthermore, Figure 2 (
When oxidation is performed as shown in C1, the region without the silicon nitride film is oxidized and a thick oxide film 15 for element isolation is formed, while the region not covered with the silicon nitride film 13 is hardly oxidized.
次に第２図ｆｄｌに示す様にシリコン窒化膜および緩衝
用シリコン酸化膜を順次エツチング除去する事により、
素子分離領域１６と活性領域１７が完成する。Next, as shown in FIG.
Element isolation region 16 and active region 17 are completed.
この後、活性領域１７には半導体素子が形成される。After this, a semiconductor element is formed in the active region 17.
従来のＬＯＣＯ３法では第２図（ｄｌに示す様に素子分
離領域の境界から活性領域へ長さｌの酸化膜が細長く伸
び、活性領域を狭くしてしまう。（これをバーズ・ピー
クという）このバーズ・ピークの長さｌは酸化条件等に
よっても異なるが、通常は０．５μｍ以上あり、素子分
子領域も狭くする事ができない、こめバーズ・ピークを
小さくする方法として、緩衝用シリコン酸化膜を薄くす
るかあるいはシリコン窒化膜を厚くする方法があるが、
どちらの場合もＬＯＧＯ３酸化工程で半導体基板に大き
な応力を及ぼし多数の結晶欠陥を誘起してしまい、素子
、分離特性を劣化させる。従って良好な素子分離特性を
保持しながら、上記のバーズ・ピークを小さくする事は
、従来のＬＯＣＯ３法を用いて不可能である。In the conventional LOCO3 method, as shown in Figure 2 (dl), an oxide film with a length l extends from the boundary of the element isolation region to the active region, narrowing the active region. (This is called a bird's peak.) The length l of the bird's peak varies depending on the oxidation conditions, etc., but it is usually 0.5 μm or more, and the device molecular area cannot be narrowed.As a method to reduce the bird's peak, a silicon oxide film for buffering is used. There are ways to make the silicon nitride film thinner or thicker.
In either case, large stress is applied to the semiconductor substrate in the LOGO3 oxidation step, inducing a large number of crystal defects, which deteriorates the device and isolation characteristics. Therefore, it is impossible to reduce the above-mentioned bird's peak while maintaining good element isolation characteristics using the conventional LOCO3 method.
上記問題点を解決するためにこの発明は、半導体基板（
シリコン）と同程度の熱膨張係数を持つ多結晶シリコン
膜の側面と表面をシリコン窒化膜で被い、この多結晶シ
リコン膜を酸化マスクとして、多結晶シリコン膜で被れ
ていない領域を酸化する。また、多結晶シリコン膜で被
れていない領域の半導体基板を酸化前に、ある程度つま
り厚いＬＯＧＯ３酸化膜の概ね半分の厚みに相当する量
をエツチングしておく。In order to solve the above problems, this invention provides a semiconductor substrate (
The sides and surface of a polycrystalline silicon film, which has a thermal expansion coefficient similar to that of silicon (silicon), are covered with a silicon nitride film, and the areas not covered with the polycrystalline silicon film are oxidized using this polycrystalline silicon film as an oxidation mask. . Further, before oxidizing the semiconductor substrate in the area not covered with the polycrystalline silicon film, a certain amount, that is, an amount corresponding to approximately half the thickness of the thick LOGO3 oxide film, is etched.
シリコン基板と熱膨張係数の等しい多結晶シリコン膜を
側壁シリコン窒化膜を酸化マスクとして使用しているか
ら、バーズ・ピークが小さく欠陥の少ない素子分離が可
能となる。またＬＯＧＯ３酸化前に半導体基板を相当量
エツチングしているため、素子分離領域と活性領域の段
差を小さくする事ができる。Since a polycrystalline silicon film having the same coefficient of thermal expansion as the silicon substrate is used and a sidewall silicon nitride film is used as an oxidation mask, element isolation with small bird peaks and fewer defects is possible. Furthermore, since the semiconductor substrate is etched to a considerable extent before LOGO3 oxidation, the step difference between the element isolation region and the active region can be reduced.
本発明の実施例を第１図＋ａｌ〜（ａに示す。第１図ｔ
ａ＋に示す様にシリコン（Ｓｔ）などの半導体基板ｌの
上に絶縁膜２を積層する。この半導体基板１はもちろん
シリコン以外の半導体基板でもよい０例えば、砒化ガリ
ウム（ＧａＡｓ）インジウムリン（１，Ｐ）等の化合物
半導体でもよい、また絶縁膜２は一般にはシリコン酸化
膜であり、酸化法でも化学気相成長（ＣＶＤ）法でも物
理成長法（ＰＶＤ）でも成長できる。このシリコン酸化
膜２は緩衝（パッド）酸化膜とも言われ、後工程のフィ
ールド酸化の時に半導体基板中に誘発する応力を緩和す
る働きを持っている０選択酸化（ＬＯＧＯ３）法におい
てこのシリコン酸化膜２が厚いほどバーズビークは長く
なる傾向にある。逆にシリコン酸化膜２が薄いほどバー
ズビークは短くなるが、一方で半導体基板中に欠陥密度
が多くなる０次にシリコン酸化膜２の上に多結晶シリコ
ン膜３を成長させる。この多結晶シリコン膜３の上にさ
らにシリコン窒化膜４を積層する。多結晶シリコン膜３
はＣＶＤ法でもＰＶＤ法でも積層する事ができる。ＣＶ
Ｄ法の場合多結晶シリコンｌｌ！３はシランガス（Ｓｉ
Ｈｔ）またはジシランガス（Ｓｉｔｅｓ）またはトリシ
ラン（ＳｉＪｓ）等のシラン系ガス（Ｓｉ＋ｍＨｎ）を
用いた化学気相成長で形成される。またシリコン窒化膜
４もＣＶＤ法でもＰＶＤ法でも積層する事ができる。Ｃ
ＶＤ法の場合、シリコン窒化膜４はジクロルシランガス
（ＳｉＨｚＣｌｇ）とアンモニアガス（ＮＨｓ）との反
応により、またはシランガス（ＳｉＨｔ）とアンモニア
ガス（ＮＨ；）との反応により形成される０次に第１回
申）に示す様に、上記のシリコン窒化膜４と多結晶シリ
コン膜３とシリコン酸化膜２を写真食刻法等の方法を用
いて選択的にエツチング除去する。すなわち、素子分離
領域となる部分のシリコン窒化膜４および多結晶シリコ
ンＷ１４３およびシリコン酸化膜２をエツチング除去す
る。このエツチングは湿式法でも良いがサイドエツチン
グの少ない乾式法がより良い、乾式法の中で特に異方性
の大きい反応性イオンエツチング（通称ＲｒＥ）やプラ
ズマエツチング（通称ＰＰＥ）が好ましい、３ミクロン
以下の微細なパターンを作成するにはこの異方性エツチ
ングが特に必要となる。また、シリコン酸化膜２は一般
には５００Å以下と薄いので湿式法でエツチングしても
特に問題はない、シリコン窒化膜４と多結晶シリコンＩ
ｔ！３とシリコン酸化１ｌ１２とを別々のエツチング装
置でエツチングしても良いし、同一のエツチング装置を
用いて連続的にエツチングしても良い。シリコン窒化膜
４と多結晶シリコン［３をエツチング除去しない部分は
将来活性領域となる０次に第１図（Ｃ１に示す様にシリ
コン窒化［４等の薄膜が除去され、シリコン等の半導体
基板１の露出した部分の半導体基板をエツチングする。Embodiments of the present invention are shown in Fig. 1+al to (a).
As shown at a+, an insulating film 2 is laminated on a semiconductor substrate l made of silicon (St) or the like. Of course, this semiconductor substrate 1 may be a semiconductor substrate other than silicon.For example, it may be a compound semiconductor such as gallium arsenide (GaAs) or indium phosphide (1,P).The insulating film 2 is generally a silicon oxide film, and the oxidation method However, it can be grown using either chemical vapor deposition (CVD) or physical growth (PVD). This silicon oxide film 2 is also called a buffer (pad) oxide film, and this silicon oxide film is used in the zero selective oxidation (LOGO3) method, which has the function of relieving stress induced in the semiconductor substrate during field oxidation in the later process. The thicker the number 2, the longer the bird's beak tends to be. Conversely, the thinner the silicon oxide film 2, the shorter the bird's beak, but on the other hand, the polycrystalline silicon film 3 is grown on the zero-order silicon oxide film 2, which increases the defect density in the semiconductor substrate. A silicon nitride film 4 is further laminated on this polycrystalline silicon film 3. Polycrystalline silicon film 3
can be laminated by CVD or PVD. CV
In case of method D, polycrystalline silicon ll! 3 is silane gas (Si
It is formed by chemical vapor deposition using a silane-based gas (Si+mHn) such as Ht) or disilane gas (Sites) or trisilane (SiJs). Further, the silicon nitride film 4 can also be deposited by CVD or PVD. C
In the case of the VD method, the silicon nitride film 4 is formed by a reaction between dichlorosilane gas (SiHzClg) and ammonia gas (NHs) or a reaction between silane gas (SiHt) and ammonia gas (NH). As shown in step 1), the silicon nitride film 4, polycrystalline silicon film 3, and silicon oxide film 2 are selectively etched away using a method such as photolithography. That is, the silicon nitride film 4, polycrystalline silicon W143, and silicon oxide film 2 in portions that will become element isolation regions are removed by etching. This etching can be done by a wet method, but a dry method with less side etching is better.Among the dry methods, reactive ion etching (commonly known as RrE) and plasma etching (commonly known as PPE), which have a large anisotropy, are particularly preferable. This anisotropic etching is especially necessary to create fine patterns. Furthermore, since the silicon oxide film 2 is generally thin, 500 Å or less, there is no particular problem even if it is etched by a wet method.
T! 3 and silicon oxide 1l12 may be etched using separate etching apparatuses, or may be etched continuously using the same etching apparatus. The area where the silicon nitride film 4 and the polycrystalline silicon film 4 are not removed by etching will become an active region in the future. Next, as shown in FIG. The exposed portion of the semiconductor substrate is etched.
この半導体基板のエツチングの目的は選択酸化を行った
後に発生する活性領域と素子分離領域との段差を小さく
する事とバーズビークを少なくする事および半導体基板
中の欠陥を低減する事である。この半導体基板ｌのエツ
チングに際し、活性領域となるべき部分のシリコン窒化
［４の上に存在するレジスト等のマスク材料はあっても
良い事はもちろんである。The purpose of this etching of the semiconductor substrate is to reduce the step difference between the active region and the element isolation region that occurs after selective oxidation, to reduce bird's beaks, and to reduce defects in the semiconductor substrate. Of course, when etching the semiconductor substrate 1, there may be a mask material such as a resist present on the silicon nitride [4] in the portion that is to become the active region.
ただ、第１開山）と（Ｃ１との間に酸化等の熱処理工程
が入る場合はレジスト等のマスク材料は除去されねばな
らない、第１図（Ｃ）におけるシリコンエツチングの方
法として、湿式法と乾式法がある。湿式法の場合、シリ
コン等の半導体基板を異方的にエツチングするエツチン
グ液が望ましい、たとえば、水酸化カリウム等のアルカ
リ液でエツチングする事により異方的にエツチングでき
る。However, if a heat treatment process such as oxidation is performed between C1 and C1, the mask material such as resist must be removed. In the case of the wet method, an etching solution that etches a semiconductor substrate such as silicon anisotropically is preferable. For example, etching can be performed anisotropically by etching with an alkaline solution such as potassium hydroxide.
また、乾式法の場合、特に異方性エツチング可能なＲｒ
ＥやＰＰＥが用いられる。シリコン等の半導体基板中を
エツチングする量は、将来選択酸化した時に活性領域と
素子分離領域とが平坦になる様に選ばれた量である０例
えは半導体基板１がシリコンの場合、素子骨ＭｅＨ域の
フィールド酸化膜の厚みが６０００人ならば、シリコン
基板をエツチングする量は約３０００人となる。In addition, in the case of the dry method, especially Rr, which can be anisotropically etched,
E and PPE are used. The amount of etching in the semiconductor substrate such as silicon is selected so that the active region and the element isolation region will be flat when selectively oxidized in the future.For example, if the semiconductor substrate 1 is silicon, the element bone MeH If the thickness of the field oxide film in the area is 6000 mm, the amount of silicon substrate to be etched will be approximately 3000 mm.
次に第１図（ｄ＋に示す様に、第２のシリコン窒化Ｉ！
＊６を積層する。この窒化膜６も窒化膜４と同様にＣＶ
Ｄ法またはＰＶＤ法等の方法により形成できる。次に異
方性の強いドライエツチング法（ＲＩＥまたはＰＰＥま
たはイオンシリング、またはスパックエツチング等の方
法）を用いて第２のシリコン窒化［６を全面エツチング
する。この時素子分Ｍ ｆｉｌ域となる部分の窒化膜は
完全にエツチング除去する事が望ましい、この異方性エ
ツチングより平坦部のシリコン窒化膜６はすべてエツチ
ングされるが、多結晶シリコン膜３の側壁部分のシリコ
ン窒化膜６の厚みは厚いので、多結晶シリコン膜３の側
壁にシリコン窒化膜６はスペーサーとして残っている。Next, as shown in FIG. 1 (d+), a second silicon nitride I!
Layer *6. This nitride film 6 also has a CV similar to the nitride film 4.
It can be formed by a method such as the D method or the PVD method. Next, the second silicon nitride [6] is etched over the entire surface using a highly anisotropic dry etching method (such as RIE, PPE, ion silling, or spack etching). At this time, it is desirable to completely remove the nitride film in the M fil region of the device by etching.Through this anisotropic etching, all of the silicon nitride film 6 in the flat area is etched away, but the sidewalls of the polycrystalline silicon film 3 are completely etched away. Since the silicon nitride film 6 is partially thick, the silicon nitride film 6 remains on the side wall of the polycrystalline silicon film 3 as a spacer.
この様子は第１図ｔｅｌに示されている。This situation is shown in FIG.
次に酸化雰囲気の中で酸化を行うと第１図（ｆ）に示す
様に、窒化膜で被れた多結晶シリコン膜３がある部分以
外の領域には厚い酸化膜７が成長するが、窒化膜で被れ
た多結晶シリコン膜のある領域は窒化膜が酸化マスクと
なる為、酸化膜は成長しない。特にスペーサーとして残
っている第２の窒化膜６は横方向への酸化を防止する。Next, when oxidation is performed in an oxidizing atmosphere, as shown in FIG. 1(f), a thick oxide film 7 grows in the area other than the area where the polycrystalline silicon film 3 covered with the nitride film is located. Since the nitride film serves as an oxidation mask in a certain region of the polycrystalline silicon film covered with the nitride film, the oxide film does not grow. In particular, the second nitride film 6 remaining as a spacer prevents oxidation in the lateral direction.
これにより横方向酸化であるバーズビークは非常に小さ
くなる。その後、酸化時に窒化膜上に薄く成長した酸化
膜、シリコン窒化膜６および４、多結晶シリコン膜３お
よび緩衝用酸化膜２を順次除去し、第１図＋ｇ＋に示す
様に活性（素子） ＳＪ域８と素子分離領域９が形成さ
れる。その後、活性領域８にはトランジスタなどの能動
素子が形成され、ＩＣが作成される。As a result, the bird's beak caused by lateral oxidation becomes very small. Thereafter, the oxide film thinly grown on the nitride film during oxidation, the silicon nitride films 6 and 4, the polycrystalline silicon film 3, and the buffer oxide film 2 are sequentially removed to form an active (device) SJ as shown in FIG. A region 8 and an isolation region 9 are formed. Thereafter, active elements such as transistors are formed in the active region 8, and an IC is manufactured.
第１図（ａｌ〜（幻に示さなかったが、第１図ｆｃｌで
示す工程または第１図（ｄｌで示す工程または第１図ｆ
ｅ＋で示す工程の後にフィールド領域反転防止用のイオ
ン注入を行ってもよい。Figure 1 (al ~ (Although not shown in the illusion, the process shown in Figure 1 fcl or the process shown in Figure 1 (dl) or the process shown in Figure 1 f
Ion implantation for preventing field region inversion may be performed after the step indicated by e+.
多結晶シリコン膜３は半導体基板であるシリコンと同一
の組成である為、物理的性質が類似している。第１図［
ｆｌに示す選択酸化の時に、酸化マスク材料と基板材料
の熱膨張係数が大きく異なると半導体基板内に欠陥が誘
起されやすくなるが、本発明では酸化マスクの主材料に
多結晶シリコン膜を用いている為、熱歪が小さく半導体
基板１内に欠陥は発生しにくくなる。また側壁シリコン
窒化膜のために横方向酸化は殆ど起こらず、バーズビー
クの小さい素子分離が形成される。さらに緩衝用シリコ
ン酸化膜２も従来より薄くする事ができ、これによるバ
ーズビークの減少も期待できる。Since the polycrystalline silicon film 3 has the same composition as the silicon that is the semiconductor substrate, it has similar physical properties. Figure 1 [
During the selective oxidation shown in fl, defects are likely to be induced in the semiconductor substrate if the thermal expansion coefficients of the oxidation mask material and the substrate material differ greatly; however, in the present invention, a polycrystalline silicon film is used as the main material of the oxidation mask. Therefore, thermal strain is small and defects are less likely to occur in the semiconductor substrate 1. Further, because of the sidewall silicon nitride film, lateral oxidation hardly occurs, and device isolation with small bird's beaks is formed. Furthermore, the buffer silicon oxide film 2 can be made thinner than before, and a reduction in bird's beak can be expected as a result.
通常のＬＯＣＯ３法では緩衝用シリコン酸化膜２の厚み
は５００〜１０００人であるが、本発明を用いると３０
〜１０００人の厚みにできる。また多結晶シリコン膜３
の厚みは厚いほどバーズビークが小さくなるが、実用上
３００〜６０００人が好ましい。またシリコン窒化膜４
の厚みはシリコン窒化膜６のオーバーエツチングしても
充分残っているだけの厚みとかつフィールド酸化時に多
結晶シリコン膜３が酸化しないだけの厚みとを有してい
ればよい、さらにシリコン窒化膜６の厚みも厚いほど側
壁の厚みも厚くなりバーズビークを小さくする。しかし
実用的には３００〜３０００人が好ましい、−例として
、緩衝用シリコン酸化膜２を２００人、多結晶シリコン
膜３を４０００人、シリコン窒化膜４を１５００人、シ
リコン窒化膜６を１５００人、シリコンエツチングをＫ
ＯＨで３０００人行い、フィールド酸化膜７を６０００
大成長させた時のバーズビークは０．２μ以下となり、
はぼパターン寸法通りの活性領域と素子分離領域ができ
る。また活性領域と素子骨ＭＨ域の段差は５００Å以下
となり良好な平坦性も得られている。さらにこの時の欠
陥密度も非常に小さく１．従来のＬＯＣＯ３法と同程度
の良好な素子分離特性を示した。In the normal LOCO3 method, the thickness of the buffer silicon oxide film 2 is 500 to 1000 mm, but with the present invention, the thickness is 30 mm.
It can be made up to 1000 people deep. Also, polycrystalline silicon film 3
The thicker the bird's beak, the smaller the bird's beak, but for practical purposes it is preferably 300 to 6,000. Also, silicon nitride film 4
The thickness of the silicon nitride film 6 only needs to be thick enough to remain even after over-etching the silicon nitride film 6, and thick enough to prevent the polycrystalline silicon film 3 from being oxidized during field oxidation. The thicker the side wall is, the thicker the side wall becomes, making the bird's beak smaller. However, in practical terms, it is preferable to have 300 to 3,000 people; for example, 200 people for the buffer silicon oxide film 2, 4,000 people for the polycrystalline silicon film 3, 1,500 people for the silicon nitride film 4, and 1,500 people for the silicon nitride film 6. , silicone etching
3000 people conducted OH, 6000 people formed field oxide film 7
The bird's beak will be less than 0.2 μ when grown to a large size.
An active region and an element isolation region can be formed according to the dimensions of the dowel pattern. Further, the step difference between the active region and the element bone MH region is less than 500 Å, and good flatness is also obtained. Furthermore, the defect density at this time is also very small.1. It showed good element isolation characteristics comparable to the conventional LOCO3 method.
この発明は以上説明したように、シリコン窒化膜で表面
および側壁を破れた多結晶シリコン膜を酸化マスクとし
て選択酸化する事により、欠陥も少なく、バーズビーク
も非常に小さい良好な素子分離を実現できる。As described above, this invention can achieve good element isolation with few defects and very small bird's beaks by selectively oxidizing a polycrystalline silicon film whose surface and sidewalls are broken with a silicon nitride film as an oxidation mask.
第１図（ａｌ〜（幻はこの発明の製造方法の工程順を示
す断面図、第２図＋ａｌ〜（ｄ）は従来の製造方法の工
程順を示す断面図である。
１．１）・・・半導体基板
２．１２・・・シリコン酸化膜
３・・・・・多結晶シリコン膜
４，１３・・・ （第１の）シリコン窒化膜６・・・・
・ （第２の）シリコン窒化膜７．１５・・・シリコン
酸化膜（フィールド酸化膜）
１４・・・・・レジスト
７．１７・・・活性領域
８．１６・・・素子骨ｉ！１）１ｗｔ域以上
出願人 セイコー電子工業株式会社
代理人 弁理士 最 上 務（他１名）（Ｃ）（り）FIG. 1(al~(phantom) is a sectional view showing the process order of the manufacturing method of the present invention, FIG. 2+al~(d) is a sectional view showing the process order of the conventional manufacturing method. 1.1)・...Semiconductor substrate 2.12...Silicon oxide film 3...Polycrystalline silicon film 4, 13...(First) silicon nitride film 6...
- (Second) silicon nitride film 7.15...Silicon oxide film (field oxide film) 14...Resist 7.17...Active region 8.16...Element bone i! 1) Applicant for 1wt range or above Seiko Electronic Industries Co., Ltd. Agent Patent Attorney Tsumugi Mogami (1 other person) (C) (Ri)
Claims (7)
膜上に多結晶シリコン膜を形成する工程と、前記多結晶
シリコン膜上に第１のシリコン窒化膜を形成する工程と
、前記第１のシリコン窒化膜と前記多結晶シリコン膜と
前記絶縁膜と半導体基板を選択的に順次エッチングする
工程と、第２のシリコン窒化膜を積層する工程と、前記
第２のシリコン窒化膜を異方性エッチングし前記多結晶
シリコン膜の側壁に前記第２のシリコン窒化膜のスペー
サを形成する工程と、前記第１のシリコン窒化膜および
前記第２のシリコン窒化膜から破れた前記多結晶シリコ
ン膜を酸化マスクとして多結晶シリコン膜で被れていな
い領域を酸化する工程と、前記第１および第２のシリコ
ン窒化膜上の酸化膜と前記第１および第２のシリコン窒
化膜と多結晶シリコン膜と前記絶縁膜とを順次除去する
事により、酸化膜で被れた領域と酸化膜のない領域を形
成する工程と、を含む事を特徴とする半導体装置の素子
分離形成方法。(1) a step of forming an insulating film on a semiconductor surface; a step of forming a polycrystalline silicon film on the insulating film; a step of forming a first silicon nitride film on the polycrystalline silicon film; a step of selectively sequentially etching the first silicon nitride film, the polycrystalline silicon film, the insulating film, and the semiconductor substrate; a step of stacking a second silicon nitride film; and an anisotropic etching of the second silicon nitride film. forming a spacer of the second silicon nitride film on the side wall of the polycrystalline silicon film by etching; and removing the polycrystalline silicon film broken from the first silicon nitride film and the second silicon nitride film. oxidizing a region not covered with the polycrystalline silicon film as an oxidation mask; and oxidizing the oxide film on the first and second silicon nitride films, the first and second silicon nitride films, and the polycrystalline silicon film. A method for forming element isolation in a semiconductor device, comprising the step of sequentially removing the insulating film to form a region covered with an oxide film and a region without an oxide film.
の範囲第１項記載の半導体装置の素子分離形成方法。(2) A method for forming element isolation in a semiconductor device according to claim 1, wherein the semiconductor is silicon.
シリコン酸化膜である事を特徴とする特許請求の範囲第
１項記載の半導体装置の素子分離形成方法。(3) The method for forming element isolation in a semiconductor device according to claim 1, wherein the insulating film is a silicon oxide film with a thickness of 30 to 1000 Å formed on the semiconductor surface.
有する事を特徴とする特許請求の範囲第１項記載の半導
体装置の素子分離形成方法。(4) The method for forming element isolation of a semiconductor device according to claim 1, wherein the polycrystalline silicon film has a thickness of 300 to 6000 Å.
Åである事を特徴とする特許請求の範囲第１項記載の半
導体装置の素子分離形成方法。(5) The thickness of the first silicon nitride film is 300 to 2000
3. The method for forming element isolation in a semiconductor device according to claim 1, wherein .ANG.
厚みの０．４〜０．６の間にある事を特徴とする特許請
求の範囲第１項記載の半導体装置の素子分離形成方法。(6) A method for forming element isolation in a semiconductor device according to claim 1, wherein the amount of etching of the semiconductor substrate is between 0.4 and 0.6 of the thickness of the oxide film for element isolation.
Åである事を特徴とする特許請求の範囲第１項記載の半
導体装置の素子分離形成方法。(7) The thickness of the second silicon nitride film is 300 to 3000
3. The method for forming element isolation in a semiconductor device according to claim 1, wherein .ANG.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10537287A JPS63271956A (en) | 1987-04-28 | 1987-04-28 | Formation of element isolation of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10537287A JPS63271956A (en) | 1987-04-28 | 1987-04-28 | Formation of element isolation of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63271956A true JPS63271956A (en) | 1988-11-09 |
Family
ID=14405867
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10537287A Pending JPS63271956A (en) | 1987-04-28 | 1987-04-28 | Formation of element isolation of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63271956A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02164037A (en) * | 1988-12-19 | 1990-06-25 | Nec Corp | Selecting oxidative separation |
| JPH07302836A (en) * | 1992-10-13 | 1995-11-14 | Hyundai Electron Ind Co Ltd | Field oxidized film formation of semiconductor device |
| WO1996029731A1 (en) * | 1995-03-17 | 1996-09-26 | Hitachi, Ltd. | Semiconductor device and method of manufacturing the same |
| US7235460B2 (en) | 1993-07-30 | 2007-06-26 | Stmicroelectronics, Inc. | Method of forming active and isolation areas with split active patterning |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS587839A (en) * | 1981-07-07 | 1983-01-17 | Toshiba Corp | Manufacture of semiconductor device |
| JPS5976472A (en) * | 1982-10-26 | 1984-05-01 | Toshiba Corp | Manufacture of semiconductor device |
| JPS59202649A (en) * | 1983-05-02 | 1984-11-16 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS62211938A (en) * | 1986-03-12 | 1987-09-17 | Fujitsu Ltd | Manufacture of semiconductor device |
-
1987
- 1987-04-28 JP JP10537287A patent/JPS63271956A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS587839A (en) * | 1981-07-07 | 1983-01-17 | Toshiba Corp | Manufacture of semiconductor device |
| JPS5976472A (en) * | 1982-10-26 | 1984-05-01 | Toshiba Corp | Manufacture of semiconductor device |
| JPS59202649A (en) * | 1983-05-02 | 1984-11-16 | Matsushita Electric Ind Co Ltd | Manufacture of semiconductor device |
| JPS62211938A (en) * | 1986-03-12 | 1987-09-17 | Fujitsu Ltd | Manufacture of semiconductor device |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02164037A (en) * | 1988-12-19 | 1990-06-25 | Nec Corp | Selecting oxidative separation |
| JPH07302836A (en) * | 1992-10-13 | 1995-11-14 | Hyundai Electron Ind Co Ltd | Field oxidized film formation of semiconductor device |
| US7235460B2 (en) | 1993-07-30 | 2007-06-26 | Stmicroelectronics, Inc. | Method of forming active and isolation areas with split active patterning |
| WO1996029731A1 (en) * | 1995-03-17 | 1996-09-26 | Hitachi, Ltd. | Semiconductor device and method of manufacturing the same |
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