JPS59202649A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS59202649A
JPS59202649A JP7776583A JP7776583A JPS59202649A JP S59202649 A JPS59202649 A JP S59202649A JP 7776583 A JP7776583 A JP 7776583A JP 7776583 A JP7776583 A JP 7776583A JP S59202649 A JPS59202649 A JP S59202649A
Authority
JP
Japan
Prior art keywords
film
substrate
oxidation
si3n4
films
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7776583A
Other languages
Japanese (ja)
Inventor
Kazuya Kikuchi
菊池 和也
Masaru Sasago
勝 笹子
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP7776583A priority Critical patent/JPS59202649A/en
Publication of JPS59202649A publication Critical patent/JPS59202649A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region

Abstract

PURPOSE:To form an insulating film functioning as an isolating section in a recessed section, to remove a steep groove and to form a surface approximately flat to the surface of a semiconductor substrate by leaving a second anti-oxidation film only to the side surface section of the recessed section and selectively oxidizing the substrate while using first and second anti-oxidation films as masks. CONSTITUTION:A thin SiO2 film 16 is formed on the surface of a recessed section 15 while using a Si3N4 film 13 as a mask. A Si3N4 film 17 is formed, and the Si3N4 film 17 remains only on the side surface section of the recessed section 15 through anisotropic dry etching. An isolation SiO2 film 18 is shaped through selective oxidation while employing the Si3N4 films 13 and 17 as masks. Sections among the Si3N4 film 17, a Si substrate 10 and a poly Si film 12 are also oxidized to some extent to form a SiO2 film 18' at that time, and the Si3N4 film 17 is pushed up in the upper direction. When the Si3N4 films 13, 17, the poly Si film 12 and SiO2 films 11, 18' are etched through isotropic dry etching, the isolation SiO2 film 18 with a surface approximately flat to the Si substrate 10 is formed.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置の製造方法、特に半導体装置の素子
分離領域の形成方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming an isolation region of a semiconductor device.

従来例の構成とその問題点 従来、半導体装置の製造における素子分離領域の形成方
法として、シリコン窒化膜(S13N4膜)を酸化防止
マスクにして選択酸化法によって分離絶縁膜を形成する
方法がある。しかし、半導体基板(Si基板)表面にS
i3N4膜パターンを形成して選択酸化するとSi3N
4膜パターンのエツジ部の下も酸化され、いわゆるバー
ズビーク、バーズヘッドが発生する。そのだめ、バーズ
ビーク、バーズヘッドの発生をなくするために、選択酸
化する領域の凹部の側面にもSi3N4膜を形成して選
択酸化する方法がちも。その従来例の一例を第1図によ
り説明する。
Conventional Structure and Problems Conventionally, as a method for forming element isolation regions in the manufacture of semiconductor devices, there is a method of forming an isolation insulating film by selective oxidation using a silicon nitride film (S13N4 film) as an oxidation prevention mask. However, S on the surface of the semiconductor substrate (Si substrate)
When an i3N4 film pattern is formed and selectively oxidized, Si3N
The bottom of the edge portion of the four-layer pattern is also oxidized, resulting in so-called bird's beaks and bird's heads. However, in order to eliminate the occurrence of bird's beaks and bird's heads, the method of selective oxidation is to form a Si3N4 film on the side surface of the recess in the area to be selectively oxidized. An example of the conventional example will be explained with reference to FIG.

Si基板1上にシリコン酸化膜(S z O2膜)2及
び513N4膜3を形成した後、ホトエツチング技術に
より所定の分離領域のSi3N4膜3、SiO2膜2及
びSi基板1を所望の深さ1てエツチングして凹部4を
形成する。次に、Si3N4模3を酸化防止マスクにし
て凹部4の表面に薄いSio2膜5を形成する。その後
、上記Si基板1上にSi3N4膜6を形成し、異方性
のエツチングにより凹部4の底面部の813N’4膜6
をエツチングすると凹部4の側面にのみ513N4、嘆
6が残存する(第1図a)。
After forming a silicon oxide film (S z O2 film) 2 and a 513N4 film 3 on a Si substrate 1, the Si3N4 film 3, SiO2 film 2 and Si substrate 1 in a predetermined isolation region are etched to a desired depth 1 using photoetching technology. A recess 4 is formed by etching. Next, a thin Sio2 film 5 is formed on the surface of the recess 4 using the Si3N4 pattern 3 as an oxidation prevention mask. Thereafter, a Si3N4 film 6 is formed on the Si substrate 1, and the 813N'4 film 6 on the bottom of the recess 4 is etched by anisotropic etching.
When etched, 513N4 and groove 6 remain only on the side surface of the recess 4 (Fig. 1a).

その後、813N4 B[3、6を1浚化防止マスクに
して選択酸化すれは第11g1bの如く、分離となるS
 1021i弥7が形成される。
After that, selective oxidation is performed using 813N4 B[3 and 6 as a mask to prevent dredging, as shown in No. 11g1b, S which becomes separated.
1021i Ya7 is formed.

、−h配薬1図の方法によるとバーズビーク、バーズヘ
ッドの発生はおさえられる。しかし、第1図すの如く、
5iO2j1棹70表面をS1基板1表面とほぼ平坦に
なるまで酸化すると、Si3N4膜6によって酸化がお
さえられるS 102膜7の周辺に溝8ができる。この
ような満8があるとハを配線パターンを形成した際、溝
8にAtが残ってしまい、ショートが生じることがある
。ショートを防ぐためにはAtのオーバーエッチを長く
すれはよいが、そうすると他のAl配線部がサイドエッ
チをおこし、設計に対して非常に精度の悪いものとなっ
てしまう。特に超LSI化を図る上でAl配線の微細加
工は重要なので、この急峻な溝8は超LSIの高密度化
の点で大きな障害となってくる。
, -h Medication Distribution 1 According to the method shown in Figure 1, the occurrence of bird's beak and bird's head can be suppressed. However, as shown in Figure 1,
When the surface of the 5iO2j1 rod 70 is oxidized until it becomes almost flat with the surface of the S1 substrate 1, a groove 8 is formed around the S102 film 7 whose oxidation is suppressed by the Si3N4 film 6. If there is such a full 8, when a wiring pattern is formed, At may remain in the groove 8, causing a short circuit. In order to prevent short-circuits, it is better to make the At overetch longer, but this will cause side etching of other Al wiring parts, resulting in extremely poor design accuracy. In particular, since microfabrication of Al wiring is important in realizing ultra-LSI, the steep groove 8 becomes a major obstacle in increasing the density of ultra-LSI.

また、酸化が促進されるにつれてS iO2膜7の体積
膨張によるストレスがSi基板1、特に凹部4のエツジ
9に加わり、その結果結晶欠陥が多く発生し、トランジ
スタの歩留りを悪くする要因となる。
Further, as oxidation is promoted, stress due to the volumetric expansion of the SiO2 film 7 is applied to the Si substrate 1, particularly the edges 9 of the recesses 4, resulting in the occurrence of many crystal defects, which becomes a factor that reduces the yield of transistors.

ところで、本発明者の検討によれば、第2図の如く、選
択酸化を途中で止めればSi○2膜7′には溝が発生し
ておらず、Si基板1にもストレスによる結晶欠陥の発
生していないことを見い出した。すなわち、Si3N4
膜6とS1基板1との間も多少酸化され、形成されたS
i○2膜7″によって813N4膜6が上部方向に押し
上げられる。
By the way, according to the study of the present inventor, as shown in FIG. 2, if the selective oxidation is stopped midway, grooves will not be generated in the Si○2 film 7', and the Si substrate 1 will also be free from crystal defects due to stress. I found that it did not occur. That is, Si3N4
The gap between the film 6 and the S1 substrate 1 is also oxidized to some extent, and the formed S
The 813N4 film 6 is pushed upward by the i○2 film 7''.

そのため、この段階では、溝の発生は見られなかった。Therefore, no grooves were observed at this stage.

しかも、ストレスも少ないので結晶欠陥の発生も見られ
なかった。しかし、S i 02膜7′の表面とSt基
板1表面を平坦にするために、さらに酸化を促進し、第
1図すの如く構造まで酸化すると溝8が発生し、ストレ
スによふ結晶欠陥が多数発生していた。なぜならば第2
図の、溝端後、さらに酸化を促進した場合、Si3N4
膜6とSi基板1との間のSiC膜7”は513N4膜
3と513N4膜6によって酸化がおさえられるため厚
くならない。そのため、Si3N4膜6ば、これ以上上
部方向に押し上げられない。従って、凹部4の底部だけ
が酸化が進み、第1図すの如く513N4膜6によって
酸化がおさえられたところに溝8が発生してし甘う。し
かも、このときの酸化の促進により、第1図すのエツジ
部9にストレスが加わり、結晶欠陥が発生する。
Moreover, since the stress was low, no crystal defects were observed. However, in order to flatten the surface of the Si02 film 7' and the surface of the St substrate 1, oxidation is further promoted, and when the structure is oxidized as shown in Figure 1, grooves 8 are generated and crystal defects due to stress occur. were occurring in large numbers. Because the second
In the figure, if oxidation is further promoted after the groove edge, Si3N4
The SiC film 7'' between the film 6 and the Si substrate 1 does not become thicker because oxidation is suppressed by the 513N4 film 3 and the 513N4 film 6. Therefore, the Si3N4 film 6 cannot be pushed upward any further. Oxidation progresses only at the bottom of the 513N4 film 6, as shown in Figure 1, and grooves 8 are formed where oxidation has been suppressed by the 513N4 film 6.Furthermore, due to the promotion of oxidation at this time, Stress is applied to the edge portion 9 of the crystal, causing crystal defects.

すなわち、酸化の促進に応じて513N4膜6が」二部
方向に押し上げられれば、溝の発生がないととが判明し
た。
In other words, it has been found that if the 513N4 film 6 is pushed up in the two-part direction as oxidation is promoted, no grooves are formed.

発明の目的 本発明はこのような従来の問題に鑑み、急峻な溝がなく
、半導体基板表面とほぼ平坦な表面を有する絶縁分離膜
となるシリコン酸化膜が形成でき、しかも、半導体基板
に加わるストレスを小さくし、結晶欠陥の少ない半導体
装置の製造方法を提供することを目的とするものである
Purpose of the Invention In view of these conventional problems, the present invention is capable of forming a silicon oxide film as an insulating separation film that has no steep grooves and has a surface that is almost flat with the surface of a semiconductor substrate, and that also reduces the stress applied to the semiconductor substrate. It is an object of the present invention to provide a method for manufacturing a semiconductor device with small crystal defects.

発明の構成 本発明は、半導体基板上に第1の絶縁膜、半導体膜及び
第1の酸化防止膜を順次形成した後、所定の領域の第1
の酸化防止膜、半導体膜、第1の絶縁膜及び半導体基板
を所望の深さだけエツチングして四部を形成する。次に
、第1の酸化防止膜をマスクにして四部表面に薄い第2
の絶縁膜を形成した後、前記半導体基板上に第2の酸化
防止膜を形成する。その後、異方性のエツチングにより
、四部の側面部のみに第2の酸化防止膜を残存させ、第
1及び第2の酸化防止膜をマスクにして選択酸化するこ
とによって凹部内に分割となる絶縁膜を形成するという
独特の方法を用いていることを特徴とするものである。
Structure of the Invention The present invention provides a first insulating film, a semiconductor film, and a first anti-oxidation film in a predetermined region after sequentially forming a first insulating film, a semiconductor film, and a first anti-oxidation film on a semiconductor substrate.
The anti-oxidation film, the semiconductor film, the first insulating film, and the semiconductor substrate are etched to a desired depth to form four parts. Next, using the first anti-oxidation film as a mask, a thin second film is applied to the surface of the four parts.
After forming the insulating film, a second anti-oxidation film is formed on the semiconductor substrate. After that, by anisotropic etching, the second oxidation-preventing film remains only on the four side surfaces, and selective oxidation is performed using the first and second oxidation-preventing films as masks, thereby forming the insulation that is divided into the recesses. It is characterized by the use of a unique method of forming a film.

すなわち、素子分離領域形成において、素子分離領域と
なる凹部以外の半導体基板上に半導体膜を形成しておく
0そうすれば、凹部内の分離絶縁膜を半導体基板表面と
ほぼ平坦になるまで酸化で形成しても第2の酸化防止膜
は半導体膜が酸化されることにより上部方向に押し上げ
られるため分離絶縁膜に溝ができない。しかも、第2の
酸化防止膜を押し上げる際のストレスは半導体膜に加わ
るため、半導体基板にはストレスが加わらず結晶欠陥が
発生しないというものである。以下図面を用いて詳細に
説明する。
In other words, when forming an element isolation region, a semiconductor film is formed on the semiconductor substrate other than the recess that will become the element isolation region.In this way, the isolation insulating film in the recess can be oxidized until it becomes almost flat with the semiconductor substrate surface. Even if the second oxidation prevention film is formed, the second oxidation prevention film is pushed upward as the semiconductor film is oxidized, so that a groove is not formed in the isolation insulating film. Moreover, since stress is applied to the semiconductor film when pushing up the second oxidation-preventing film, stress is not applied to the semiconductor substrate and no crystal defects occur. This will be explained in detail below using the drawings.

実施例の説! 第3図は本発明にかかる素子分離を形成する半導体装置
の製造方法の第1の実施例を示す。
Example theory! FIG. 3 shows a first embodiment of the method for manufacturing a semiconductor device forming element isolation according to the present invention.

Si基板10上に絶縁膜例えばSi○2膜11゜半導体
膜例えば多結晶ンリコン膜(Poly Si膜)12及
び酸化防止膜例えばSi3N4膜13を順次形成する。
On the Si substrate 10, an insulating film such as a Si◯2 film 11°, a semiconductor film such as a polycrystalline silicon film (PolySi film) 12, and an oxidation prevention film such as a Si3N4 film 13 are successively formed.

その後、ホトリソ技術により分離領域以外の領域上にホ
トレジストパターン14を形成する。そして、ホトレジ
ストパターン14をマスクにして異方性のドライエツチ
ングによって513N4膜13 、 Po1y Si膜
12 、 S 102膜11及びS1基板1oを所望の
深さまでエツチングし凹部15を形成する(第3図a)
。凹部15のエツチング深さは、分離絶縁膜の膜厚の約
半分程度が良い0次に、ホトレジストパターン14を除
去した後、513N4膜13をマスクにして凹部15表
面に薄いSi○2膜16全16する(第3図b)。
Thereafter, a photoresist pattern 14 is formed on the area other than the isolation area by photolithography. Then, using the photoresist pattern 14 as a mask, the 513N4 film 13, the PolySi film 12, the S102 film 11, and the S1 substrate 1o are etched to a desired depth by anisotropic dry etching to form a recess 15 (see FIG. 3a). )
. The etching depth of the recess 15 is preferably approximately half the thickness of the isolation insulating film. Next, after removing the photoresist pattern 14, a thin Si*2 film 16 is completely etched on the surface of the recess 15 using the 513N4 film 13 as a mask. 16 (Figure 3b).

次に、上記Si基板10上に513N4膜17を形成し
だ後(第3図C)、異方性のドライエツチングで513
N4膜17をエツチングすれば凹部15の側面部のみに
813N4膜17が残存する(第3図d)。
Next, after forming the 513N4 film 17 on the Si substrate 10 (FIG. 3C), the 513N4 film 17 is etched by anisotropic dry etching.
When the N4 film 17 is etched, the 813N4 film 17 remains only on the side surfaces of the recess 15 (FIG. 3d).

次に、513N4嘆13及び17をマスクにして選択酸
化することによって分離S z 02膜18を形成する
。このとき、513N4膜17とSi基板10及びPo
1y Si膜12の間も多少酸化されSi○2膜18′
が形成され、Si3N4膜17は上部方向に押し上げら
れる。(第3図e)。
Next, the isolation S z 02 film 18 is formed by selectively oxidizing the 513N4 films 13 and 17 as a mask. At this time, the 513N4 film 17, the Si substrate 10 and the Po
1y The space between the Si film 12 is also slightly oxidized and the Si○2 film 18'
is formed, and the Si3N4 film 17 is pushed upward. (Figure 3e).

次に、513N4膜13 、17 、 Po1y Si
膜12及びSiO2膜11.18’ を等方性のドライ
エツチングによりエツチングすれば、第3図fの如くS
i基板10とほぼ平坦な表面を不する分離SiO2膜1
8が形成される。
Next, 513N4 films 13, 17, PolySi
If the film 12 and the SiO2 film 11.18' are etched by isotropic dry etching, S as shown in FIG.
Isolated SiO2 film 1 having a substantially flat surface with the i-substrate 10
8 is formed.

以上、第1の実施例によれば、513N4膜13及び1
7をマスクにして選択酸化し、SiO2膜18全18基
板10表面とほぼ平坦になる寸で酸 。
As described above, according to the first embodiment, the 513N4 films 13 and 1
7 as a mask, selectively oxidize the SiO2 film 18 until it becomes almost flat with the surface of the substrate 10.

化してもS iO2膜18には溝が形成されない。No groove is formed in the SiO2 film 18 even if

々ぜならば、Si基板10上にPo1y Si膜12が
形成されていることによって513N4膜17とS1基
板1o及びPo1y Si膜12間にS z 02膜1
8′が形成される。従来の方法においても凹部側面部の
513N4膜とS を加温にSiO2膜が形成されるが
、81基板上面に形成された813N4膜により酸化が
おさえられるため、ある程度酸化が進むと四部?tl(
11面部の813N4膜と81基板間の酸化がおさえら
れる。
In this case, since the Poly Si film 12 is formed on the Si substrate 10, the S z 02 film 1 is formed between the 513N4 film 17, the S1 substrate 1o, and the Poly Si film 12.
8' is formed. In the conventional method, a SiO2 film is formed by heating the 513N4 film and S on the side surfaces of the recess, but the oxidation is suppressed by the 813N4 film formed on the top surface of the 81 substrate. tl(
Oxidation between the 813N4 film on the 11th surface and the 81st substrate is suppressed.

しかし7、本発明では81基板1o上にPo1ySi膜
12が形成されているので、513N4膜17とPo1
ySi膜12間にも酸化が進みS z 02膜18′が
形成される。この5102膜18′は酸化の促進に応じ
て厚くなり、それによってSi3N4膜17は上部方向
に押し上げられる。したがつて、S 102膜18の酸
化に応じて813N4膜17が上部方向に押し上げられ
るのでS i O2膜18に溝ができない。
However, in the present invention, since the Po1ySi film 12 is formed on the 81 substrate 1o, the 513N4 film 17 and the Po1ySi film 12 are formed on the 81 substrate 1o.
Oxidation also progresses between the ySi films 12 to form S z 02 films 18'. This 5102 film 18' becomes thicker as the oxidation progresses, thereby pushing the Si3N4 film 17 upward. Therefore, as the S 102 film 18 is oxidized, the 813N4 film 17 is pushed upward, so that no groove is formed in the S i O 2 film 18 .

また、513N4膜17を上部方向に押し上げる際のス
トレスは、Po1y Si l]%12に加わるだめ、
Si基板10にはストレスが加わらず結晶欠陥が発生し
ない。
Moreover, the stress when pushing the 513N4 film 17 upward is not applied to the PolySi l]%12.
No stress is applied to the Si substrate 10, and no crystal defects occur.

次に、本発明の第2の実施例について第4図を用いて説
明する。
Next, a second embodiment of the present invention will be described using FIG. 4.

81基板20上に5102膜21 + S i3N4膜
22゜Po1ySi膜23及び513N4膜24を順次
形成する。その後、ホトリン技術によりホトレジストパ
ターン25を形成し、異方性のドライエツチングにより
513N4膜24 、 Po1y Sil莫23,5i
3N422、Si○2膜21及びSi基板2oを所望の
深さまでエツチングして凹部26を形成する(第4図a
)。
A 5102 film 21 + Si3N4 film 22° PolySi film 23 and a 513N4 film 24 are sequentially formed on the 81 substrate 20. Thereafter, a photoresist pattern 25 is formed using photolithography technology, and a 513N4 film 24 and a PolySil film 23,5i are formed by anisotropic dry etching.
3N422, the Si○2 film 21, and the Si substrate 2o are etched to a desired depth to form a recess 26 (see Fig. 4a).
).

次に、ホトレジストパターン25を除去した後、513
N4膜24をマスクにして凹部26表面に薄いS 10
2膜27を形成する(第4図b)。
Next, after removing the photoresist pattern 25, 513
Using the N4 film 24 as a mask, a thin S10 film is applied to the surface of the recess 26.
Two films 27 are formed (FIG. 4b).

次に、上記81基板20上にS13”丁。11莫28を
形成し/こ後、児方性のトライエノチンクで5i3N4
脱28をエツチングずれは四部26の佃11/11部の
みに5i3N4ttJ(28か残存する(第413:i
c)。
Next, on the 81 substrate 20, 5i3N4 was formed on the 81 substrate 20.
The difference in etching the removal 28 is 5i3N4ttJ (28 remains (No. 413: i
c).

次に、5131\1411莫24及び28をマスクにし
てJXX酸酸化ることによって分離S 102膜29が
形成する。このとき、513N4!1剪28とSi基板
2Q及びPo1y Si膜23の間も多少酸化され51
02膜29′か形成され、513N4膜28は」二部方
向に押し]−けられる(第4図d)。
Next, an isolated S 102 film 29 is formed by oxidizing with JXX acid using the 5131\1411 layers 24 and 28 as a mask. At this time, the space between the 513N4!1 shear 28, the Si substrate 2Q, and the PolySi film 23 is also slightly oxidized.
The 02 membrane 29' is formed and the 513N4 membrane 28 is pushed in the two-part direction (FIG. 4d).

次に、S 13N 4膜24 、28 、 Po1y 
S1膜23及びSi○2膜29′をエツチングすれは、
第4図eの如(Si基板20の表面とほぼ平坦な表面を
有する分:’41f、 S 102膜29が形成される
Next, S 13N 4 films 24 , 28 , Po1y
When etching the S1 film 23 and the Si○2 film 29',
An S 102 film 29 is formed as shown in FIG.

さらに、所望領域の513N4膜22.5102膜21
及びSi基板20をエツチングして選択酸化すれは、第
41Zi fの如く他の分離5IO2膜30を形成する
ことができる。
Furthermore, 513N4 film 22 and 5102 film 21 in the desired area
By etching and selectively oxidizing the Si substrate 20, another isolation 5IO2 film 30 such as the 41st Zif can be formed.

以上、第2の実施例によれは、第1の実施例と同様に溝
のない平坦な表面を有する分離SiO2膜29を形成す
ることができる。本実施例では、81基板20とPo1
ySill休23との間に5131N4膜22があるか
特に問題はなく、Po1ySi膜23を酸化するために
必要な酸素はSi○2膜27全27て供給され、Si○
2膜29′が形成される。
As described above, according to the second embodiment, the isolation SiO2 film 29 having a flat surface without grooves can be formed as in the first embodiment. In this embodiment, 81 substrate 20 and Po1
There is no particular problem whether there is a 5131N4 film 22 between the ySill film 23, and the oxygen necessary to oxidize the Po1ySi film 23 is supplied by the Si○2 film 27, and the Si○
Two films 29' are formed.

寸だ、513N4嘆28を」一部方向に押し」二ける際
のストレスは、第1の実施例と同様にPo1ySi膜2
3に加わるため、81基板2Qに結晶欠陥が発生しない
The stress when pushing the 513N4 part 28 in one direction is the same as in the first embodiment.
3, no crystal defects occur in the 81 substrate 2Q.

さらに、本実施例では813N4膜22を他の分子4f
tU 5IO2g 30を形成する際の選択酸化マスク
として用いることができる。
Furthermore, in this example, the 813N4 film 22 is coated with other molecules 4f.
It can be used as a selective oxidation mask when forming tU 5IO2g 30.

以」二、第1及び第2の実施例においてPo1ySi膜
の膜厚は、凹部の深さの〆以」−あれば良い。
Second, in the first and second embodiments, the thickness of the Po1ySi film may be as long as the depth of the recess.

また、S 102膜18′及び29′の膜厚は分離Si
O2膜18及び29の膜厚に比べると非宮に薄いので分
離S h O2膜18及び29の横方向への拡がりはあ
ま9ない。
Moreover, the film thickness of the S102 films 18' and 29' is
Since it is extremely thin compared to the thickness of the O2 films 18 and 29, the separation S h O2 films 18 and 29 do not spread much in the lateral direction.

発明の効果 以上のように、本発明によれは半桿体基板上に半導体膜
を形成し、半導体膜」二及び四部の側面部のみに形成し
たrで?化防止膜をマスクにして選択酸化することによ
ってバーズビーク、バードヘッドをなくすることができ
、その上、従来の製造方法て生じた分肉11准縁II!
@の急 な溝もほとんど生じない。バードヘッド、急 
な清が生じないため、半導体基板の表面は平坦て、配線
時における段差部での段線あるいは配線のエッチ残りに
よる短絡もおこらず、プロセスが安定するため歩留りの
向上にもつながる。、また、バーズビークもtryとん
と生じないため、トランジスタの活性領域のつぶれはな
くなり、高密度、高集積化に大きく寄与する。
Effects of the Invention As described above, according to the present invention, a semiconductor film is formed on a semi-rod substrate, and the semiconductor film is formed only on the side surfaces of the second and fourth parts. By selectively oxidizing using the anti-oxidation film as a mask, bird's beaks and bird's heads can be eliminated, and in addition, the thinning 11-edge II!
There are almost no sharp @ grooves. bird head, sudden
Since there are no gaps, the surface of the semiconductor substrate is flat, and no short circuits occur due to stepped lines or unetched wiring during wiring, and the process is stabilized, leading to improved yields. In addition, bird's beaks do not occur even after a try, so there is no collapse of the active region of the transistor, which greatly contributes to high density and high integration.

さらに、半導体基板」二に半導体膜を形成しているため
、選択酸化時の分離絶縁膜による凹部側曲部に形成した
酸化防止膜を押し上ける1祭のストレスは、半導体膜に
加わり、半導体基板にはほとんどストレスが加わらない
ので結晶欠陥の発生がなく、トランジスタの歩留り向上
にも太いに役立っている。
Furthermore, since the semiconductor film is formed on the semiconductor substrate, the stress during selective oxidation that pushes up the anti-oxidation film formed on the curved side of the recess due to the isolation insulating film is applied to the semiconductor film and Since almost no stress is applied to the substrate, no crystal defects occur, which greatly helps improve transistor yields.

以」二のように本発明は高密度化・高集積化・歩留り向
上を図った半導体装置の製造方法である。
As described above, the present invention is a method for manufacturing a semiconductor device that achieves higher density, higher integration, and improved yield.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)、 (bzは従来の半導体装置の製造方法
を示す工程断五図ミー第2図は第1図に示す従来の半導
体装置の製造工程の途中断面図、第3り1(a)−(0
は本発明の一実施例にかかる半導体装置の製造工程断面
図、第4図(a)〜(f7は本発明の他の実施例にがか
る半導体装置の製造工程断面[ン1である。 10 、20−−−・・Si基板、12 、23−=−
Po1ySi!fig、13,17,22,24;28
・・・・・S 13N 4IpJ、   1 8  、
 2 9  、 3 0 ・・・・・・ S 102 
 ill。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 7 第2図 第3図 第3図 第4図
1(a), (bz is a process cross-sectional view showing a conventional semiconductor device manufacturing method. FIG. 2 is a sectional view halfway through the conventional semiconductor device manufacturing process shown in FIG. 1. a) - (0
4(a) to (f7) are cross-sectional views of the manufacturing process of a semiconductor device according to another embodiment of the present invention. 20---...Si substrate, 12, 23-=-
Po1ySi! fig, 13, 17, 22, 24; 28
...S 13N 4IpJ, 1 8,
2 9 , 3 0 ... S 102
ill. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 7 Figure 2 Figure 3 Figure 3 Figure 4

Claims (2)

【特許請求の範囲】[Claims] (1)半導体基板の一生面上に第1の絶縁膜、半導体膜
及び第1の酸化防止膜を順次形成する工程と、所定の領
域の前記第1の酸化防止膜、半導体膜、第1の絶縁膜及
び半導体基板を所望の深さだけエツチングして凹部を形
成する工程と、前記凹部表面に薄い第2の絶縁膜を形成
する工程と、前記半導体基板上に第2の酸化防止膜を形
成する工程と、前記第2の酸化防止膜をエツチングし前
記凹部の側面部のみに前記第2の酸化防止膜を残存させ
る工程と、前記第1及び第2の酸化防止膜をマスクにし
て選択酸化により前記凹部内に分離絶縁膜を形成する工
程とを備えていることを特徴とする半導体装置の製造方
法。
(1) A step of sequentially forming a first insulating film, a semiconductor film, and a first antioxidant film on the whole surface of a semiconductor substrate, and forming a recess by etching the insulating film and the semiconductor substrate to a desired depth; forming a thin second insulating film on the surface of the recess; and forming a second anti-oxidation film on the semiconductor substrate. a step of etching the second oxidation prevention film to leave the second oxidation prevention film only on the side surfaces of the recess; and selective oxidation using the first and second oxidation prevention films as masks. A method of manufacturing a semiconductor device, comprising the step of: forming an isolation insulating film in the recess.
(2)第1の絶縁膜かシリコン酸化膜とシリコン窒化膜
から成ることを特徴とする特許請求の範囲第1項に記載
の半導体装置の製造方法。
(2) The method for manufacturing a semiconductor device according to claim 1, wherein the first insulating film is made of a silicon oxide film and a silicon nitride film.
JP7776583A 1983-05-02 1983-05-02 Manufacture of semiconductor device Pending JPS59202649A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7776583A JPS59202649A (en) 1983-05-02 1983-05-02 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7776583A JPS59202649A (en) 1983-05-02 1983-05-02 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS59202649A true JPS59202649A (en) 1984-11-16

Family

ID=13643030

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7776583A Pending JPS59202649A (en) 1983-05-02 1983-05-02 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS59202649A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63217640A (en) * 1987-03-06 1988-09-09 Seiko Instr & Electronics Ltd Formation of element isolation in semiconductor device
JPS63271956A (en) * 1987-04-28 1988-11-09 Seiko Instr & Electronics Ltd Formation of element isolation of semiconductor device
JPH02164037A (en) * 1988-12-19 1990-06-25 Nec Corp Selecting oxidative separation

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63217640A (en) * 1987-03-06 1988-09-09 Seiko Instr & Electronics Ltd Formation of element isolation in semiconductor device
JPS63271956A (en) * 1987-04-28 1988-11-09 Seiko Instr & Electronics Ltd Formation of element isolation of semiconductor device
JPH02164037A (en) * 1988-12-19 1990-06-25 Nec Corp Selecting oxidative separation

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