JPH09199494A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH09199494A JPH09199494A JP2191796A JP2191796A JPH09199494A JP H09199494 A JPH09199494 A JP H09199494A JP 2191796 A JP2191796 A JP 2191796A JP 2191796 A JP2191796 A JP 2191796A JP H09199494 A JPH09199494 A JP H09199494A
- Authority
- JP
- Japan
- Prior art keywords
- film
- sio
- polycrystalline
- substrate
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本願の発明は、LOCOS法
によってSi基板に素子分離用のSiO2 膜を形成する
半導体装置の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device in which a SiO 2 film for element isolation is formed on a Si substrate by the LOCOS method.
【0002】[0002]
【従来の技術】半導体装置における素子分離構造として
は、LOCOS法によってSi基板に素子分離用のSi
O2 膜を形成する構造が最も一般的に用いられている
が、最小線幅が0.35μm程度にまで微細化された半
導体装置では、バーズビークの発生を抑制して微細化を
進めるために、変形LOCOS法であるPPL(Pad Po
lyLOCOS)法が用いられている。2. Description of the Related Art As an element isolation structure in a semiconductor device, Si for element isolation is formed on a Si substrate by the LOCOS method.
The structure for forming an O 2 film is most commonly used, but in a semiconductor device whose minimum line width is miniaturized to about 0.35 μm, in order to suppress bird's beak generation and promote miniaturization, A modified LOCOS method, PPL (Pad Po
lyLOCOS) method is used.
【0003】このPPL法では、図1(a)に示す様
に、Si基板11上にパッド用のSiO2 膜12とO2
の拡散係数がSiO2 膜12よりも小さい多結晶Si膜
13と酸化防止膜であるSiN膜14とを順次に形成す
る。In this PPL method, as shown in FIG. 1A, a SiO 2 film 12 for a pad and an O 2 film are formed on a Si substrate 11.
A polycrystalline Si film 13 having a diffusion coefficient smaller than that of the SiO 2 film 12 and a SiN film 14 which is an antioxidant film are sequentially formed.
【0004】そして、素子分離領域にすべき領域では多
結晶Si膜13の膜厚方向の一部とSiO2 膜12とを
残してそれ以外のSiN膜14と多結晶Si膜13とを
除去し、素子活性領域にすべき領域に残したSiN膜1
4をマスクにしてSi基板11を選択的に酸化して、素
子分離用のSiO2 膜15を形成する。なお、本願の発
明の従来例では、素子分離領域にすべき領域に30nm
の膜厚の多結晶Si膜13を残していた。Then, in the region to be the element isolation region, a part of the polycrystalline Si film 13 in the film thickness direction and the SiO 2 film 12 are left and the other SiN film 14 and the polycrystalline Si film 13 are removed. , SiN film 1 left in the region to be the device active region
4 is used as a mask to selectively oxidize the Si substrate 11 to form a SiO 2 film 15 for element isolation. In the conventional example of the invention of the present application, 30 nm is formed in the region which should be the element isolation region.
The polycrystalline Si film 13 having the film thickness of 1 is left.
【0005】[0005]
【発明が解決しようとする課題】ところで、図1(b)
(c)は、PPL法において、形成当初の多結晶Si膜
13の膜厚を40nmとし、素子分離領域にすべき領域
に残す多結晶Si膜13の膜厚と、SiO2 膜15にお
けるSi基板11の表面からの深さa、凸部の高さb及
びバーズビークの長さcとの関係を示している。従っ
て、素子分離領域にすべき領域に30nmの膜厚の多結
晶Si膜13を残していた従来例では、凸部の高さbが
高くて、SiO2 膜15における段差が大きかった。By the way, FIG. 1 (b)
In (C), in the PPL method, the film thickness of the polycrystalline Si film 13 at the initial formation is set to 40 nm, the film thickness of the polycrystalline Si film 13 left in a region to be an element isolation region, and the Si substrate in the SiO 2 film 15. 11 shows the relationship between the depth a from the surface of No. 11, the height b of the convex portion, and the length c of the bird's beak. Therefore, in the conventional example in which the polycrystalline Si film 13 having a film thickness of 30 nm was left in the region to be the element isolation region, the height b of the convex portion was high and the step difference in the SiO 2 film 15 was large.
【0006】一方、素子分離領域等のパターンを微細化
するために、リソグラフィで使用する露光装置における
光学系の開口数を大きくして解像力を高めると、光学系
の焦点深度余裕は逆に開口数の2乗に反比例して急激に
小さくなる。このため、従来例の様にSiO2 膜15に
おける段差が大きいと、Si基板11上に形成する第1
層目の配線をパターニングする際の焦点深度余裕dが更
に小さくなって、従来例では微細な半導体装置を高い歩
留りで製造することが困難であった。On the other hand, if the numerical aperture of the optical system in the exposure apparatus used in lithography is increased to increase the resolution in order to miniaturize the pattern of the element isolation region and the like, the depth of focus margin of the optical system is conversely increased. It decreases in inverse proportion to the square of. Therefore, if the step difference in the SiO 2 film 15 is large as in the conventional example, the first step formed on the Si substrate 11
Since the depth of focus margin d when patterning the wiring of the layer is further reduced, it is difficult to manufacture a fine semiconductor device with a high yield in the conventional example.
【0007】[0007]
【課題を解決するための手段】請求項1の半導体装置の
製造方法は、Si基板上にSiO2 膜と多結晶Si膜と
酸化防止膜とを順次に形成する工程と、素子分離領域を
形成すべき領域における前記酸化防止膜と前記多結晶S
i膜の25〜65%の膜厚分とを除去する工程と、前記
除去後の前記酸化防止膜をマスクにして前記Si基板を
選択的に酸化することによって、素子分離用のSiO2
膜を形成する工程とを具備することを特徴としている。According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a step of sequentially forming a SiO 2 film, a polycrystalline Si film and an antioxidant film on a Si substrate, and an element isolation region are formed. And the polycrystalline S in the region to be
A step of removing 25 to 65% of the i film and a step of selectively oxidizing the Si substrate by using the removed anti-oxidation film as a mask to remove SiO 2 for element isolation.
And a step of forming a film.
【0008】請求項2の半導体装置の製造方法は、請求
項1の半導体装置の製造方法において、前記除去後の前
記多結晶Si膜の膜厚を10〜25nmにすることを特
徴としている。A method of manufacturing a semiconductor device according to a second aspect is the method of manufacturing a semiconductor device according to the first aspect, characterized in that the film thickness of the polycrystalline Si film after the removal is set to 10 to 25 nm.
【0009】請求項3の半導体装置の製造方法は、請求
項1の半導体装置の製造方法において、前記多結晶Si
膜の表面にSiO2 膜を形成した後に、このSiO2 膜
上に前記酸化防止膜を形成することを特徴としている。According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the first aspect, wherein the polycrystalline Si is used.
It is characterized in that after the SiO 2 film is formed on the surface of the film, the antioxidant film is formed on the SiO 2 film.
【0010】請求項1、2の半導体装置の製造方法で
は、素子分離用のSiO2 膜を形成する際にSi基板上
のSiO2 膜上に形成した多結晶Si膜のうちで25〜
65%の膜厚分を除去しているので、素子分離用のSi
O2 膜におけるバーズビークの発生を抑制しつつ段差を
小さくすることができる。In the method of manufacturing a semiconductor device according to the first and second aspects, when the SiO 2 film for element isolation is formed, 25 to 25 of the polycrystalline Si films formed on the SiO 2 film on the Si substrate are formed.
Since 65% of the film thickness is removed, Si for element isolation
The step can be reduced while suppressing the occurrence of bird's beaks in the O 2 film.
【0011】請求項3の半導体装置の製造方法では、多
結晶Si膜の表面にSiO2 膜を形成した後に酸化防止
膜を形成しているので、素子分離用のSiO2 膜を形成
した後に酸化防止膜を除去する際に、多結晶Si膜の表
面のSiO2 膜がストッパになって、Si基板の掘れを
防止することができる。In the method of manufacturing a semiconductor device according to the third aspect, since the SiO 2 film is formed on the surface of the polycrystalline Si film and then the antioxidant film is formed, the oxidation is performed after the SiO 2 film for element isolation is formed. When the protective film is removed, the SiO 2 film on the surface of the polycrystalline Si film serves as a stopper to prevent digging of the Si substrate.
【0012】[0012]
【発明の実施の形態】以下、本願の発明の一実施形態
を、図1、2を参照しながら説明する。本実施形態で
は、図2(a)に示す様に、Si基板21を酸化して、
膜厚が10nm程度であるパッド用のSiO2 膜22を
Si基板21の表面に形成する。そして、膜厚が50n
m程度である多結晶Si膜23をCVD法でSiO2 膜
22上に堆積させる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. In this embodiment, as shown in FIG. 2A, the Si substrate 21 is oxidized to
A pad SiO 2 film 22 having a film thickness of about 10 nm is formed on the surface of the Si substrate 21. And the film thickness is 50n
A polycrystalline Si film 23 having a thickness of about m is deposited on the SiO 2 film 22 by the CVD method.
【0013】その後、多結晶Si膜23の表面を酸化す
ることによって、膜厚が10nm程度のSiO2 膜24
を多結晶Si膜23の表面に形成すると共に多結晶Si
膜23の膜厚を40nm程度にする。そして、膜厚が1
00nm程度のSiN膜25をSiO2 膜24上に堆積
させる。Then, the surface of the polycrystalline Si film 23 is oxidized to form a SiO 2 film 24 having a thickness of about 10 nm.
Is formed on the surface of the polycrystalline Si film 23, and
The film thickness of the film 23 is set to about 40 nm. And the film thickness is 1
A SiN film 25 having a thickness of about 00 nm is deposited on the SiO 2 film 24.
【0014】次に、図2(b)に示す様に、SiN膜2
5上でレジスト26を素子活性領域のパターンに加工
し、このレジスト26をマスクにして、SiN膜25と
SiO2 膜24と多結晶Si膜23の20nm程度の膜
厚分とを異方性エッチングした後、レジスト26を除去
する。従って、素子分離領域にすべき領域に残した多結
晶Si膜23の膜厚も20nm程度である。Next, as shown in FIG. 2B, the SiN film 2
5, the resist 26 is processed into a pattern of the element active region, and the resist 26 is used as a mask to anisotropically etch the SiN film 25, the SiO 2 film 24 and the polycrystalline Si film 23 having a film thickness of about 20 nm. After that, the resist 26 is removed. Therefore, the film thickness of the polycrystalline Si film 23 left in the region to be the element isolation region is also about 20 nm.
【0015】次に、図2(c)に示す様に、SiN膜2
5を酸化防止マスクにしてSi基板21及び多結晶Si
膜23を酸化することによって、膜厚が300nm程度
である素子分離用のSiO2 膜27をSi基板21の表
面に選択的に形成する。そして、図2(d)に示す様
に、SiN膜25をエッチングで除去するが、この時、
SiO2 膜24がエッチングのストッパになって、多結
晶Si膜23及びSi基板21がエッチングされるのを
防止することができる。Next, as shown in FIG. 2C, the SiN film 2
5 as an antioxidation mask and Si substrate 21 and polycrystalline Si
By oxidizing the film 23, a SiO 2 film 27 for element isolation having a film thickness of about 300 nm is selectively formed on the surface of the Si substrate 21. Then, as shown in FIG. 2D, the SiN film 25 is removed by etching. At this time,
The SiO 2 film 24 serves as an etching stopper to prevent the polycrystalline Si film 23 and the Si substrate 21 from being etched.
【0016】その後、SiO2 膜24、多結晶Si膜2
3、SiO2 膜27のエッジ部における多結晶Si膜2
3の残り、及びこのエッジ部における荒れを除去して、
素子分離領域の形成を完了する。そして、更に従来公知
の工程を実行して、この半導体装置を完成させる。After that, the SiO 2 film 24 and the polycrystalline Si film 2
3. Polycrystalline Si film 2 at the edge of SiO 2 film 27
Remove the rest of 3 and the roughness at this edge,
The formation of the element isolation region is completed. Then, the conventionally known process is further executed to complete the semiconductor device.
【0017】なお、以上の実施形態では、図2(b)の
工程で、多結晶Si膜23の40nm程度の膜厚のうち
で20nm程度を異方性エッチングして20nm程度を
残したが、図1(c)からも明らかな様に、30〜15
nm程度の膜厚分を異方性エッチングして10〜25n
m程度の膜厚分を残しても、SiO2 膜27におけるに
おけるバーズビークの発生を抑制しつつ段差を小さくす
ることができる。In the above embodiment, about 20 nm of the film thickness of about 40 nm of the polycrystalline Si film 23 is anisotropically etched to leave about 20 nm in the step of FIG. 2B. As is clear from FIG. 1 (c), 30 to 15
The thickness of about 10 nm is anisotropically etched to 10 to 25n
Even if a film thickness of about m is left, the step difference can be reduced while suppressing the occurrence of bird's beaks in the SiO 2 film 27.
【0018】また、以上の実施形態では、図2(b)の
工程でSiN膜25をエッチングした時点の多結晶Si
膜23の膜厚を40nm程度としたが、この時点の多結
晶Si膜23の膜厚は40nm以外でもよく、その場合
でも、この時点の多結晶Si膜23の膜厚の25〜65
%の膜厚分を除去すれば、SiO2 膜27におけるバー
ズビークの発生を抑制しつつ段差を小さくすることがで
きる。Further, in the above embodiment, polycrystalline Si at the time of etching the SiN film 25 in the step of FIG. 2B.
Although the film thickness of the film 23 is set to about 40 nm, the film thickness of the polycrystalline Si film 23 at this time may be other than 40 nm, and even in this case, the film thickness of the polycrystalline Si film 23 at this time is 25 to 65.
%, The step difference can be reduced while suppressing the occurrence of bird's beaks in the SiO 2 film 27.
【0019】[0019]
【発明の効果】請求項1、2の半導体装置の製造方法で
は、素子分離用のSiO2 膜におけるバーズビークの発
生を抑制することができるので、半導体装置の微細化を
進めることができ、しかも、素子分離用のSiO2 膜に
おける段差を小さくすることができるので、配線をパタ
ーニングするためのリソグラフィにおける焦点深度余裕
を大きくすることができる。従って、微細な半導体装置
を高い歩留りで製造することができる。According to the method of manufacturing a semiconductor device of the first and second aspects, since it is possible to suppress the occurrence of bird's beaks in the SiO 2 film for element isolation, miniaturization of the semiconductor device can be promoted, and moreover, Since the step difference in the SiO 2 film for element isolation can be reduced, the depth of focus margin in lithography for patterning the wiring can be increased. Therefore, a fine semiconductor device can be manufactured with a high yield.
【0020】請求項3の半導体装置の製造方法では、素
子分離用のSiO2 膜を形成した後に酸化防止膜を除去
する際に、Si基板の掘れを防止することができるの
で、Si基板の損傷等がなくて信頼性の高い半導体装置
を製造することができる。In the method of manufacturing a semiconductor device according to the present invention, since the Si substrate can be prevented from being dug when the antioxidant film is removed after the SiO 2 film for element isolation is formed, the Si substrate is damaged. It is possible to manufacture a highly reliable semiconductor device without such problems.
【図1】(a)はPPL法を説明するための側断面図、
(b)はPPL法で形成した素子分離用SiO2 膜の側
面模式図、(c)はPPL法における多結晶Si膜の残
膜厚と素子分離用SiO2 膜の深さ、高さ及びバーズビ
ークの長さ並びにSi基板上の第1層目の配線のリソグ
ラフィにおける焦点深度余裕との関係を示すグラフであ
る。FIG. 1A is a side sectional view for explaining a PPL method,
(B) is a schematic side view of the element isolation SiO 2 film formed by the PPL method, and (c) is the remaining film thickness of the polycrystalline Si film and the depth, height and bird's beak of the element isolation SiO 2 film in the PPL method. 2 is a graph showing the relationship between the length of the line and the depth of focus margin in lithography of the first layer wiring on the Si substrate.
【図2】本願の発明の一実施形態を順次に示す側断面図
である。FIG. 2 is a side sectional view sequentially showing an embodiment of the present invention.
11 Si基板 12 SiO2 膜 13 多結晶Si膜 14 SiN膜 15 SiO2 膜 21 Si基板 22 SiO2 膜 23 多結晶Si膜 24 SiO2 膜 25 SiN膜 27 SiO2 膜11 Si substrate 12 SiO 2 film 13 Polycrystalline Si film 14 SiN film 15 SiO 2 film 21 Si substrate 22 SiO 2 film 23 Polycrystalline Si film 24 SiO 2 film 25 SiN film 27 SiO 2 film
Claims (3)
と酸化防止膜とを順次に形成する工程と、 素子分離領域を形成すべき領域における前記酸化防止膜
と前記多結晶Si膜の25〜65%の膜厚分とを除去す
る工程と、 前記除去後の前記酸化防止膜をマスクにして前記Si基
板を選択的に酸化することによって、素子分離用のSi
O2 膜を形成する工程とを具備することを特徴とする半
導体装置の製造方法。1. A step of sequentially forming a SiO 2 film, a polycrystalline Si film, and an antioxidant film on a Si substrate, and a step of forming the SiO 2 film and the polycrystalline Si film in a region where an element isolation region is to be formed. A step of removing 25 to 65% of the film thickness, and a step of selectively oxidizing the Si substrate using the removed anti-oxidation film as a mask.
And a step of forming an O 2 film.
10〜25nmにすることを特徴とする請求項1記載の
半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the film thickness of the polycrystalline Si film after the removal is set to 10 to 25 nm.
形成した後に、このSiO2 膜上に前記酸化防止膜を形
成することを特徴とする請求項1記載の半導体装置の製
造方法。3. The method of manufacturing a semiconductor device according to claim 1, wherein after forming a SiO 2 film on the surface of the polycrystalline Si film, the antioxidant film is formed on the SiO 2 film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2191796A JPH09199494A (en) | 1996-01-12 | 1996-01-12 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2191796A JPH09199494A (en) | 1996-01-12 | 1996-01-12 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH09199494A true JPH09199494A (en) | 1997-07-31 |
Family
ID=12068439
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2191796A Pending JPH09199494A (en) | 1996-01-12 | 1996-01-12 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH09199494A (en) |
-
1996
- 1996-01-12 JP JP2191796A patent/JPH09199494A/en active Pending
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