JPS63217639A - Formation of element isolation in semiconductor device - Google Patents
Formation of element isolation in semiconductor deviceInfo
- Publication number
- JPS63217639A JPS63217639A JP5126987A JP5126987A JPS63217639A JP S63217639 A JPS63217639 A JP S63217639A JP 5126987 A JP5126987 A JP 5126987A JP 5126987 A JP5126987 A JP 5126987A JP S63217639 A JPS63217639 A JP S63217639A
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon
- nitride film
- silicon nitride
- element isolation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000002955 isolation Methods 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 230000015572 biosynthetic process Effects 0.000 title description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 43
- 238000000034 method Methods 0.000 claims abstract description 26
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 9
- 239000010703 silicon Substances 0.000 claims abstract description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 50
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 50
- 230000003647 oxidation Effects 0.000 claims description 19
- 238000007254 oxidation reaction Methods 0.000 claims description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 125000006850 spacer group Chemical group 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 150000004767 nitrides Chemical class 0.000 abstract description 13
- 230000007547 defect Effects 0.000 abstract description 9
- 239000000758 substrate Substances 0.000 abstract description 9
- 241000293849 Cordylanthus Species 0.000 abstract 2
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 229910000077 silane Inorganic materials 0.000 description 3
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 210000000988 bone and bone Anatomy 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- VEDJZFSRVVQBIL-UHFFFAOYSA-N trisilane Chemical compound [SiH3][SiH2][SiH3] VEDJZFSRVVQBIL-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、半導体装置の素子分離形成方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for forming element isolation in a semiconductor device.
この発明は、バーズ・ピークが小さく欠陥の少ない素子
分離形成方法に関するもので、半導体表面に薄い酸化膜
を形成した後、多結晶シリコン膜を成長させ、さらにシ
リコン窒化膜を積層させる。The present invention relates to a device isolation formation method with small bird peaks and fewer defects, in which a thin oxide film is formed on a semiconductor surface, a polycrystalline silicon film is grown, and a silicon nitride film is further laminated.
次に将来素子分離領域となる部分のシリコン窒化膜及び
多結晶シリコン膜を選択的にエツチング除去する。次に
シリコン窒化膜を積層した後、反応性ドライエツチング
等の異方性エツチング法を用い、このシリコン窒化膜を
異方性エツチングし、多結晶シリコン膜の側壁と上部と
にシリコン窒化膜を残し、他の領域のシリコン窒化膜を
完全に除去する。このシリコン窒化膜で被われた多結晶
シリコン膜をマスクにして、多結晶シリコン膜のない領
域を酸化し素子骨ＨｆＪ域を形成する。次に活性領域と
なる部分に存在する窒化膜、多結晶シリコン膜及び酸化
膜を順次除去する。Next, the silicon nitride film and polycrystalline silicon film in portions that will become element isolation regions in the future are selectively etched away. Next, after laminating a silicon nitride film, this silicon nitride film is anisotropically etched using an anisotropic etching method such as reactive dry etching, leaving a silicon nitride film on the sidewalls and top of the polycrystalline silicon film. , the silicon nitride film in other areas is completely removed. Using the polycrystalline silicon film covered with this silicon nitride film as a mask, the region without the polycrystalline silicon film is oxidized to form an element bone HfJ region. Next, the nitride film, polycrystalline silicon film, and oxide film existing in the portion that will become the active region are sequentially removed.
以上により厚い酸化膜で被われた素子分離領域と半導体
表面が露出している活性領域が形成される。Through the above steps, an element isolation region covered with a thick oxide film and an active region in which the semiconductor surface is exposed are formed.
この後、活性領域には半導体素子が作成される。After this, a semiconductor element is created in the active region.
半導体装置の素子分離として従来から選択酸化法（ＬＯ
ＣＯ３法）が使用されている。このＬＯＣＯ８法は次の
様なものである。第２図（ａｌに示す様にシリコンなど
の半導体表面１１を酸化し、選択酸化時に発生する応力
を緩和するための緩衝用シリコン酸化膜１２を形成し、
さらに選択酸化時の酸化マスク用材料としてのシリコン
窒化膜１３をＣＶＤ法にて積層する。次に第２図中）に
示す様に、写真食刻法を用いレジスト１４を所望の形状
に形成し、このレジスト１４をマスクとしてシリコン窒
化膜１３をエツチングする。さらに第２図（Ｃ１に示す
様に酸化を行うとシリコン窒化膜のないｈｐ域は酸化さ
れ、厚い素子分離用の酸化膜１５が形成され、一方シリ
コン窒化膜１３で被われていない領域は殆ど酸化されな
い。次に第２図１ｄｌに示す様にシリコン窒化膜及び緩
衝用シリコン酸化膜を順次エツチング除去する事により
、素子骨Ｍ９Ｍ域１６と活性領域１７が完成する。この
後、活性領域１７には半導体素子が形成される。Selective oxidation (LO) has traditionally been used to isolate elements in semiconductor devices.
CO3 method) is used. This LOCO8 method is as follows. As shown in FIG. 2 (al), a semiconductor surface 11 such as silicon is oxidized, and a buffer silicon oxide film 12 is formed to relieve stress generated during selective oxidation.
Furthermore, a silicon nitride film 13, which serves as an oxidation mask material during selective oxidation, is deposited by CVD. Next, as shown in FIG. 2), a resist 14 is formed into a desired shape using photolithography, and the silicon nitride film 13 is etched using the resist 14 as a mask. Further, when oxidation is performed as shown in FIG. 2 (C1), the hp region where there is no silicon nitride film is oxidized and a thick oxide film 15 for element isolation is formed, while the area not covered with the silicon nitride film 13 is almost completely oxidized. It is not oxidized. Next, as shown in FIG. A semiconductor element is formed.
従来のＬＯＣＯ３法では第２図１ｄｌに示す様に素子分
離領域の境界から活性領域へ長さｌの酸化膜が細長く伸
び、活性領域を狭くしてしまう。（これをバーズ・ピー
クという）このバーズ・ピークの長さｉは酸化条件等に
よっても異なるが通常は０．５μｍ以上であり、素子分
離領域も狭くする事ができない。このパース・ピークを
小さくする方法として、緩衝用シリコン酸化膜を薄くす
るか、あるいはシリコン窒化膜を厚くする方法があるが
、どちらの場合もＬＯＧＯ３酸化工程で半導体基板に大
きな応力を及ぼし多数の結晶欠陥を誘起してしまい、素
子分離特性を劣化させる。従って良好な素子分離特性を
保持しながら、上記のバーズ・ピークを小さくする事は
、従来のＬＯＣＯ３法を用いては不可能である。In the conventional LOCO3 method, as shown in FIG. 2 1dl, an oxide film with a length l extends from the boundary of the element isolation region to the active region, thereby narrowing the active region. (This is called a bird's peak.) The length i of this bird's peak varies depending on the oxidation conditions, etc., but is usually 0.5 μm or more, and the element isolation region cannot be narrowed. There are ways to reduce this perspective peak by making the buffer silicon oxide film thinner or by making the silicon nitride film thicker, but in either case, the LOGO3 oxidation process places a large stress on the semiconductor substrate and causes a large number of crystals to form. This induces defects and deteriorates element isolation characteristics. Therefore, it is impossible to reduce the above-mentioned bird's peak while maintaining good element isolation characteristics using the conventional LOCO3 method.
ｃ問題点を解決するための手段〕
上記問題点を解決するためにこの発明は、半導体基板（
シリコン）と同程度の熱膨張係数を持つ多結晶シリコン
膜の側面と表面をシリコン窒化膜で被い、この多結晶シ
リコン膜を酸化マスクとして、多結晶シリコン膜で被わ
れていない領域を酸化する。又、緩衝用シリコン酸化膜
も５０〜５００人と非常に薄くできる。Means for Solving Problem c] In order to solve the above problem, the present invention provides a semiconductor substrate (
The sides and surface of a polycrystalline silicon film, which has a thermal expansion coefficient similar to that of silicon (silicon), are covered with a silicon nitride film, and the areas not covered by the polycrystalline silicon film are oxidized using this polycrystalline silicon film as an oxidation mask. . Furthermore, the buffer silicon oxide film can be made extremely thin, with a thickness of 50 to 500 layers.
緩衝用シリコン酸化膜を５０〜５００人と薄くできる事
とシリコン基板と熱膨張係数の等しい多結晶シリコン膜
を酸化マスクとして使用できる事からバーズ・ピークが
小さく欠陥の少ない素子分離が可能となる。Since the buffer silicon oxide film can be made 50 to 500 times thinner and a polycrystalline silicon film having the same coefficient of thermal expansion as the silicon substrate can be used as an oxidation mask, element isolation with small bird peaks and fewer defects is possible.
本発明の実施例を第１図（８）〜（ｆｌに示す。第１図
＋ａｌに示す様にシリコンなどの半導体基板１の上にシ
リコン酸化膜２を積層する。シリコン酸化膜２は酸化法
でもＣＶＤ法でも成長できる。An embodiment of the present invention is shown in FIG. 1 (8) to (fl). As shown in FIG. However, it can also be grown using the CVD method.
第１図＋ａｌに示す様に、次にシリコン酸化膜２の上に
多結晶シリコン膜３をＣＶＤ法で成長させる。As shown in FIG. 1+al, a polycrystalline silicon film 3 is then grown on the silicon oxide film 2 by the CVD method.
この多結晶シリコン膜３の上にさらにシリコン窒化膜４
を積層する。多結晶シリコン膜３はシランガス（Ｓｉ８
４）またはジシランガス（ＳｉＪｈ）又は、トリシラン
（ＳｉＪｓ）等のシラン系ガス（ＳｉｍＨｎ）を用いた
化学気相成長法で形成される。A silicon nitride film 4 is further formed on this polycrystalline silicon film 3.
Laminate. The polycrystalline silicon film 3 is made of silane gas (Si8
4) Alternatively, it is formed by a chemical vapor deposition method using disilane gas (SiJh) or silane-based gas (SimHn) such as trisilane (SiJs).
又、シリコン窒化膜４はジクロルシランガス（Ｓｉ１１
２ｃＩ１．ｚ）とアンモニア（ＮＨｚ） との反応によ
り、またはシランガス（ＳｉＬ）とアンモニア（ＮＬ）
との反応により形成される。更に多結晶シリコン膜３お
よびシリコン窒化膜４は上記の化学気相成長法以外の方
法、例えばスパッター法等により生成してもよい。次に
第１図Ｔｏｌに示す様に、上記の多結晶シリコン膜３と
シリコン窒化膜４を写真食刻法等の方法を用いて選択的
にエツチング除去する。即ち、素子分離領域となる部分
のシリコン窒化膜４及び多結晶シリコン膜３をエツチン
グ除去する。Moreover, the silicon nitride film 4 is made of dichlorosilane gas (Si11
2cI1. z) and ammonia (NHz) or silane gas (SiL) and ammonia (NL)
Formed by reaction with Furthermore, the polycrystalline silicon film 3 and the silicon nitride film 4 may be formed by a method other than the above-mentioned chemical vapor deposition method, such as a sputtering method. Next, as shown in FIG. 1, the polycrystalline silicon film 3 and silicon nitride film 4 are selectively etched away using a method such as photolithography. That is, the silicon nitride film 4 and polycrystalline silicon film 3 in the portions that will become element isolation regions are removed by etching.
このエツチングは湿式法でも良いがサイドエツチングの
少ない乾式法がより良い、乾式法の中でも特に異方性の
大きい反応性イオンエツチング（通称ＲＩＥ）やプラズ
マドライエツチング（通称ＰＰＥ）が好ましい。又、シ
リコン窒化膜４と多結晶シリコン膜３を別々のエツチン
グ装置でエツチングしても良いし、同一のエツチング装
置を用いて連続的にエツチングしても良い。シリコン窒
化膜４と多結晶シリコン１１ｆｆ３をエツチング除去し
ない部分は将来活性領域となる。次に第１図ｆｃｌに示
す様に第２の窒化膜５を積層する。この窒化膜５も窒化
膜４と同様に化学気相成長法またはスパッター法等の方
法により形成できる。次に異方性の強いドライエツチン
グ法（ＲＩＥ又はＰＰＥ又はイオンミリング又はスパッ
タエツチング等の方法）を用いて第２の窒化ｎｆ１５を
全面エツチングする。この時、素子分離領域となる部分
のシリコン酸化膜２の上に窒化膜は完全にエツチング除
去する事が望ましい。そのためにオーバーエツチングを
行うが、これによりシリコン酸化膜２及び第１のシリコ
ン窒化膜４の一部はエツチングされるがシリコン酸化Ｗ
Ａ２及び第１のシリコン窒化膜４のそれぞれの厚みを適
度な値にする事とオーバーエツチングを過度に行わない
ようにすれば特に問題はない、この異方性エツチングに
より平坦部のシリコン窒化膜５はすべてエツチングされ
るが、多結晶シリコン膜３の側壁部分のシリコン窒化膜
５の厚みは厚いので、多結晶シリコン膜３の側壁にシリ
コン窒化膜５はスペーサーとして残っている。This etching may be performed by a wet method, but a dry method with less side etching is better.Among the dry methods, reactive ion etching (commonly known as RIE) and plasma dry etching (commonly known as PPE), which have large anisotropy, are particularly preferred. Further, the silicon nitride film 4 and the polycrystalline silicon film 3 may be etched using separate etching devices, or may be etched continuously using the same etching device. The portions where the silicon nitride film 4 and polycrystalline silicon 11ff3 are not removed by etching will become active regions in the future. Next, as shown in FIG. 1 fcl, a second nitride film 5 is laminated. Like the nitride film 4, this nitride film 5 can also be formed by a method such as chemical vapor deposition or sputtering. Next, the second nitride nf 15 is etched over the entire surface using a highly anisotropic dry etching method (such as RIE, PPE, ion milling, or sputter etching). At this time, it is desirable to completely remove the nitride film on the silicon oxide film 2 in the portion that will become the element isolation region by etching. For this purpose, over-etching is performed, and as a result, part of the silicon oxide film 2 and the first silicon nitride film 4 are etched, but the silicon oxide W
There is no particular problem as long as the thicknesses of A2 and the first silicon nitride film 4 are set to appropriate values and over-etching is not performed excessively.This anisotropic etching removes the silicon nitride film 5 on the flat area. are completely etched, but since the thickness of the silicon nitride film 5 on the side wall portion of the polycrystalline silicon film 3 is thick, the silicon nitride film 5 remains on the side wall of the polycrystalline silicon film 3 as a spacer.
この様子は第１図（ｄｌに示されている０次に酸化雰囲
気の中で酸化を行うと第１図ｆｅｌに示す様に、窒化膜
で被われた多結晶シリコン膜３がある部分以外の領域に
は厚い酸化膜６が成長するが、窒化膜で被われた多結晶
シリコン膜のある領域は窒化膜が酸化マスクとなる為、
酸化膜は成長しない、特にスペーサーとして残っている
第２の窒化膜５は横方向への酸化を防止する。これによ
り横方向酸化であるバーズ・ピークは非常に小さくなる
。その後、酸化時に窒化膜上に薄く成長した酸化膜、シ
リコン窒化膜４及び５、多結晶シリコン膜３及び緩衝用
酸化膜２を順次除去し、第１図（［１に示す様に活性（
素子）領域７と素子分離領域８が形成される。その後、
活性領域７にはトランジスタなどの能動素子が形成され
ＩＣが作成される。When oxidation is performed in the zero-order oxidation atmosphere shown in Fig. 1 (dl), as shown in Fig. A thick oxide film 6 grows in the region, but in the region where the polycrystalline silicon film covered with the nitride film is, the nitride film acts as an oxidation mask.
The oxide film does not grow; in particular, the second nitride film 5 remaining as a spacer prevents oxidation in the lateral direction. This makes the bird's peak, which is lateral oxidation, very small. Thereafter, the oxide film that grew thinly on the nitride film during oxidation, the silicon nitride films 4 and 5, the polycrystalline silicon film 3, and the buffer oxide film 2 were sequentially removed, and the activated
An element) region 7 and an element isolation region 8 are formed. after that,
Active elements such as transistors are formed in the active region 7 to form an IC.
第１図には示さなかったが、シリコン窒化膜４及び多結
晶シリコン膜３をエツチングした後、又は第２のシリコ
ン窒化膜５を積層した後、又は第２のシリコン窒化膜５
をエツチングした後にフィールド領域反転防止用のイオ
ン注入を行っても良い。Although not shown in FIG. 1, after etching the silicon nitride film 4 and polycrystalline silicon film 3, or after laminating the second silicon nitride film 5, or after depositing the second silicon nitride film 5,
After etching, ion implantation may be performed to prevent field region inversion.
多結晶シリコン膜は半導体基板であるシリコンと同一の
組成である為、物理的性質が［（以している０選択酸化
法で特に問題となるのは、酸化マスク材料と基板材料の
熱膨張係数が異なる事から生ずる熱歪とそれによる半導
体基板内に誘起される欠陥である。酸化マスク材料とし
て多結晶シリコンを用い、その多結晶シリコンの側壁と
表面をシリコン窒化膜で被う事により熱歪は非常に小さ
くなり、シリコン基板中に発生する欠陥も非常に少なく
なる。従って緩衝用シリコン酸化膜２を薄くする事がで
きる事と側壁窒化膜の横方向酸化の防止によりバーズ・
ピークを非常に小さくできる。Since the polycrystalline silicon film has the same composition as the silicon that is the semiconductor substrate, the physical properties of the polycrystalline silicon film are This is thermal strain caused by the difference in the thermal strain and defects induced in the semiconductor substrate due to the thermal strain.By using polycrystalline silicon as the oxidation mask material and covering the sidewalls and surface of the polycrystalline silicon with a silicon nitride film, thermal strain can be reduced. becomes very small, and the number of defects generated in the silicon substrate is also very small.Therefore, the buffer silicon oxide film 2 can be made thinner, and the sidewall nitride film can be prevented from being oxidized in the lateral direction.
The peak can be made very small.
通常のＬＯＣＯ３法では緩衝用シリコン酸化膜２の厚み
は５００〜１０００人であるが、本発明を用いると３０
〜５００人の厚みにできる。又、多結晶シリコン膜３の
厚みは厚いほどバーズ・ピークが小さくなるが、実用上
３００〜６０００人が好ましい。又、シリコン窒化膜４
の厚みはシリコン窒化膜５のオーバーエツチングしても
充分残うているだけの厚みとかつフィールド酸化時に多
結晶シリコン膜２が酸化しないだけの厚みとを有してい
ればよい。更にシリコン窒化膜５の厚みも厚いほど側壁
の厚みも厚くなり、バーズ・ピークを小さくする。しか
し、実用的には３００〜３０００人が好ましい、−例と
して、緩衝用シリコン酸化膜２を２００人、多結晶シリ
コン膜３を４０００人、シリコン窒化膜４を１５００人
、シリコン窒化膜５を１５００人として、シリコン酸化
膜６を６０００人成長させた時のバーズ・ピークは０．
２ μ以下となり、はぼパターン寸法通りの活性領域と
素子骨Ｍ領域ができる。又、この時の欠陥密度も非常に
小さく、良好な素子分離特性を示した。In the normal LOCO3 method, the thickness of the buffer silicon oxide film 2 is 500 to 1000 mm, but with the present invention, the thickness is 30 mm.
It can be made up to 500 people deep. Further, the thicker the polycrystalline silicon film 3, the smaller the bird's peak, but in practice it is preferably 300 to 6,000. Also, silicon nitride film 4
It is sufficient that the thickness of the polycrystalline silicon film 2 is sufficiently thick enough to remain even if the silicon nitride film 5 is over-etched, and that the polycrystalline silicon film 2 is not oxidized during field oxidation. Furthermore, the thicker the silicon nitride film 5, the thicker the sidewalls become, which reduces the bird's peak. However, in practice, it is preferable to use 300 to 3,000 people. - For example, 200 people for the buffer silicon oxide film 2, 4,000 people for the polycrystalline silicon film 3, 1,500 people for the silicon nitride film 4, and 1,500 people for the silicon nitride film 5. The bird's peak when 6000 people grow silicon oxide film 6 is 0.
The active region and the element bone M region are formed in accordance with the dimensions of the dowel pattern. Moreover, the defect density at this time was also very small, and good element isolation characteristics were exhibited.
この発明は以上説明したように、シリコン窒化膜で表面
及び側壁を被われた多結晶シリコン膜を酸化マスクとし
て選択酸化する事により、欠陥も少なく、バーズ・ピー
クも非常に小さい良好な素子分離を実現できる。As explained above, this invention achieves good element isolation with few defects and very small bird's peaks by selectively oxidizing a polycrystalline silicon film whose surface and side walls are covered with a silicon nitride film as an oxidation mask. realizable.
【図面の簡単な説明】
第１図ｔａｒ〜（［１はこの発明の製造方法の工程順を
示す断面図、第２図（ａｌ〜（ｄ＋は従来の製造方法の
工程順を示す断面図である。
１．１１・・半導体基板
２．１２・ ・シリコン酸化Ｒ莫
３・・・・多結晶シリコン膜
４・・・・ （第１の）シリコン窒化膜５・・・・ （
第２の）シリコン窒化膜６．１５・・シリコン酸化Ｉｌ
！ （フィールド酸化膜）７．１７・・活性領域
８．１６・・素子分離領域
１３・・・・シリコン窒化膜
１４・・・・フォトレジスト
以上
出願人 セイコー電子工業株式会社
第１図[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1.11... Semiconductor substrate 2.12... Silicon oxide R3... Polycrystalline silicon film 4... (First) silicon nitride film 5... (
2nd) Silicon nitride film 6.15...Silicon oxide Il
! (Field oxide film) 7.17...Active region 8.16...Element isolation region 13...Silicon nitride film 14...Photoresist and above Applicant Seiko Electronics Co., Ltd. Figure 1
Claims (6)
膜上に多結晶シリコン膜を形成する工程と、前記多結晶
シリコン膜上に第１のシリコン窒化膜を形成する工程と
、前記第１のシリコン窒化膜と前記多結晶シリコン膜を
選択的に順次エッチングする工程と、第２のシリコン窒
化膜を形成する工程と、前記第２のシリコン窒化膜を異
方性エッチングし、前記多結晶シリコン膜の側壁に前記
第２のシリコン窒化膜のスペーサーを形成する工程と、
前記第１のシリコン窒化膜及び前記第２のシリコン窒化
膜から被われた前記多結晶シリコン膜を酸化マスクとし
て多結晶シリコン膜で被われていない領域を酸化する工
程と、前記第１及び第２のシリコン窒化膜上の酸化膜と
前記第１及び第２のシリコン窒化膜と多結晶シリコン膜
と前記絶縁膜とを順次除去する事により、酸化膜で被わ
れた領域と酸化膜のない領域を形成する工程とを含む事
を特徴とする半導体装置の素子分離形成方法。(1) a step of forming an insulating film on a semiconductor surface; a step of forming a polycrystalline silicon film on the insulating film; a step of forming a first silicon nitride film on the polycrystalline silicon film; a step of selectively sequentially etching the first silicon nitride film and the polycrystalline silicon film; a step of forming a second silicon nitride film; anisotropically etching the second silicon nitride film; forming a spacer of the second silicon nitride film on the sidewall of the silicon film;
oxidizing a region not covered with the polycrystalline silicon film using the polycrystalline silicon film covered by the first silicon nitride film and the second silicon nitride film as an oxidation mask; By sequentially removing the oxide film on the silicon nitride film, the first and second silicon nitride films, the polycrystalline silicon film, and the insulating film, the area covered with the oxide film and the area without the oxide film are removed. 1. A method for forming element isolation in a semiconductor device, the method comprising: forming a semiconductor device.
の範囲第１項記載の半導体装置の素子分離形成方法。(2) A method for forming element isolation in a semiconductor device according to claim 1, wherein the semiconductor is silicon.
のシリコン酸化膜である事を特徴とする特許請求の範囲
第１項記載の半導体装置の素子分離形成方法。(3) The insulating film formed on the semiconductor surface has a thickness of 30 to 1000 Å
2. A method for forming element isolation in a semiconductor device according to claim 1, wherein the silicon oxide film is a silicon oxide film.
有する事を特徴とする特許請求の範囲第１項記載の半導
体装置の素子分離形成方法。(4) The method for forming element isolation of a semiconductor device according to claim 1, wherein the polycrystalline silicon film has a thickness of 300 to 6000 Å.
Åである事を特徴とする特許請求の範囲第１項記載の半
導体装置の素子分離形成方法。(5) The thickness of the first silicon nitride film is 300 to 2000
3. The method for forming element isolation in a semiconductor device according to claim 1, wherein .ANG.
Åである事を特徴とする特許請求の範囲第１項記載の半
導体装置の素子分離形成方法。(6) The thickness of the second silicon nitride film is 300 to 3000
3. The method for forming element isolation in a semiconductor device according to claim 1, wherein .ANG.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5126987A JPS63217639A (en) | 1987-03-06 | 1987-03-06 | Formation of element isolation in semiconductor device |
| US07/164,431 US5149669A (en) | 1987-03-06 | 1988-03-04 | Method of forming an isolation region in a semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5126987A JPS63217639A (en) | 1987-03-06 | 1987-03-06 | Formation of element isolation in semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63217639A true JPS63217639A (en) | 1988-09-09 |
Family
ID=12882225
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5126987A Pending JPS63217639A (en) | 1987-03-06 | 1987-03-06 | Formation of element isolation in semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63217639A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5374584A (en) * | 1992-07-10 | 1994-12-20 | Goldstar Electron Co. Ltd. | Method for isolating elements in a semiconductor chip |
| US5538916A (en) * | 1993-04-28 | 1996-07-23 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing semiconductor device isolation region |
| JPH0982699A (en) * | 1995-09-14 | 1997-03-28 | Nec Corp | Manufacture of semiconductor device |
| CN117438372A (en) * | 2023-12-21 | 2024-01-23 | 粤芯半导体技术股份有限公司 | Pressure-resistant deep trench isolation method and device, electronic equipment and storage medium |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5976472A (en) * | 1982-10-26 | 1984-05-01 | Toshiba Corp | Manufacture of semiconductor device |
| JPS59121850A (en) * | 1982-12-27 | 1984-07-14 | Toshiba Corp | Manufacture of semiconductor device |
-
1987
- 1987-03-06 JP JP5126987A patent/JPS63217639A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5976472A (en) * | 1982-10-26 | 1984-05-01 | Toshiba Corp | Manufacture of semiconductor device |
| JPS59121850A (en) * | 1982-12-27 | 1984-07-14 | Toshiba Corp | Manufacture of semiconductor device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5374584A (en) * | 1992-07-10 | 1994-12-20 | Goldstar Electron Co. Ltd. | Method for isolating elements in a semiconductor chip |
| US5538916A (en) * | 1993-04-28 | 1996-07-23 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing semiconductor device isolation region |
| JPH0982699A (en) * | 1995-09-14 | 1997-03-28 | Nec Corp | Manufacture of semiconductor device |
| CN117438372A (en) * | 2023-12-21 | 2024-01-23 | 粤芯半导体技术股份有限公司 | Pressure-resistant deep trench isolation method and device, electronic equipment and storage medium |
| CN117438372B (en) * | 2023-12-21 | 2024-04-19 | 粤芯半导体技术股份有限公司 | Pressure-resistant deep trench isolation method and device, electronic equipment and storage medium |
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