JPS63271391A - Thin film transistor array substrate and manufacture thereof - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an active matrix display substrate using thin film transistors (TPT) and a method for manufacturing the same, and more particularly to a method for manufacturing a substrate for a liquid crystal display.

Background Art Displays using active matrix type display substrates using TPT have been actively researched because they provide higher image quality than simple matrix type display devices. T
The active matrix display device using PT is the second
This is the configuration shown in the figure. A source (or drain) electrode busbar 15 and a gate electrode busbar 1 formed on a transparent substrate 10
2a, a display substrate 25 supporting TFTs 23 and picture element electrodes 12b, and a counter substrate 27 having a counter electrode 26. Liquid crystal is sealed between these substrates 25 and 27. Active matrix type display substrates using TPT have the disadvantage of being more expensive than simple matrix type display devices, and methods to reduce the number of processes have been proposed.Active matrix type display substrates using TET Japanese Patent Application No. 1983 regarding the method of manufacturing display devices
-128667 discloses a method for simplifying the process. Its configuration will be explained below. FIG. 3 is a sectional view explaining the process, and FIG. 4 is a plan view.

(1) A transparent electrode I is formed on the glass substrate 10 by DC sputtering.
100 OA of TO and 1000 Å of Cr metal layer are deposited.

(2) ITO, Cr, ITOI la, Cr 12a
Etching is performed so as to leave a gate electrode made of ITOllb and a picture element electrode made of Cr12b. In FIG. 4a, a pattern of Cr electrodes 12a and 12b is formed, and ITOlla and 11b are formed below this.

(3) Next, SiNx was formed as an insulating layer by plasma CVD method.
Layer 13 is 4000A, 831 layer 14 is 1 as a semiconductor layer.
Deposit 00OA.

(4) Etching is performed in a photolithography process using a second mask so that layers 13 and 14 are left in the pattern shown in Figure 1, forming a gate insulating layer and a channel region.
A Si island region is formed.

(5) Next, a source/drain metal layer is deposited by DC sputtering.

(6) Etching the source/drain metal layer by a photolithography process using a third mask so as to leave the source (or drain) electrode 15a and drain (or source) electrode 15b in the pattern shown in FIG. 4C. do. A- in Figure 4C of the completed active matrix substrate
Cross-sectional views taken along lines A' and BB' are shown in FIGS. 3a and 3b. Although not shown in FIG. 2, 12a, 1
Below 2b are ITOlla and llb, aS i 14
Gate insulating layers 13 are formed under the same pattern.

Problems to be Solved by the Invention When an active matrix substrate is produced by the above method, when the 5iNX layer 13 and the 831 layer 14 are formed in the pattern shown in FIG. The substrate 10 will be exposed. This exposed glass substrate is exposed to and corroded by the deep etching solution made of HF before debossing when forming the source/drain metal layer in (5) and the etching solution when forming the source/drain pattern in (6). As a result, electrical connection failure (disconnection) between the picture element electrode and the drain due to poor coverage of the source/drain metal layer as shown in FIG. 5a occurs.
0, a chip 200 at the edge of the picture element electrode due to underetching of the glass substrate as shown in Figure 5, and a short circuit 300 between the gate and the picture element and between the source and the picture element due to fragments of the chipped picture element electrode. This resulted in defects and significantly lowered the yield of the process.

The present invention has been made to solve the above-mentioned drawbacks, and an object of the present invention is to provide a method for increasing process yield by eliminating exposure of the glass substrate.

Means for Solving the Problems The present invention involves creating a TPT and a pixel electrode on a glass substrate in the process of creating an active matrix display substrate in which each pixel includes a thin film transistor and a pixel electrode for display as constituent elements. It is characterized by forming a film that is chemically resistant to the etching solution used during the process.

Operation The present invention has the above-described structure, so that even if the insulating film on the pixel electrode is removed, the glass substrate is not exposed because of the protective film, and the substrate is not corroded in the subsequent process, so that good electrical connection between the pixel and the drain can be achieved. A proper connection can be obtained, and short-circuit defects caused by chipping of the edges of the picture element electrodes can also be avoided.

Example FIG. 1 is a sectional view illustrating the process.

(1) Si02 layer 2 is formed on the glass substrate 10 by normal pressure CVD method.
0 to 2000 A, a transparent electrode ITO layer to 100 A, and a Cr metal layer to 10.00 A by DC sputtering.

(2) Etching is performed to leave TTOlCr in the form of a gate electrode made of ITOlla and Cr12a, and a picture element electrode made of ITollb and Cr12b.

(3) Next, SiNx was formed as an insulating layer by plasma CVD method.
The layer 13 is 4000A, and the aSi layer 14 is 1A as a semiconductor layer.
000A deposited.

(4) Etching is performed in a photolithography process using a second mask so that layers 13 and 14 are left in the pattern shown in Figure 4, forming a gate insulating layer and a channel region.
A Si island region is formed.

(5) Next, after cleaning the substrate H20: HF=50:1
After removing the oxide on the a-3i layer by soaking in for 30 seconds,
MoSi2 at 1000A and AI at 70A using DC sputtering method
00A deposited.

(6) AI and MoSi2 are etched in a photolithography process using a third mask so as to leave the source (or drain) electrode 15a and drain (or source) electrode 15b in the pattern shown in FIG. 4C. The etching solution for AI is H3PO4:HNO3=25: 1.M
The etching solution for oSi2 is HNO3: HF=50:
It is 1.

Sio2 used as a protective film for glass in the above steps and O20 of glass (Corning, Inc., 7059): HF=5
The etching rate for HNO3:HF=50:1 is shown in the following table.

The following table shows glass (Corning, 7059) and SiO2
O20 of membrane (normal pressure CVD): HF=50: 1. HN
Etching for Os: HF=50:1 Actually coated SiO2 on a glass substrate using the above method and etched TPT.
When a pixel electrode was created, the corrosion of the substrate, which occurred as much as 100OOA when not coated with SiO2, was reduced to 1/20 by 5.
It was possible to suppress the current to about 00A, and the yield was significantly improved.

In this embodiment, TPT can be realized with three masks.

In the embodiments described above, a method was shown in which the gate electrode was formed on ITO and the gate wiring was formed using Cr metal, but instead of ITO, transparent electrodes such as SnO2, CdO, ZnO, etc. can be used. The metal on the transparent electrode should be selected from a material that can withstand the etching agent of the semiconductor layer and the insulating layer.
, Mo, silicide, etc. Furthermore, metals include AI and Mo.
It may be composed of two or more types of layers such as Si2, A1 and Ti. Further, although SINx is used as an example of the insulating layer, the material is not particularly selected, such as SiO2, TazO6, Al2O3, etc. Although the semiconductor layer was made of aSi,
CdSe, Te, polySi, etc. may also be used. Etching also includes wet etching and dry etching (
reactive ion etching, chemical dry etching)
Either is fine. SiO2 is used as a protective film for the substrate, but this can be changed to AlO3, SiNx depending on the process and material.
, Ta205, or the like can be used.

Effects of the Invention When an active matrix substrate using inverted staggered TPT is fabricated using the process according to the present invention, the glass substrate will not be corroded by the etching process even when the insulating film on the picture element electrode is removed, which is particularly advantageous. Gansho 6 L-1
The process simplification shown in No. 28667 can be effectively carried out, and it can greatly contribute to cost reduction and improvement of yield.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view explaining the steps of an embodiment of the present invention, FIG. 2 is an exploded view of a display device using TPT, and FIG.
FIG. 4 is a plan view and a sectional view illustrating a process using an inverted stagger type TPT shown in Japanese Patent Application No. 128667/1982, and FIG. 5 is a sectional view showing defects in the conventional process. 11: Transparent electrode, 12: Metal layer, 12a: Gate bus line pattern, 12b: Picture element electrode pattern. Name of agent: Patent attorney Toshio Nakao and one other person Figure 1

Claims (2)

[Claims] (1) A source or drain electrode bus for transmitting a signal, a gate electrode bus for transmitting a signal, a thin film transistor formed at the intersection of the source or drain electrode bus and the gate electrode bus, and a drain or source of the thin film transistor. a connected electrode as a component, the gate electrode bus bar is composed of a multilayer film in which a transparent electrode layer and at least a part of the transparent electrode layer are laminated with a metal layer, and a thin film on a substrate that protects the substrate. A thin film transistor array substrate comprising: (2) a source or drain electrode bus that transmits a signal;
Manufacturing a substrate including, as constituent elements, a gate electrode bus for transmitting a signal, a thin film transistor formed at the intersection of the source or drain electrode bus and the gate electrode bus, and an electrode connected to the drain or source of the thin film transistor. In the method, a thin film for protecting the substrate, a transparent electrode layer and a metal layer are deposited on an insulating substrate to form a multilayer film, the transparent electrode layer and the metal layer are selectively removed using the same mask, and the gate 1. A method for manufacturing a thin film transistor array substrate, comprising the steps of simultaneously forming separate patterns of electrode busbars and electrodes, and selectively forming the thin film transistors on the gate electrodes.