JPS63265493A - Multilayer ceramic board - Google Patents
Multilayer ceramic boardInfo
- Publication number
- JPS63265493A JPS63265493A JP10070187A JP10070187A JPS63265493A JP S63265493 A JPS63265493 A JP S63265493A JP 10070187 A JP10070187 A JP 10070187A JP 10070187 A JP10070187 A JP 10070187A JP S63265493 A JPS63265493 A JP S63265493A
- Authority
- JP
- Japan
- Prior art keywords
- multilayer ceramic
- ceramic board
- pattern
- ta2n
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000919 ceramic Substances 0.000 title claims abstract description 28
- 239000004020 conductor Substances 0.000 claims abstract description 19
- 239000002241 glass-ceramic Substances 0.000 claims abstract description 15
- 239000010409 thin film Substances 0.000 claims abstract description 14
- 239000011230 binding agent Substances 0.000 claims abstract description 11
- 239000011347 resin Substances 0.000 claims abstract description 8
- 229920005989 resin Polymers 0.000 claims abstract description 8
- 238000004544 sputter deposition Methods 0.000 claims abstract description 8
- 238000005498 polishing Methods 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims description 27
- 238000010304 firing Methods 0.000 claims description 10
- 238000010030 laminating Methods 0.000 claims description 4
- 239000010410 layer Substances 0.000 abstract description 20
- 239000010408 film Substances 0.000 abstract description 10
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 5
- 238000001312 dry etching Methods 0.000 abstract description 3
- 239000011229 interlayer Substances 0.000 abstract description 2
- 230000003746 surface roughness Effects 0.000 abstract description 2
- 238000010276 construction Methods 0.000 abstract 1
- 239000010949 copper Substances 0.000 description 9
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000011651 chromium Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000012299 nitrogen atmosphere Substances 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 2
- 210000004709 eyebrow Anatomy 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical group [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 1
- SWELZOZIOHGSPA-UHFFFAOYSA-N palladium silver Chemical compound [Pd].[Ag] SWELZOZIOHGSPA-UHFFFAOYSA-N 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔概要〕
ガラスセラミックからなるグリーンシートを使用した多
層セラミック基板において、
焼成してなる多層基板の表面を研磨加工で平滑化し、逆
スパッタにより清浄化したことにより、該基板上に薄膜
回路素子が形成可能とな、た新規多層セラミック基板で
ある。[Detailed Description of the Invention] [Summary] In a multilayer ceramic substrate using a green sheet made of glass ceramic, the surface of the fired multilayer substrate is smoothed by polishing and cleaned by reverse sputtering. This is a novel multilayer ceramic substrate on which thin film circuit elements can be formed.
本発明は９００℃程度の低温で焼成するガラスセラミッ
クのグリーンシートを使用した多層セラミック基板、特
に薄膜回路素子を表面に形成した多層セラミック基板に
関する。The present invention relates to a multilayer ceramic substrate using a glass ceramic green sheet fired at a low temperature of about 900° C., and particularly to a multilayer ceramic substrate having thin film circuit elements formed on its surface.
バインダ樹脂を含むガラスセラミックのグリーンシート
を使用した多層セラミック基板は、特開昭５９−９９５
号公報によれば、熱解重合型樹脂を含むバインダを使用
してガラスセラミック層を形成し−、この層の上に銅導
体層を形成し、多層化した未焼結体を、ガラスセラミッ
クに含まれるガラス成分が加熱による変化を示さない温
度におい゛て、水蒸気分圧を０．００５〜０．３気圧に
制御した窒素雰囲気中でバインダを飛散させ焼成したも
のである。A multilayer ceramic substrate using a glass-ceramic green sheet containing a binder resin is disclosed in Japanese Patent Application Laid-Open No. 59-995.
According to the publication, a glass ceramic layer is formed using a binder containing a thermally depolymerizable resin, a copper conductor layer is formed on this layer, and the multilayered green body is made into a glass ceramic. The binder is dispersed and fired in a nitrogen atmosphere with a water vapor partial pressure of 0.005 to 0.3 atm at a temperature at which the glass components contained do not change due to heating.
なお、前記特開昭５９−９９５号公報による多層セラミ
ック基板では、誘電率に係わるガラスセラミックのアル
ミナ含有量は４０〜６０重量％、焼成時のクランクに係
わるガラスセラミックスリップのバインダ樹脂の含有量
は５〜１６重量％とじ、銅の表面抵抗に係わる水蒸気分
圧を０．００５〜０．３気圧に制御した窒素雰囲気中で
バインダを飛散させる焼成温度は５５０〜６５０℃、ガ
ラスセラミックの焼成温度は９００℃程度にすることが
推奨されている。In addition, in the multilayer ceramic substrate according to the above-mentioned Japanese Patent Application Laid-Open No. 59-995, the alumina content of the glass ceramic, which is related to the dielectric constant, is 40 to 60% by weight, and the content of the binder resin of the glass ceramic slip, which is related to the crank during firing, is 40 to 60% by weight. 5 to 16% by weight, and the firing temperature for scattering the binder in a nitrogen atmosphere with the water vapor partial pressure related to the surface resistance of copper controlled to 0.005 to 0.3 atm is 550 to 650°C, and the firing temperature for glass ceramic is It is recommended that the temperature be about 900°C.
複数枚（例えば３０枚）のグリーンシートを積層し焼成
する従来の前記多層セラミック基板は、それ以前の方法
で製造された多層セラミック回路基板より、銅導体層の
表面抵抗が低く、絶縁層は緻密でありクランクがなく、
炭素残留物が少ない等の利点を有する。しかし、部分的
に眉間導体層およびバイアホールが形成されるため、表
面に凹凸の生じることが不可抗力であり、該凹凸のある
表面に薄膜回路素子（例えば薄膜抵抗素子）を形成でき
ないという問題点があった。The conventional multilayer ceramic circuit board, which is made by laminating and firing a plurality of green sheets (for example, 30 sheets), has a copper conductor layer with a lower surface resistance and an insulating layer with a denser layer than multilayer ceramic circuit boards manufactured by the previous method. and there is no crank,
It has advantages such as less carbon residue. However, since the conductor layer and the via holes are formed partially between the eyebrows, the occurrence of unevenness on the surface is unavoidable, and there is a problem that thin film circuit elements (for example, thin film resistive elements) cannot be formed on the uneven surface. there were.
〔問題点を解決するための手段〕
本発明は前記問題点の除去を目的とし、第１図の実施例
の多層セラミック基板１によれば、所望の導体層２およ
びバイアホール３を形成したガラスセラミックのグリー
ンシートを複数枚積層し焼成した基板４の表面５に、研
磨加工と逆スパッタ処理を施したのち、薄膜回路素子を
形成してなることを特徴とするものである。[Means for Solving the Problems] The present invention aims to eliminate the above problems, and according to the multilayer ceramic substrate 1 of the embodiment shown in FIG. It is characterized in that a thin film circuit element is formed after polishing and reverse sputtering are performed on the surface 5 of a substrate 4 made by laminating and firing a plurality of ceramic green sheets.
上記手段によれば、積層グリーンシートを焼成してなる
基板の表面を、研磨加工で平滑にし、逆スパッタによっ
て清浄にしたことで、該表面に薄膜回路素子の形成が可
能となり、そのことによって多層セラミック基板の高密
度構成および製造コストの低減が実現される。According to the above means, by smoothing the surface of the substrate formed by firing the laminated green sheets by polishing and cleaning it by reverse sputtering, it is possible to form a thin film circuit element on the surface, thereby making it possible to form a multilayer A high-density configuration of the ceramic substrate and a reduction in manufacturing costs are achieved.
以下に、図面を用いて本発明の実施例による多層セラミ
ック基板を説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Multilayer ceramic substrates according to embodiments of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例による多層セラミック基板の
要部を示す模式断面図、第２図は該多層セラミック基板
の主要製造工程に対応する模式断面図である。FIG. 1 is a schematic sectional view showing essential parts of a multilayer ceramic substrate according to an embodiment of the present invention, and FIG. 2 is a schematic sectional view corresponding to the main manufacturing steps of the multilayer ceramic substrate.
第１図において、Ｔａ、Ｎパターン６と導体パターン７
からなる′ｒｊＩｌ！抵抗素子を上面に形成した多層セ
ラミック基板１は、バインダ樹脂を含むガラスセラミッ
クからなり層間導体層２．異層間の導体層２を接続する
および上面に表呈するバイアホール３を形成してなる３
枚のグリーンシートを重ね、それを焼成して多層基板４
を作成する。しかるのち、表面粗さＲａ０．１μ−程度
に研磨加工したのち逆スパッタによって清浄化した上面
５に、スパッタにより被着した窒化タンタル（Ｔ ａ
！ Ｎ ）膜の不要部分をドライエツチングで除去して
なるＴａ、Ｎパターン６を形成し、Ｔａ、Ｎパターン６
に一端が積層する導体パターン７を形成し完成する。In FIG. 1, Ta, N pattern 6 and conductor pattern 7
'rjIl! A multilayer ceramic substrate 1 on which a resistance element is formed is made of glass ceramic containing a binder resin, and has an interlayer conductor layer 2. 3 formed by forming a via hole 3 that connects the conductor layer 2 between different layers and is exposed on the top surface.
Multilayer board 4 is created by stacking green sheets and firing them.
Create. Thereafter, tantalum nitride (T a
! N) A Ta,N pattern 6 is formed by removing unnecessary portions of the film by dry etching.
A conductor pattern 7 having one end laminated is formed and completed.
なお、導体パターン７はクローム（Ｃｒ）層７ａと銅（
Ｃｕ）層７ｂの積層構成であり、Ｃｒ膜にＣｕ膜を積層
形成しその不要部分を溶去し形成したものである。Note that the conductor pattern 7 includes a chromium (Cr) layer 7a and a copper (
It has a laminated structure of a Cu layer 7b, and is formed by laminating a Cu film on a Cr film and eluting unnecessary parts of the Cu film.
以下に、第２図を用いて多層セラミック基板ｌの主要工
程を工程順に説明する。Below, the main steps of the multilayer ceramic substrate 1 will be explained in order of process using FIG.
まず、樹脂バインダーを含むガラスセラミックのグリー
ンシートの所要部に銅導体層およびバイアホールを形成
し、複数枚の該グリーンシートを重ねて焼成し、第２図
（イ）に示す多層基板４が得られる。First, a copper conductor layer and via holes are formed in required parts of a glass ceramic green sheet containing a resin binder, and a plurality of the green sheets are stacked and fired to obtain the multilayer substrate 4 shown in FIG. 2(A). It will be done.
なお、使用したグリーンシートの厚さは厚さ約２００μ
ｍであり、導体層に金（Ａｕ）、銀パラジウム（Ａｇ／
Ｐｄ）等も使用できるが、本実施例では安価な銅を使用
している。The thickness of the green sheet used was approximately 200μ.
m, and the conductor layer contains gold (Au), silver palladium (Ag/
Pd) or the like can also be used, but in this example, inexpensive copper is used.
また、熱解重合型樹脂を含むバインダを使用したガラス
セラミックのグリーンシートを重ねた前記焼成は、約６
００℃で該バインダを飛散させたのち、約９００℃でガ
ラスセラミックを焼結させる。In addition, the above-mentioned firing process of stacking glass-ceramic green sheets using a binder containing a thermally depolymerizable resin
After scattering the binder at 00°C, the glass ceramic is sintered at about 900°C.
次いで、基板４の上面５を研磨加工により表面粗さＲａ
０，１μ−程度に仕上げ、逆スパッタにより清浄にした
のち、窒素雰囲気中でタンタルをスバッタし第２図（Ｅ
ｌ）に示すように、Ｔａ、Ｎ膜８を上面５に被着させる
。Next, the upper surface 5 of the substrate 4 is polished to have a surface roughness Ra.
After finishing to about 0.1 μ- and cleaning by reverse sputtering, tantalum was spattered in a nitrogen atmosphere to form a surface of 0.1 μm (Fig. 2).
As shown in 1), a Ta,N film 8 is deposited on the upper surface 5.
次いで、Ｔａ、Ｎ膜８の上にレジストパターンを形成し
、ドライエツチングでＴａ１Ｎ膜８の不要部分を除去し
第２図（ハ）に示すように、ＴａｇＮパターン（抵抗体
パターン）６を形成させたのち、導体パターン７を形成
させ多層セラミック基板１が完成する。Next, a resist pattern is formed on the Ta,N film 8, and unnecessary portions of the Ta1N film 8 are removed by dry etching to form a TagN pattern (resistor pattern) 6, as shown in FIG. 2(C). Thereafter, a conductor pattern 7 is formed to complete the multilayer ceramic substrate 1.
なお、前記実施例では薄膜回路素子として薄膜抵抗素子
を形成しているが、該抵抗素子と同様に薄膜コンデンサ
が形成できることを付記する。In the above embodiments, a thin film resistance element is formed as a thin film circuit element, but it should be noted that a thin film capacitor can be formed in the same way as the resistance element.
以上説明したように本発明によれば、ガラスセラミック
からなる複数枚のグリーンシートを焼成で一体化し、研
磨、逆スパッタした該焼成基板の表面に薄膜回路素子の
形成を可能とし、多層セラミック基板は回路構成が高密
度化すると共に、安価に提供できるようにした効果があ
る。As explained above, according to the present invention, a plurality of green sheets made of glass ceramic are integrated by firing, and thin film circuit elements can be formed on the surface of the fired substrate which is polished and reverse sputtered. This has the effect of increasing the density of the circuit configuration and being able to provide it at low cost.
第１図は本発明の一実施例による多層セラミック基板の
要部を示す模式断面図、
第２図は第１図に示す多層セラミック基板の主要製造工
程に対応する模式断面図、
である。
図中において、
１は多層セラミック基板、
２は眉間導体層、
３はバイアホール、
４は多層基板、
５は基板４の上面、
６はＴａ、Ｎパターン、
７は導体層、
８はＴ ａ ｔ Ｎ膜、
を示す。FIG. 1 is a schematic sectional view showing essential parts of a multilayer ceramic substrate according to an embodiment of the present invention, and FIG. 2 is a schematic sectional view corresponding to the main manufacturing steps of the multilayer ceramic substrate shown in FIG. 1. In the figure, 1 is a multilayer ceramic substrate, 2 is a conductor layer between the eyebrows, 3 is a via hole, 4 is a multilayer substrate, 5 is the upper surface of the substrate 4, 6 is a Ta, N pattern, 7 is a conductor layer, 8 is Ta t N film, is shown.
Claims (1)
導体層（２）およびバイアホール（３）を形成した複数
枚のグリーンシートを重ね焼成した基板（４）の表面（
５）に、研磨加工と逆スパッタ処理を施したのち、薄膜
回路素子を形成してなることを特徴とする多層セラミッ
ク基板。The surface of a substrate (4) made by laminating and firing a plurality of green sheets made of glass ceramic containing a binder resin and having a desired conductor layer (2) and via holes (3) formed therein (
5) A multilayer ceramic substrate characterized in that a thin film circuit element is formed after polishing and reverse sputtering.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10070187A JPS63265493A (en) | 1987-04-23 | 1987-04-23 | Multilayer ceramic board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10070187A JPS63265493A (en) | 1987-04-23 | 1987-04-23 | Multilayer ceramic board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63265493A true JPS63265493A (en) | 1988-11-01 |
| JPH0521358B2 JPH0521358B2 (en) | 1993-03-24 |
Family
ID=14281012
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10070187A Granted JPS63265493A (en) | 1987-04-23 | 1987-04-23 | Multilayer ceramic board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63265493A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0575272A (en) * | 1991-09-12 | 1993-03-26 | Nec Corp | Manufacture of printed-wiring board |
| JPH05315752A (en) * | 1992-05-06 | 1993-11-26 | Fujitsu Ltd | Manufacture of ceramic printed board |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55128856A (en) * | 1979-03-23 | 1980-10-06 | Ibm | Method of fabricating electric connection package of glasssceramic*conductor |
| JPS5825475A (en) * | 1981-08-05 | 1983-02-15 | Nec Corp | Sputtering device |
| JPS61163696A (en) * | 1985-01-11 | 1986-07-24 | 日本特殊陶業株式会社 | Multilayer circuit board |
-
1987
- 1987-04-23 JP JP10070187A patent/JPS63265493A/en active Granted
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55128856A (en) * | 1979-03-23 | 1980-10-06 | Ibm | Method of fabricating electric connection package of glasssceramic*conductor |
| JPS5825475A (en) * | 1981-08-05 | 1983-02-15 | Nec Corp | Sputtering device |
| JPS61163696A (en) * | 1985-01-11 | 1986-07-24 | 日本特殊陶業株式会社 | Multilayer circuit board |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0575272A (en) * | 1991-09-12 | 1993-03-26 | Nec Corp | Manufacture of printed-wiring board |
| JPH05315752A (en) * | 1992-05-06 | 1993-11-26 | Fujitsu Ltd | Manufacture of ceramic printed board |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0521358B2 (en) | 1993-03-24 |
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