JPH0697660A - Multi-layer ceramics substrate and its manufacture - Google Patents

Multi-layer ceramics substrate and its manufacture

Info

Publication number
JPH0697660A
JPH0697660A JP24782692A JP24782692A JPH0697660A JP H0697660 A JPH0697660 A JP H0697660A JP 24782692 A JP24782692 A JP 24782692A JP 24782692 A JP24782692 A JP 24782692A JP H0697660 A JPH0697660 A JP H0697660A
Authority
JP
Japan
Prior art keywords
thick film
substrate
pad
vias
layer substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP24782692A
Other languages
Japanese (ja)
Inventor
Shoichi Hattori
正一 服部
Kazue Nakamura
一枝 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP24782692A priority Critical patent/JPH0697660A/en
Publication of JPH0697660A publication Critical patent/JPH0697660A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4673Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
    • H05K3/4676Single layer compositions

Abstract

PURPOSE:To provide a multi-layer ceramics substrate and its manufacturing method, with which the connection reliability between the thick film via formed inside and the thin film pad formed on a surface is improved. CONSTITUTION:Multiple laminated inner layer substrates 24, containing a thick film pattern, a thick film via 28 and a thick film pad 30 formed to face the thick film via 28, respectively, multiple grinding layer substrates 26 containing thick film vias 32 and thick film pads 34 formed to face the thick film via 32, respectively, laminated on the upper and lower sides of the substrate 24, and thin film pads 38 formed on the upper and lower sides of the grinding layer substrate 26 are provided to constitute a multi-layer ceramics substrate. And at least at multiple layers of the grinding layer substrate 26, on upper and lower sides, multiple thick film vias 32 are connected to one thick film pad 34, and at the same time, one thin film pad 38 is connected to multiple thick film vias 34 on upper and lower sides of the grinding layer substrate 26.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】コンピューターや電子交換機等多
量の情報を処理する電子装置は、小型化、高信頼性、高
速化への要求が一段と高く、従って電子回路を高密度化
することが要求される。このためチップ(半導体素子)
自体の集積度を高め、要求に対処している。
[Industrial application] Electronic devices such as computers and electronic exchanges that process a large amount of information are required to be smaller, more reliable, and faster, and therefore higher density of electronic circuits is required. It Therefore, a chip (semiconductor element)
We are increasing the degree of integration of ourselves and dealing with demands.

【0002】また最近では、高密度化実装及び高速化の
要求に伴い、放熱性が良く高速化に適した多層セラミッ
ク基板上にチップを実装する技術が開発されており、近
年の多層セラミック基板は実装密度の上昇に伴い、厚膜
回路基板を研磨した後その表面に薄膜回路を形成するも
のが多用されており、多層セラミック基板製造時に厚膜
−薄膜接続の信頼度をより一層向上させることが要求さ
れている。
Recently, with the demand for high-density mounting and high-speed mounting, a technique for mounting a chip on a multilayer ceramic substrate having good heat dissipation and suitable for high-speed processing has been developed. Along with the increase in packaging density, it is widely used to polish a thick film circuit board and then form a thin film circuit on the surface, which can further improve the reliability of thick film-thin film connection when manufacturing a multilayer ceramic substrate. Is required.

【0003】[0003]

【従来の技術】図3は従来例断面図を示しており、
(A)は焼成された後の厚膜回路基板2を、(B)は研
磨した後表面に薄膜回路を形成した多層セラミック基板
12を示している。
2. Description of the Related Art FIG. 3 shows a sectional view of a conventional example.
(A) shows the thick film circuit board 2 after firing, and (B) shows the multilayer ceramic substrate 12 having a thin film circuit formed on the surface after polishing.

【0004】厚膜回路基板2は複数の内層基板4と、内
層基板4の上下に積層された研磨層基板6とから構成さ
れる。内層基板4には厚膜ビア8と厚膜パッド10と、
図示しない厚膜パターンが形成されており、研磨層基板
6には厚膜ビア8と厚膜パッド10とが形成されてい
る。内層基板4及び研磨層基板6とも、グリーンシート
を熱圧着し、所定温度で所定時間焼成して形成される。
The thick film circuit board 2 is composed of a plurality of inner layer substrates 4 and polishing layer substrates 6 laminated on and below the inner layer substrate 4. A thick film via 8 and a thick film pad 10 on the inner layer substrate 4;
A thick film pattern (not shown) is formed, and a thick film via 8 and a thick film pad 10 are formed on the polishing layer substrate 6. Both the inner layer substrate 4 and the polishing layer substrate 6 are formed by thermocompressing green sheets and firing at a predetermined temperature for a predetermined time.

【0005】図3(B)は、厚膜回路基板2の表面を研
磨して平面度及び平行度を出した後、表面上に薄膜パッ
ド14を形成した完成体としての多層セラミック基板1
2を示している。薄膜パッド14は銅、アルミニウム等
をスパッタリングした後、所定パターンにエッチングを
して形成されている。
FIG. 3B shows a multilayer ceramic substrate 1 as a finished product in which a thin film pad 14 is formed on the surface of the thick film circuit board 2 after polishing the surface to obtain flatness and parallelism.
2 is shown. The thin film pad 14 is formed by sputtering copper, aluminum, etc., and then etching it into a predetermined pattern.

【0006】[0006]

【発明が解決しようとする課題】従来の多層セラミック
基板12では、図示したように1個の厚膜ビア8に対し
て1個の薄膜パッド14が接続されていたため、数10
ppmの確立(数10万回に1回の割合)で厚膜ビア8
と薄膜パッド14との接続不良を生じるという問題があ
った。
In the conventional multi-layer ceramic substrate 12, one thin film pad 14 is connected to one thick film via 8 as shown in the figure.
Thick film via 8 with ppm establishment (once every 100,000 times)
There was a problem that a connection failure between the thin film pad 14 and the thin film pad 14 occurred.

【0007】本発明は、このような点に鑑みてなされた
ものであり、その目的とするところは、内部に形成した
厚膜ビアと表面上に形成した薄膜パッドとの接続信頼度
を向上するようにした多層セラミック基板及びその製造
方法を提供することである。
The present invention has been made in view of the above points, and an object thereof is to improve the reliability of connection between a thick film via formed inside and a thin film pad formed on the surface. It is an object of the present invention to provide a multilayer ceramic substrate and a method for manufacturing the same.

【0008】[0008]

【課題を解決するための手段】本発明によると、それぞ
れ厚膜パターンと、厚膜ビアと、該厚膜ビアに対向する
位置に形成された厚膜パッドとを有する複数の積層され
た内層基板と、該積層された内層基板の表裏に積層され
た、それぞれ厚膜ビアと、該厚膜ビアに対向する位置に
形成された厚膜パッドとを有する複数の研磨層基板と、
該研磨層基板の表裏に形成された薄膜パッドとから構成
される多層セラミック基板において、前記研磨層基板の
少なくとも表裏側の複数層で1個の厚膜パッドに対して
複数の厚膜ビアを接続するとともに、該研磨層基板の表
裏で前記複数の厚膜ビアに1個の薄膜パッドを接続した
ことを特徴とする多層セラミック基板が提供される。
According to the present invention, a plurality of stacked inner layer substrates each having a thick film pattern, a thick film via, and a thick film pad formed at a position facing the thick film via. And a plurality of polishing layer substrates each having a thick film via and a thick film pad formed at a position facing the thick film via, which are stacked on the front and back of the laminated inner layer substrate,
In a multilayer ceramic substrate composed of thin film pads formed on the front and back surfaces of the polishing layer substrate, a plurality of thick film vias are connected to one thick film pad in a plurality of layers on at least the front and back sides of the polishing layer substrate. In addition, a multilayer ceramic substrate is provided in which one thin film pad is connected to the plurality of thick film vias on the front and back of the polishing layer substrate.

【0009】好ましくは、研磨層基板の全てにおいて1
個の厚膜パッドに対して複数の厚膜ビアが接続されてい
る。本発明の他の側面によると、穴あけをした第1のグ
リーンシートを導体で穴埋めをして第1の厚膜ビアを形
成し、該第1のグリーンシートに導体を印刷して厚膜パ
ターンと第1の厚膜パッドを形成し、穴あけをした第2
のグリーンシートを導体で穴埋めをして第2の厚膜ビア
を形成し、該第2のグリーンシートに導体を印刷して前
記第2の厚膜ビアの複数個に接続する第2の厚膜パッド
を形成し、前記第1のグリーンシートを複数層積層する
とともに、積層された第1のグリーンシートの上下に第
2のグリーンシートをそれぞれ複数層積層し、前記積層
体を加熱しながら加圧して第1及び第2のグリーンシー
トの各々を圧着し、圧着された積層体を所定温度で所定
時間焼成し、焼成された積層体の上下両面を研磨して所
望の平面度及び平行度を出し、研磨された表面上に前記
第2の厚膜ビアの複数個に接続される薄膜パッドを形成
することを特徴をする多層セラミック基板の製造方法が
提供される。
Preferably, 1 is used for all of the polishing layer substrates.
A plurality of thick film vias are connected to each thick film pad. According to another aspect of the present invention, the first green sheet with holes is filled with a conductor to form a first thick film via, and a conductor is printed on the first green sheet to form a thick film pattern. The first thick film pad is formed and the second hole is punched.
Second thick film for forming a second thick film via by filling the green sheet of the above with a conductor, and printing a conductor on the second green sheet to connect to a plurality of the second thick film vias. A pad is formed, a plurality of layers of the first green sheet are laminated, a plurality of layers of a second green sheet are laminated above and below the laminated first green sheet, and the laminated body is pressed while being heated. Each of the first and second green sheets by pressure bonding, the pressure-bonded laminated body is fired at a predetermined temperature for a predetermined time, and the upper and lower surfaces of the fired laminated body are polished to obtain desired flatness and parallelism. A method of manufacturing a multilayer ceramic substrate is provided, which comprises forming thin film pads connected to a plurality of the second thick film vias on a polished surface.

【0010】[0010]

【作用】多層セラミック基板は内層基板及び研磨層基板
を積層した厚膜回路基板を研磨して平面度及び平行度を
出した後、表面に薄膜パッドを形成して製造される。薄
膜パッドは複数個の厚膜ビアに接続されているため、一
方の厚膜−薄膜接続部に異常を生じ接続不良が生じた場
合にも、他方の接続部が正常であれば正常に機能するた
め、厚膜−薄膜接続部の接続信頼度を向上することがで
きる。
A multilayer ceramic substrate is manufactured by polishing a thick film circuit substrate in which an inner layer substrate and a polishing layer substrate are laminated to obtain flatness and parallelism, and then forming a thin film pad on the surface. Since the thin film pad is connected to multiple thick film vias, even if one thick film-thin film connection part becomes abnormal and connection failure occurs, it will function properly if the other connection part is normal. Therefore, the connection reliability of the thick film-thin film connection portion can be improved.

【0011】[0011]

【実施例】以下、図面を参照して本発明の実施例を詳細
に説明する。図1は本発明実施例に係る多層セラミック
基板の分解断面図であり、図2(A)は焼成された厚膜
回路基板の断面図、図2(B)は研磨され薄膜回路の形
成された多層セラミック基板の断面図である。
Embodiments of the present invention will now be described in detail with reference to the drawings. 1 is an exploded cross-sectional view of a multilayer ceramic substrate according to an embodiment of the present invention, FIG. 2 (A) is a cross-sectional view of a thick film circuit board that has been fired, and FIG. 2 (B) is a polished thin film circuit. It is sectional drawing of a multilayer ceramic substrate.

【0012】図2(A)を参照すると、複数の内層基板
24及び内層基板24の上下に積層された研磨層基板2
6とからなる厚膜回路基板22が示されている。内層基
板24は例えば数10層積層されており、各内層基板2
4には複数の厚膜ビア28と、それぞれ各厚膜ビア28
に接続された複数の厚膜パッド30と、図示しない厚膜
パターンが形成されている。これらの厚膜ビア28、厚
膜パッド30及び厚膜パターンは、例えば銅から形成さ
れている。
Referring to FIG. 2A, a plurality of inner layer substrates 24 and a polishing layer substrate 2 stacked above and below the inner layer substrate 24.
A thick film circuit board 22 consisting of 6 and 6 is shown. The inner layer substrates 24 are, for example, several tens of layers stacked, and each inner layer substrate 2
4 includes a plurality of thick film vias 28 and each thick film via 28.
A plurality of thick film pads 30 connected to each other and a thick film pattern (not shown) are formed. The thick film via 28, the thick film pad 30, and the thick film pattern are made of, for example, copper.

【0013】内層基板24に複数層積層された研磨層基
板26は基板全体の平面度及び平行度を出すために任意
の位置まで研磨されるべき基板であり、内層基板24に
設けた1個の厚膜ビア28に対して2個の厚膜ビア32
が形成されており、2個の厚膜ビア32に対して1個の
厚膜パッド34が接続されている。
The polishing layer substrate 26, which is a plurality of layers laminated on the inner layer substrate 24, is a substrate to be polished to an arbitrary position in order to obtain the flatness and parallelism of the entire substrate. Two thick film vias 32 for each thick film via 28
Are formed, and one thick film pad 34 is connected to the two thick film vias 32.

【0014】内層基板24及び研磨層基板26は、例え
ばガラスセラミックスのグリーンシートを積層して熱圧
着し、これらを所定温度で所定時間焼成することにより
形成される。
The inner layer substrate 24 and the polishing layer substrate 26 are formed, for example, by laminating glass ceramic green sheets, thermocompression-bonding them, and firing them at a predetermined temperature for a predetermined time.

【0015】以下、本発明実施例の多層セラミック基板
の製造プロセスについて説明する。先ず、内層基板とな
るガラスセラミックス製の第1のグリーンシートに穴あ
けをし、銅で穴埋めをして第1の厚膜ビア28を形成す
る。次いで、第1のグリーンシートに銅をスクリーン印
刷して第1の厚膜パッド30と図示しない厚膜パターン
とを形成する。
The manufacturing process of the multilayer ceramic substrate of the embodiment of the present invention will be described below. First, a first green sheet made of glass ceramics, which is an inner layer substrate, is punched and filled with copper to form a first thick film via 28. Then, copper is screen-printed on the first green sheet to form a first thick film pad 30 and a thick film pattern (not shown).

【0016】内層基板24に形成された厚膜パターンは
基板ごとに異なっており、それぞれ信号層、電源層又は
アース層の役目をする。さらに、研磨層基板26となる
ガラスセラミックス製の第2のグリーンシートに穴あけ
をし、これらの穴を銅で穴埋めをして第2の厚膜ビア3
2を形成する。次いで、第2のグリーンシートに銅をス
クリーン印刷してそれぞれ第2の厚膜ビア32の2個に
接続する第2の厚膜パッド34を形成する。
The thick film pattern formed on the inner layer substrate 24 is different for each substrate and serves as a signal layer, a power source layer or a ground layer, respectively. Further, the second green sheet made of glass ceramics to be the polishing layer substrate 26 is perforated, and these holes are filled with copper to form the second thick film via 3
Form 2. Next, copper is screen-printed on the second green sheet to form second thick film pads 34 that connect to the two second thick film vias 32, respectively.

【0017】第2のグリーンシートは焼成して研磨層基
板26となるものであるため、第2のグリーンシート上
には厚膜パターンを形成しない。このように加工された
第1のグリーンシートを複数層積層するとともに、積層
された第1のグリーンシートの上下に第2のグリーンシ
ートをそれぞれ複数層積層する。
Since the second green sheet is fired to form the polishing layer substrate 26, no thick film pattern is formed on the second green sheet. A plurality of layers of the first green sheet processed as described above are laminated, and a plurality of second green sheets are laminated above and below the laminated first green sheet.

【0018】この積層体を約100〜150℃で加熱し
ながら約300kg/cm2 の力で加圧して各グリーンシー
トを熱圧着する。次いで、圧着された積層体を約100
0℃で約2.5時間焼成して、厚膜回路基板22を製造
する。
While heating the laminated body at about 100 to 150 ° C., each green sheet is thermocompression-bonded by applying a pressure of about 300 kg / cm 2 . Next, the pressure-bonded laminated body is about 100
The thick film circuit board 22 is manufactured by firing at 0 ° C. for about 2.5 hours.

【0019】次いで、焼成された厚膜回路基板22の上
下両面の研磨層基板26を任意の位置まで研磨して、所
望の平面度及び平行度を出すようにする。次いで、研磨
された基板上にスパッタリングにより例えばアルミニウ
ムの被膜を形成し、エッチングすることにより研磨層基
板26に形成された2個の厚膜ビア32に接続された薄
膜パッド38を形成する。薄膜パッド38の厚さは数μ
m程度である。
Next, the polishing layer substrates 26 on the upper and lower surfaces of the baked thick film circuit substrate 22 are polished to arbitrary positions so as to obtain desired flatness and parallelism. Next, a film of, for example, aluminum is formed on the polished substrate by sputtering, and is etched to form the thin film pad 38 connected to the two thick film vias 32 formed on the polishing layer substrate 26. The thickness of the thin film pad 38 is several μ
It is about m.

【0020】このようにして形成した多層セラミック基
板36が図2(B)に示されている。図1は図2(B)
に示された多層セラミック基板の分解断面図を示してい
る。尚、図2(A)、(B)において、各内層基板24
及び研磨層基板26の境界線が示されているが、これは
説明の便宜上理解を助けるために示されているに過ぎ
ず、焼成された実際の多層セラミック基板では各内層基
板24及び研磨層基板26は一体化されてこれらの境界
線は識別し得ないものである。
The multilayer ceramic substrate 36 thus formed is shown in FIG. 2 (B). Figure 1 is Figure 2 (B)
3 is an exploded sectional view of the multilayer ceramic substrate shown in FIG. 2A and 2B, each inner layer substrate 24
The boundary line between the polishing layer substrate 26 and the polishing layer substrate 26 is shown only for the sake of convenience of description and for the sake of understanding. In the fired actual multilayer ceramic substrate, each inner layer substrate 24 and polishing layer substrate 26 are shown. 26 is integrated so that these boundaries are indistinguishable.

【0021】本実施例によれば、基板表面に形成された
薄膜パッドは2個の厚膜ビアに接続されているため、一
方の厚膜−薄膜接続部に何らかの異常が生じ接続不具合
が生じた場合にも、もう一方の厚膜−薄膜接続部が正常
であれば回路全体を正常に機能させることができる。
According to this embodiment, since the thin film pad formed on the surface of the substrate is connected to the two thick film vias, one thick film-thin film connection portion has some abnormality and a connection failure occurs. Also in this case, if the other thick film-thin film connection portion is normal, the entire circuit can function normally.

【0022】上述した実施例では、1個の薄膜パッドに
対して2個の厚膜ビアを接続しているが、本発明はこの
構成に限定されるものではなく、1個の薄膜パッドに対
して3個以上の厚膜ビアを接続する構成を含むものであ
る。
In the above-described embodiment, two thick film vias are connected to one thin film pad, but the present invention is not limited to this structure and one thin film pad is connected. It includes a structure in which three or more thick film vias are connected together.

【0023】[0023]

【発明の効果】本発明の多層セラミック基板は以上詳述
したように構成したので、厚膜−薄膜の接続チャンスを
整数倍化できるため、内部に形成した厚膜ビアと表面上
に形成した薄膜パッドとの接続信頼度を向上できるとい
う効果を奏する。
Since the multilayer ceramic substrate of the present invention is configured as described above in detail, the connection chance of thick film-thin film can be multiplied by an integer. Therefore, the thick film via formed inside and the thin film formed on the surface are formed. This has the effect of improving the reliability of connection with the pad.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明実施例に係る多層セラミック基板の分解
断面図である。
FIG. 1 is an exploded sectional view of a multilayer ceramic substrate according to an embodiment of the present invention.

【図2】本発明実施例の断面図であり、(A)は焼成後
の厚膜回路基板を、(B)は表面研磨をした後薄膜パッ
ドを形成し、完成された多層セラミック基板をそれぞれ
示している。
2A and 2B are cross-sectional views of an embodiment of the present invention, in which FIG. 2A is a thick film circuit board after firing, and FIG. Shows.

【図3】従来例断面図であり、(A)は厚膜回路基板
を、(B)は完成された多層セラミック基板をそれぞれ
示している。
FIG. 3 is a cross-sectional view of a conventional example, (A) shows a thick film circuit board, and (B) shows a completed multilayer ceramic board.

【符号の説明】[Explanation of symbols]

22 厚膜回路基板 24 内層基板 26 研磨層基板 28,32 厚膜ビア 30,34 厚膜パッド 36 多層セラミック基板 38 薄膜パッド 22 Thick Film Circuit Board 24 Inner Layer Substrate 26 Polishing Layer Substrate 28,32 Thick Film Via 30,34 Thick Film Pad 36 Multilayer Ceramic Substrate 38 Thin Film Pad

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 それぞれ厚膜パターンと、厚膜ビア(28)
と、該厚膜ビア(28)に対向する位置に形成された厚膜パ
ッド(30)とを有する複数の積層された内層基板(24)と、
該積層された内層基板(24)の表裏に積層された、それぞ
れ厚膜ビア(32)と、該厚膜ビア(32)に対向する位置に形
成された厚膜パッド(34)とを有する複数の研磨層基板(2
6)と、該研磨層基板(26)の表裏に形成された薄膜パッド
(38)とから構成される多層セラミック基板において、 前記研磨層基板(26)の少なくとも表面側の複数層で1個
の厚膜パッド(34)に対して複数の厚膜ビア(32)を接続す
るとともに、 該研磨層基板(26)の表裏で前記複数の厚膜ビア(34)に1
個の薄膜パッド(38)を接続したことを特徴とする多層セ
ラミック基板。
1. A thick film pattern and a thick film via (28), respectively.
And a plurality of laminated inner layer substrates (24) having thick film pads (30) formed at positions facing the thick film vias (28),
A plurality of thick film vias (32) stacked on the front and back of the stacked inner layer substrate (24), and thick film pads (34) formed at positions facing the thick film vias (32). Polishing layer substrate (2
6) and a thin film pad formed on the front and back of the polishing layer substrate (26)
A multilayer ceramic substrate composed of (38) and a plurality of thick film vias (32) are connected to one thick film pad (34) by a plurality of layers on at least the surface side of the polishing layer substrate (26). The plurality of thick film vias (34) are provided on the front and back of the polishing layer substrate (26).
A multi-layer ceramic substrate characterized by connecting individual thin film pads (38).
【請求項2】 前記研磨層基板(26)の全てにおいて1個
の厚膜パッド(34)に対して複数の厚膜ビア(32)を接続し
たことを特徴とする請求項1記載の多層セラミック基
板。
2. The multilayer ceramic according to claim 1, wherein a plurality of thick film vias (32) are connected to one thick film pad (34) in all of the polishing layer substrates (26). substrate.
【請求項3】 前記内層基板(24)と研磨層基板(26)はガ
ラスセラミックスから形成される請求項1又は2記載の
多層セラミック基板。
3. The multilayer ceramic substrate according to claim 1, wherein the inner layer substrate (24) and the polishing layer substrate (26) are made of glass ceramics.
【請求項4】 前記厚膜ビア(28,32) 、厚膜パッド(30,
34) 及び厚膜パターンは銅から形成され、前記薄膜パッ
ド(38)はアルミニウムから形成される請求項1〜3のい
ずれかに記載の多層セラミック基板。
4. The thick film via (28, 32), the thick film pad (30,
34) The multilayer ceramic substrate according to any one of claims 1 to 3, wherein the thick film pattern is formed of copper, and the thin film pad (38) is formed of aluminum.
【請求項5】 穴あけをした第1のグリーンシートを導
体で穴埋めをして第1の厚膜ビア(28)を形成し、 該第1のグリーンシートに導体を印刷して厚膜パターン
と第1の厚膜パッド(30)を形成し、 穴あけをした第2のグリーンシートを導体で穴埋めをし
て第2の厚膜ビア(32)を形成し、 該第2のグリーンシートに導体を印刷して前記第2の厚
膜ビア(32)の複数個に接続する第2の厚膜パッド(34)を
形成し、 前記第1のグリーンシートを複数層積層するとともに、
積層された第1のグリーンシートの上下に第2のグリー
ンシートをそれぞれ複数層積層し、 前記積層体を加熱しながら加圧して第1及び第2のグリ
ーンシートの各々を圧着し、 圧着された積層体を所定温度で所定時間焼成し、 焼成された積層体の上下両面を研磨して所望の平面度及
び平行度を出し、 研磨された表面上に前記第2の厚膜ビア(34)の複数個に
接続される薄膜パッド(38)を形成することを特徴をする
多層セラミック基板の製造方法。
5. A first thick film via (28) is formed by filling the perforated first green sheet with a conductor, and a conductor is printed on the first green sheet to form a thick film pattern and a first thick film pattern. 1 thick film pad (30) is formed, the second green sheet with holes is filled with a conductor to form a second thick film via (32), and a conductor is printed on the second green sheet. To form a second thick film pad (34) connected to a plurality of the second thick film vias (32), and stacking a plurality of layers of the first green sheet,
A plurality of second green sheets are laminated on the upper and lower sides of the laminated first green sheet, and the laminated body is pressurized while being heated, so that each of the first and second green sheets is pressure-bonded and pressure-bonded. The laminated body is fired at a prescribed temperature for a prescribed time, the upper and lower surfaces of the fired laminated body are polished to obtain desired flatness and parallelism, and the second thick film via (34) is formed on the polished surface. A method of manufacturing a multilayer ceramic substrate, comprising forming a thin film pad (38) connected to a plurality of layers.
JP24782692A 1992-09-17 1992-09-17 Multi-layer ceramics substrate and its manufacture Withdrawn JPH0697660A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24782692A JPH0697660A (en) 1992-09-17 1992-09-17 Multi-layer ceramics substrate and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24782692A JPH0697660A (en) 1992-09-17 1992-09-17 Multi-layer ceramics substrate and its manufacture

Publications (1)

Publication Number Publication Date
JPH0697660A true JPH0697660A (en) 1994-04-08

Family

ID=17169246

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24782692A Withdrawn JPH0697660A (en) 1992-09-17 1992-09-17 Multi-layer ceramics substrate and its manufacture

Country Status (1)

Country Link
JP (1) JPH0697660A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012028730A (en) * 2010-07-21 2012-02-09 Samsung Electro-Mechanics Co Ltd Multi layer circuit board and method of manufacturing the same
US8222540B2 (en) 2009-05-14 2012-07-17 Fujitsu Limited Printed wiring board and electronic-component package
CN115720414A (en) * 2023-01-10 2023-02-28 四川斯艾普电子科技有限公司 Method for forming thick-film anti-ignition circuit board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8222540B2 (en) 2009-05-14 2012-07-17 Fujitsu Limited Printed wiring board and electronic-component package
JP2012028730A (en) * 2010-07-21 2012-02-09 Samsung Electro-Mechanics Co Ltd Multi layer circuit board and method of manufacturing the same
CN115720414A (en) * 2023-01-10 2023-02-28 四川斯艾普电子科技有限公司 Method for forming thick-film anti-ignition circuit board

Similar Documents

Publication Publication Date Title
JP3547146B2 (en) Package for integrated circuit
US4195195A (en) Tape automated bonding test board
US6852569B2 (en) Method of fabricating multilayer ceramic substrate
JPH0697656A (en) Production of ceramic multilayered board
JPH0697660A (en) Multi-layer ceramics substrate and its manufacture
JPH11121527A (en) Mounting of bare chip component, manufacture of ceramic board, the ceramic board and semiconductor device
JPH06232005A (en) Lc composite component
JPH0817965A (en) Electronic component and its preparation
JP2758603B2 (en) Manufacturing method of ceramic multilayer wiring board
JP5185622B2 (en) Multilayer wiring board
JP2001144437A (en) Multilayer ceramic board and method of production
JPH1131632A (en) Method for manufacturing solid-state composite component
JP2000068149A (en) Laminated electronic component and manufacture therefor
JP6500987B2 (en) Laminated wiring board and probe card provided with the same
JP2793446B2 (en) Lamination pressing method for multilayer ceramic substrate
JP2630232B2 (en) Method for manufacturing multilayer wiring board
JP2002151854A (en) Multilayer printed wiring board and manufacturing method therefor
JPH0727989B2 (en) Method for manufacturing ceramic package type semiconductor device
JP4413375B2 (en) Interposer with built-in capacitor and manufacturing method thereof
JPH10294560A (en) Multi-layered wiring board
JP3248345B2 (en) Multilayer ceramic substrate
JPS6226200B2 (en)
JPH0750462A (en) Electronic circuit board
JPH05191047A (en) Manufacture of multilayer ceramic circuit board
JP2001267467A (en) Multilayer ceramic substrate, its manufacturing method and electronic device

Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19991130