JPH05191047A - Manufacture of multilayer ceramic circuit board - Google Patents

Manufacture of multilayer ceramic circuit board

Info

Publication number
JPH05191047A
JPH05191047A JP347392A JP347392A JPH05191047A JP H05191047 A JPH05191047 A JP H05191047A JP 347392 A JP347392 A JP 347392A JP 347392 A JP347392 A JP 347392A JP H05191047 A JPH05191047 A JP H05191047A
Authority
JP
Japan
Prior art keywords
green sheet
lines
buried
conductor
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP347392A
Other languages
Japanese (ja)
Inventor
Shigenori Aoki
重憲 青木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP347392A priority Critical patent/JPH05191047A/en
Publication of JPH05191047A publication Critical patent/JPH05191047A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To eliminate voids on the peripheries of conductor lines and to prevent an interlayer separation from being generated by a method wherein the conductor lines are adhered on a carrier film, a slurry is applied to dry the lines, a green sheet provided its lower part with the conductor lines is formed and the green sheet is laminated on a green sheet with the conductor lines buried therein, is pressed, is formed integrally with the green sheet with the lines buried therein and is subjected to firing. CONSTITUTION:A green sheet 8 with conductor lines 2 buried previously therein is used. Here, as the material for the lines 2, a metal foil of a thickness of 30mum or thereabouts is previously punched out or is subjected to photo-etching and the metal foil formed by patterning is used. A green sheet is formed by a doctor blade method in a state that the lines 2 consisting of this metal foil are adhered on a carrier film, whereby the green sheet with the lines 2 buried therein can be formed. That is, when a green sheet 9 is positioned and abutted on the sheet 8 with the lines 2 buried therein, is pressed and is formed integrally with the sheet 8, voids on the peripheries of the lines 2 can be eliminated and by heating this sheet 9, a ceramic circuit board with good characteristics can be manufactured.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は導体線路の周辺に空隙部
を無くし、性能と信頼性を向上した多層セラミック回路
基板の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multi-layer ceramic circuit board which has no voids around a conductor line and has improved performance and reliability.

【0002】情報処理装置の主体を占めるLSI やVLSIな
どの半導体素子は集積度が向上していることから発熱量
が大きく、そのため耐熱性の優れたセラミックを用いて
多層回路基板が構成されており、この基板上に多数の半
導体素子をマトリックス状に装着して電子回路が作られ
ている。
Semiconductor devices such as LSIs and VLSIs, which occupy the main body of information processing devices, generate a large amount of heat due to their improved degree of integration, and therefore, multilayer circuit boards are constructed using ceramics with excellent heat resistance. An electronic circuit is made by mounting a large number of semiconductor elements in a matrix on this substrate.

【0003】[0003]

【従来の技術】多層セラミック回路基板の製造方法とし
ては、ガラスセラミックスやアルミナセラミックスより
なる粉末と有機バインダ,可塑剤,有機溶剤などを混合
してスラリーを作り、これをドクタブレード法により高
分子よりなるキャリアフィルム上に一定の厚さに塗布
し、乾燥してグリーンシートを形成する。
2. Description of the Related Art As a method for manufacturing a multilayer ceramic circuit board, a powder made of glass ceramics or alumina ceramics is mixed with an organic binder, a plasticizer, an organic solvent, etc. to make a slurry, which is made of a polymer by a doctor blade method. Is applied to a uniform carrier film to a certain thickness and dried to form a green sheet.

【0004】次に、一定の大きさに切断したグリーンシ
ートの必要位置にパンチで穴開けを行った後、この穴に
導体ペーストを充填しバイアホールを形成する。次に、
このグリーンシートの表面にスクリーンプリント法によ
り導体線路を印刷して乾燥させた後、このグリーンシー
トを位置合わせしながら積層し、加圧して一体化し、こ
れを非酸化性雰囲気中で焼成することにより多層セラミ
ック回路基板が作られている。
Next, after punching holes at required positions of the green sheet cut into a certain size, the holes are filled with a conductor paste to form via holes. next,
After printing a conductor line on the surface of this green sheet by screen printing and drying, stacking this green sheet while aligning it, pressurizing it to integrate it, and firing it in a non-oxidizing atmosphere. A multilayer ceramic circuit board is made.

【0005】こゝで、従来のグリーンシートの厚さは一
般に300 μm 程度であり、また導体線路の厚さは30〜50
μm 程度のものが使用されていた。然し、情報処理装置
の小型化と高性能化を推進する必要から多層セラミック
回路基板は薄層化が必要であり、そのため単位層を形成
するグリーンシートの厚さは100 μm 以下にまで薄層化
している。
Here, the thickness of the conventional green sheet is generally about 300 μm, and the thickness of the conductor line is 30 to 50.
Those of about μm were used. However, because it is necessary to reduce the size and performance of information processing devices, it is necessary to reduce the thickness of multilayer ceramic circuit boards.Therefore, the thickness of the green sheets that form the unit layers should be reduced to 100 μm or less. ing.

【0006】一方、配線パターンについてはLSI やVLSI
を駆動するための電流容量を確保する必要上からグリー
ンシートの薄層化に合わせて薄くすることはできない。
図3は従来の製造方法を示す断面図である。
On the other hand, regarding wiring patterns, LSI and VLSI
Since it is necessary to secure a current capacity for driving the green sheet, it cannot be thinned in accordance with the thinning of the green sheet.
FIG. 3 is a sectional view showing a conventional manufacturing method.

【0007】すなわち、同図(A)に示すようにグリー
ンシート1の上に導体ペーストよりなる導体線路2が形
成されており、この上にグリーンシート3を位置決めし
て積層し、加圧しているが、この場合、グリーンシート
1,3が厚く、また、或る程度軟らかいことから、加圧
によって導体線路2をグリーンシート1,3に埋め込む
ことができ、これを焼成することによ密な回路基板が得
られている。
That is, as shown in FIG. 1A, a conductor line 2 made of a conductor paste is formed on a green sheet 1, on which a green sheet 3 is positioned, laminated and pressed. However, in this case, since the green sheets 1 and 3 are thick and soft to some extent, the conductor line 2 can be embedded in the green sheets 1 and 3 by pressurization, and a dense circuit can be formed by firing the green sheets 1 and 3. The substrate has been obtained.

【0008】然し、同図(B)に示すようにグリーンシ
ート4,5が薄くなると、加圧の際のグリーンシート
4,5の変形によっては導体線路2の厚さを吸収するこ
とは不可能となり、導体線路2の周囲に隙間6を生じ
る。
However, as shown in FIG. 2B, when the green sheets 4 and 5 become thin, it is impossible to absorb the thickness of the conductor line 2 due to the deformation of the green sheets 4 and 5 during pressurization. Therefore, a gap 6 is formed around the conductor line 2.

【0009】そのために、焼成を行った後にも隙間を生
じており、これが原因で導体線路2相互の絶縁不良を生
ずると共に、基板剥離が起こり易かった。これらのこと
から、改良が必要であった。
For this reason, a gap is formed even after firing, which causes insulation failure between the conductor lines 2 and easily causes substrate peeling. From these things, improvement was needed.

【0010】[0010]

【発明が解決しようとする課題】多層セラミック回路基
板の形成に当たって、グリーンシートの厚さが100 μm
以下にまで薄くなり、一方、導体線路の厚さが30〜50μ
m のように、グリーンシートの厚さに較べてそれ程には
違わない場合は、グリーンシートを積層して加圧を行っ
てもグリーンシート中に隙間なく完全に埋没させること
は不可能である。
When forming a multilayer ceramic circuit board, the thickness of the green sheet is 100 μm.
The thickness of the conductor line is 30 to 50μ
When the thickness of the green sheet is not so different from the thickness of the green sheet, such as m, it is impossible to completely bury the green sheets in the green sheet without a gap even if the green sheets are stacked and pressed.

【0011】そのため、焼成して生じた多層セラミック
回路基板の導体線路の周辺には隙間が残り、これが原因
で絶縁不良や剥離を生じている。そこで、この解決が課
題である。
Therefore, a gap remains around the conductor line of the multilayer ceramic circuit board produced by firing, which causes insulation failure and peeling. Therefore, this solution is an issue.

【0012】[0012]

【課題を解決するための手段】上記の課題は金属箔をパ
ターン形成した導体線路を高分子よりなるキャリアフィ
ルム上に貼着した後、このキャリアフィルム上にスラリ
ーを塗布した後に乾燥させて、導体線路を下部に備えた
グリーンシートを作る工程と、このグリーンシートにバ
イアを穴開けして後、導体ペーストをバイアに充填して
バイアホールを形成する工程と、このグリーンシートを
位置合わせして積層し、加圧して一体化した後に焼成す
る工程と、を含むことを特徴として多層セラミック回路
基板の製造方法を構成することにより解決することがで
きる。
[Means for Solving the Problems] The above-mentioned problems are solved by applying a conductor line on which a metal foil is patterned onto a carrier film made of a polymer, applying a slurry onto the carrier film, and then drying the conductor to form a conductor. The process of making a green sheet with a line at the bottom, the process of making a via hole in this green sheet, then filling the via with conductive paste to form a via hole, and aligning and stacking this green sheet It is possible to solve the problem by configuring a method for manufacturing a multilayer ceramic circuit board, which comprises the step of applying pressure, integrating, and then firing.

【0013】[0013]

【作用】発明者は導体線路の厚さが厚く、グリーンシー
トの変形によって導体線路をグリーンシート中に埋没さ
せることが不可能なことから、予め導体線路をグリーン
シート中に埋没したものを使用するものである。
The inventor uses a conductor line which is previously buried in the green sheet because the conductor line is thick and it is impossible to bury the conductor line in the green sheet due to deformation of the green sheet. It is a thing.

【0014】こゝで、導体線路は予め30μm 程度の厚さ
の金属箔を打ち抜き或いはフォトエッチングしてパター
ン形成したものを使用する。この理由は量産に当たって
は導体線路の種類は限られており、比較的廉価で形成で
きることによる。
In this case, the conductor line is a metal foil having a thickness of about 30 μm, which is punched or photoetched to form a pattern. The reason for this is that the type of conductor line is limited in mass production and can be formed at a relatively low cost.

【0015】そして、この金属箔よりなる導体線路をキ
ャリアフィルムの上に貼着した状態でドクタブレード法
によりグリーンシートを形成することにより導体線路を
埋没したグリーンシートを作ることができる。
Then, a green sheet in which the conductor line is buried can be produced by forming the green sheet by the doctor blade method with the conductor line made of the metal foil stuck on the carrier film.

【0016】図1は本発明の原理図であって、導体線路
2を埋没したグリーンシート8の上にグリーンシート9
を位置決めして当接し、加圧して一体化すれば隙間を無
くすることができ、これを加熱することにより特性のよ
いセラミック回路基板を作ることができる。
FIG. 1 is a principle view of the present invention, in which a green sheet 9 is placed on a green sheet 8 in which a conductor line 2 is buried.
By positioning and abutting, and applying pressure to integrate them, a gap can be eliminated, and by heating this, a ceramic circuit board with excellent characteristics can be manufactured.

【0017】[0017]

【実施例】実施例1:下記の材料を用いてグリーンシー
トを形成した。 硼硅酸ガラス粉末( 平均粒径5μm )・・・・・・・・
・・・・50重量部 アルミナ粉末 (平均粒径5μm )・・・・・・・・
・・・・50重量部 ポリビニルブチラール(バインダ) ・・・・・
・・・・10 〃 ジブチルフタレート (可塑剤) ・・・・・
・・・・5 〃 アセトン (溶剤) ・・・・・
・・・・400 〃 を加え、ボールミルを用いて混練してスラリーを作っ
た。
EXAMPLES Example 1: A green sheet was formed using the following materials. Borosilicate glass powder (average particle size 5 μm)
・ ・ ・ 50 parts by weight Alumina powder (average particle size 5 μm)
・ ・ ・ 50 parts by weight Polyvinyl butyral (binder) ・ ・ ・ ・ ・
・ ・ ・ ・ 10 〃 Dibutyl phthalate (plasticizer)
・ ・ ・ ・ 5 〃 Acetone (solvent) ・ ・ ・ ・ ・
・ ・ ・ ・ 400 〃 was added and kneaded using a ball mill to make a slurry.

【0018】また、厚さが50μm の銅(Cu)箔を打ち抜い
て4種類の導体線路を準備し、図2に示す工程により本
発明に係る多層セラミック回路基板を形成した。先ず、
厚さが100 μm のキャリアフィルム( ポリエチレンテレ
フタレート) 10の上に4種類の導体線路11を貼着した。
(以上同図A) 次に、この上にスラリーをドクターブレード法により塗
布した後、乾燥して厚さが100 μm のグリーンシート12
を形成した。( 以上同図B) 次に、グリーンシート12の必要な位置を穴開けして後、
スクリーン印刷法により銅ペーストを充填してバイアホ
ール13を形成した。( 以上同図C) 次に、キャリアフィルム10より剥がした4種類のグリー
ンシート12を位置合わせして積層し、100 ℃で10MPaの
条件で積層して一体化し積層体14を得た。(以上同図
D) 次に、この積層体14をN2気流中で1000℃で焼成して多層
セラミック回路基板15を得た。( 以上同図E) この基板を切断して調べた結果、導体線路11はガラスセ
ラミックスに密着しており、また層間剥離などの兆候は
全く認められなかった。
Further, a copper (Cu) foil having a thickness of 50 μm was punched out to prepare four kinds of conductor lines, and the multilayer ceramic circuit board according to the present invention was formed by the steps shown in FIG. First,
Four types of conductor lines 11 were attached on a carrier film (polyethylene terephthalate) 10 having a thickness of 100 μm.
(A in the same figure) Next, the slurry is applied onto this by the doctor blade method and then dried to obtain a green sheet 12 having a thickness of 100 μm.
Formed. (Above B in the same figure) Next, after making holes at required positions of the green sheet 12,
Via holes 13 were formed by filling a copper paste by a screen printing method. Next, four types of green sheets 12 peeled from the carrier film 10 were aligned and laminated, and laminated at 100 ° C. under the condition of 10 MPa to be integrated to obtain a laminated body 14. (The above D in the same figure) Next, this laminated body 14 was fired at 1000 ° C. in an N 2 stream to obtain a multilayer ceramic circuit board 15. As a result of the cutting and examination of this substrate, the conductor line 11 was in close contact with the glass ceramics, and no sign of delamination was observed.

【0019】[0019]

【発明の効果】本発明の実施により導体線路の周辺に空
隙がなく、また層間剥離などがない多層セラミック回路
基板を製造することができる。
By implementing the present invention, it is possible to manufacture a multilayer ceramic circuit board having no void around the conductor line and no delamination.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の原理図である。FIG. 1 is a principle diagram of the present invention.

【図2】本発明に係る製造工程を示す断面図である。FIG. 2 is a cross-sectional view showing a manufacturing process according to the present invention.

【図3】従来法による積層, 加圧, 焼成工程を示す断面
図である。
FIG. 3 is a cross-sectional view showing a stacking process, a pressurizing process, and a baking process according to a conventional method.

【符号の説明】[Explanation of symbols]

1,3,4,5,8,9,12 グリーンシート 2,11 導体線路 6 隙間 10 キャリアフィルム 13 バイアホール 15 多層セラミック回路基板 1,3,4,5,8,9,12 Green sheet 2,11 Conductor line 6 Gap 10 Carrier film 13 Via hole 15 Multilayer ceramic circuit board

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 金属箔をパターン形成した導体線路を高
分子よりなるキャリアフィルム上に貼着した後、該キャ
リアフィルム上にスラリーを塗布した後に乾燥させて、
導体線路を下部に備えたグリーンシートを作る工程と、 該グリーンシートにバイアを穴開けして後、導体ペース
トを該バイアに充填してバイアホールを形成する工程
と、 該グリーンシートを位置合わせして積層し、加圧して一
体化した後に焼成する工程と、 を含むことを特徴とする多層セラミック回路基板の製造
方法。
1. A conductor line formed by patterning a metal foil is attached onto a carrier film made of a polymer, and a slurry is applied onto the carrier film and then dried.
A step of forming a green sheet having a conductor line at the bottom, a step of forming a via hole in the green sheet and then filling the via with a conductor paste, and aligning the green sheet. Laminating, pressurizing and integrating, and then firing, and a method for manufacturing a multilayer ceramic circuit board.
JP347392A 1992-01-13 1992-01-13 Manufacture of multilayer ceramic circuit board Withdrawn JPH05191047A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP347392A JPH05191047A (en) 1992-01-13 1992-01-13 Manufacture of multilayer ceramic circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP347392A JPH05191047A (en) 1992-01-13 1992-01-13 Manufacture of multilayer ceramic circuit board

Publications (1)

Publication Number Publication Date
JPH05191047A true JPH05191047A (en) 1993-07-30

Family

ID=11558304

Family Applications (1)

Application Number Title Priority Date Filing Date
JP347392A Withdrawn JPH05191047A (en) 1992-01-13 1992-01-13 Manufacture of multilayer ceramic circuit board

Country Status (1)

Country Link
JP (1) JPH05191047A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6488795B1 (en) * 1999-10-27 2002-12-03 Murata Manufacturing Co. Ltd Multilayered ceramic substrate and method of producing the same
JP2002353626A (en) * 2001-05-28 2002-12-06 Kyocera Corp Multilayer wiring board and method of manufacturing the same
WO2008010642A1 (en) * 2006-07-19 2008-01-24 Joinset Co., Ltd Ceramic component and method of manufacturing the same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6488795B1 (en) * 1999-10-27 2002-12-03 Murata Manufacturing Co. Ltd Multilayered ceramic substrate and method of producing the same
JP2002353626A (en) * 2001-05-28 2002-12-06 Kyocera Corp Multilayer wiring board and method of manufacturing the same
JP4693284B2 (en) * 2001-05-28 2011-06-01 京セラ株式会社 Multilayer wiring board and manufacturing method thereof
WO2008010642A1 (en) * 2006-07-19 2008-01-24 Joinset Co., Ltd Ceramic component and method of manufacturing the same
KR100821274B1 (en) * 2006-07-19 2008-04-10 조인셋 주식회사 Chip Ceramic Electronic component
US7791450B2 (en) 2006-07-19 2010-09-07 Joinset Co., Ltd. Ceramic component and method of manufacturing the same

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Effective date: 19990408