JPS63261435A - Parity error check system - Google Patents

Abstract

PURPOSE:To reduce the size of a circuit and to reduce cost by forming a parity circuit only by one mask ROM 1 consisting of 64K even if the capacity of a main memory RAM or a parity RAM is increased. CONSTITUTION:The mask ROM 12 inputs 8-bit parity data 11 from the parity RAM 10, 3-bit address information specifying one of 8 bits, an output bit from a parity generating circuit 13 and a read/write control signal 120 as addresses. In a reading mode, one bit specified by the address information out of 8 bits outputted from the RAM 10 is compared with the output bit of the circuit 13 and the compared result is outputted. In a writing mode, the ROM 12 replaces the specified one bit out of 8 bits from the RAM 10 by the output logic of the circuit 13. Other 7 bits not specified by the address information are directly outputted and the updated data are written in the RAM 10. Consequently, the size of the circuit can be reduced and the cost can be also reduced.

Description

[Detailed Description of the Invention] [Summary] The present invention is a RAM for parity of 8 bits, 7 bits x 8, rather than a 1 bit x 64 RAM for example.
This circuit uses AM to construct a parity check and parity update circuit, which was conventionally created using random logic, using a mask ROM. When using an 8-bit x 8 parity RAM, each of the 8 bits 0 to 7 of address 0 stores each parity for data at addresses 0 to 7 of the main memory RAM. The parity for the data at address 0 in the main memory RAM is only the least significant bit of the 8 bits at address O in the parity RAM.

The address of the mask ROM includes 8-bit output data of the parity RAM, 3-bit address information specifying one of the 8 bits, an output bit from the parity generation circuit, and a read or write specification signal. In the parity RAM read mode, the mask ROM outputs a test result of one bit specified by the address information among the eight output bits of the parity RAM and the output bit of the parity generation circuit.

Furthermore, in the write mode of the parity RAM,
Of the 8 bits output from the parity RAM, 1 bit specified by the address information is replaced with the logic output from the parity generation circuit, and the other 7 bits not specified by the address information ('11) are used as is. The 8-bit output data, in which only 1 bit has been updated, is output from the mask ROM.
M is written again.

According to the present invention, an 8-bit x 8 RAM, which is cheaper than a 1-bit x 64 RAM, is used, and data can be stored in 8 bits.
If it is a bit, main memory RAM or parity RAM
Even if the number of 8 disks increases, it can be configured with one 64 mask ROM, and the circuit scale can be reduced.

[Industrial application field]

The present invention relates to an error detection method for read/write information in a main memory RAM in order to improve the reliability of the main memory device. Particularly, in the present invention, when writing the parity of write data input to the main memory RAM to the parity RAM and reading the parity to perform a parity check, the logic related to the parity check and parity update is executed using a mask ROM. Regarding the parity check method.

[Traditional technique]

BACKGROUND ART As information systems become more sophisticated and larger in scale, the need for technology to make each device even more reliable has increased. In particular, it is important to ensure the reliability of the stored information in the main memory that stores programs and data necessary for the operation of the central processing unit. The method of error detection and correction technology that corrects errors becomes increasingly important.

Techniques that perform error correction rather than error detection generally require a large number of redundant bits, and there are also conditions such as encoding technology for error correction, an increase in the number of logic circuits for correction, and correction time. .

For example, main memory requires high speed, so
An error detection scheme or a single error correction double error detection code is used. Error detection method is the basis of high reliability.
It is important not to overlook errors in the occurrence of failures or malfunctions.

Generally, a parity check method is used to detect errors in one bit. The parity check encoding method is N
This is a method in which one parity bit is added to each information bit to obtain all information, and the number of bits that are logical 1 in the information is set to an even number or an odd number. When targeting the main memory RAM, the exclusive OR of write data is used as a parity bit, and this bit is added to the main memory RAM (1, RA).
The parity of data written to M and output is similarly checked using an exclusive OR circuit.

When parity is added to write data, 1 bit of parity is added to each data, so the required number of parities to be written is equal to the number of addresses in main memory RAM, which increases the memory capacity. Accordingly, the area for storing parity also increases. A method has been put into practical use in which an area for storing parity is provided separately from the main memory RAM, and is installed as a parity RAM, and the parity is updated and checked using random logic.

[Problem that the invention seeks to solve]

As the capacity of memory increases, the price of parity RAM becomes a problem. For example, if the data is 8 bits and the main memory RAM uses 64 bytes, the parity RAM needs to use 64 bytes. Generally 1 bit x 6
8-bit x 8 RAM is lower than 4-bit RAM.
Since the parity is i1i, a parity RAM has conventionally been constructed using an 8-bit×8 RAM, and a parity circuit for updating and checking parity has been constructed using random logic. However, random logic has the drawbacks of increased circuit scale and increased packaging density.

The present invention eliminates such conventional drawbacks and
In the parity circuit using the parity RAM of
To provide a parity check method that can reduce cost and further reduce circuit scale by replacing with OM.

[Means for resolving the shortcomings]

The configuration block diagram of the parity check method of the present invention is shown in the first diagram.
As shown in the figure. Parity RAM10 has 8 bits x 8 RAM
For example, in each of the 8 bits 0 to 7 of address 0, each parity for each data of addresses 0 to 7 of the main iQ RAM is stored. The mask ROM 12 stores the 8-bit parity data 11 read from the parity RAM 10 and the main memory RAM.
The output bit from the parity generation circuit 13 that generates parity for the data read from or written to the main memory RAM (Do-D7) and the MI to the parity R
Parity address (A2.81.AO) that specifies which part of the 8-bit parity read from O is valid.
) and 1 bit of the read/write control signal 120, a total of 13 bits, are input as an address. In the read mode of the parity RAM 10, the mask ROM 12 reads the parity address (A2.AI, A
1 bit specified by O) and the parity generation circuit 13
The comparison result is compared with the output bit from . In the write mode, the mask ROM 12 transfers one bit defined as 1 of the 8-bit output parity data 11 of the parity RAM 10 specified by the parity address (A2, AI, AO) to the parity generation circuit 1.
The other 7 bits not designated by the parity address are output unchanged. The updated data is written to the parity RAM10.

In the read mode, the bit of the comparison result at the bit position specified as 1 by the parity address (82.AI, 80) is sent to the parity error launch printer 14.

[For production]

In the present invention, for example, the parity RAM 10 of 64 bits is set to 1.
RAM is 8 bits x 8 instead of 64 bits RAM.
Using AM, the parity check and update circuit, which was conventionally created using random logic, has been replaced with mask ROM1.
2.

The address of the mask ROM includes 8-bit output parity data of the parity RAM, and 3-bit address information (A2.A) specifying 1 bit of the 8 bits.
I, AO), parity generation '1': Output bit and read or write control signal 120 from the circuit 13. In the read mode, the mask ROM 12 outputs the test result of 1 bit specified by the address information among the 8 bits output from the parity RAM 10 and the output bit of the parity generation circuit.

In addition, in the write mode, the mask ROM 12
replaces 1 bit specified by the address information among the 8 bits output from the parity RAM 10 with the logic output from the parity generation circuit 13.

The other 7 bits not specified by the address information are output as is from the mask ROM, and the 8-bit output data with only 1 bit updated is stored in the parity RAM 10.
will be written again.

According to the present invention, even if the capacity of the main memory RAM and parity RAM increases, a parity circuit can be configured with one 64-bit mask ROM, and the circuit scale can be reduced.

〔Example〕

Next, the parity check method of the present invention will be explained with reference to the drawings.

In the present invention, 64-bit parity RAM 10 is set to 1
Not a 64-bit RAM (, 8-bit RAM
Use AM. The circuit size is reduced by replacing a part of the circuit conventionally made using Langmurosic with a mask ROM 12.

The configuration block diagram of the parity check method of the present invention is shown in the first diagram.
As shown in the figure. When the data in the main memory RAM is 8 pins, 1 bit of parity is added to 1 byte of data. If the main memory RAM (not shown) has 64 bytes, 64 bits of parity are required, and the parity RAM 10 requires 64 chips. 64
In 64K RAM that stores the parity of Pino 1 in RAM is cheaper.

When using an 8-bit x 8 RAM, for example, each pin 1- of 8 bits 0 to 7 of address O stores each parity for data of addresses O to 7 of the main memory RAM. Bit O is main 2f,! Parity of data at address O of RAM, bit 1 is the main memory RA
The parity of address 1 of M is stored. Similarly, bit 7 stores the parity of address 7 of the main memory RAM. In the 8-bit data at address 1 of parity RAM10, the Oth bit stores the parity for address 8 of main memory RAM. The same applies hereafter. That is, the parity for 8 (VA) consecutive addresses in the main memory RAM becomes one word of parity data in the parity RAM.

The parity for the data at address O in the main memory RAM is only the least significant bit of the 8 bits at address O in parity RAM10. Therefore, parity RAMl0
When address O is specified, only the least significant bit is required as parity for address 0 of the main memory RAM. The upper 7 bits other than the least significant bit are not required for parity update or parity check for the data at address 0 of the main 2ifi RAM. When parity checking is performed on data in the main memory RAM, that is, in the read mode, the parity RAM 10 is also in the read mode. In the read mode, a parity check is performed on the data at address 0 of the main memory RAM using only the required least significant bit parity of the output 8-bit parity. Then, the parity of the least significant bit is written directly to the parity RAM 10 again. Furthermore, when updating the contents of main memory RAM address O, the lowest parity bit of address O of parity RAM 10 is also updated. This is write mode. In write mode, at the same time as writing data other than parity to address O of main memory RAM,
The parity generated from the parity generation circuit 13 inputting the data is sent to the parity RA via the mask ROM 12.
It is written to the least significant pinto, ie, bit 0, of address O of M10. Other parity data from bit 1 to bit 7 is output from parity RAM 10 and mask ROM 12.
The parity data is written to the parity RAM 10 as is as the same parity data. That is, in the write mode, only the necessary 1 bit of the contents of each address in the parity RAM 10 is updated, and the other 7 bits are not updated.
It is written as is into the parity RAM 10.

Conventionally, a circuit that executes operations for reading and writing the parity RAM 10 using hardware has been implemented using random logic.

However, in the present invention, as shown in FIG.
Replace Mτ2 with the random logic. This allows the circuit scale to be reduced, the mounting area to be reduced, and the cost to be reduced.

The address input of the mask ROM 12 is the parity RAM 1.
8 bits of output parity data 11 of 0, 1 bit of output 130 of parity generation circuit 13, parity RAM
3 bits of addresses AO-A2 for setting 1 bit of 8 bits of parity data of each address of l0 as 1, and a read/write control signal 120 for specifying whether the mode is read mode or write mode. This is 1 bit.

The address lines of the mask ROM 12 have a total of 13 bits. The input of the parity ordering circuit 13 is the write data (DO-D7) from the central processing unit (CPU) etc. to the main memory RAM in the write mode, and the main memory RA in the read mode.
This is 8-bit data (Do-D7) read from M. The parity generation circuit 13 generates parity for this 8-bit data by exclusive OR, and outputs the parity to the output line 13.
Output to 0.

During the parity check in the read mode, the output 130 of the parity generation circuit 13 is focused on the parity RAM10.
It is compared with 1 bit specified by address AO-A2 out of 8 bits of parity data output from . The comparison result has already been created in the mask ROM 12. 8-bit data is output to the output 121 of the mask ROM 12, one bit of which is the comparison result. In read mode, read/write control signal 1
20 is O. For example, the O bit of the 8 bits of parity data in parity RAM 10 is 1 from 80 to A2.
If specified, the 3-bit address (A2.Al
, 'AO) is (000).

For example, as shown in FIG. 2(A), the mask ROM 12
The data (01010101) output from parity RAM 10 is input from address 7 to O, and address 1
0, 9.8 correspond to A2, At, AO, respectively,
0,0.0 is input. In addition, a logic O specifying the read mode is input to address 12, and address 11 is inputted to
The logic 1 output from the parity generation circuit 13 is input. If the contents of address O of the main memory RAM are normal and the output 130 of the parity generation circuit 13 is 1, the parity RA
The least significant bit of the 8 bits of parity data at address O of M10 also becomes 1. Therefore, at this time, as shown in FIG. 2(B), the output data of the mask ROM 12 has the upper 7 bits set to 0 and the least significant bit set to 1. This logic 1 means a conveyor check OK signal. However, main memory R
The contents of AM address 0 are abnormal and the parity generation circuit 12
The output of the parity RAM 10 may be O, and the least significant bit of the address O of the parity RAM 10 may be 1.

For example, as shown in FIG. 2(A'), the mask ROM1
The data output from the parity RAM 10 is input to addresses 7 to O of 2, and this data is assumed to be the same as in (A). Also, A2. A.I.

Addresses 10, 9.8 corresponding to AO are also the same as (A) (
0, 0, 0) is input, and address 12 is also input with a logic 0 specifying the read mode. However, the address 11 input from the output line 130 of the parity generation circuit 13 is set to logic 1, unlike in (A). At this time, since the result of the conveyor check means a mismatch, the mask ROM 12
As shown in FIG. 2 (B'), the least significant bit is 0 and the other 7 bits are also 0. f6, that is, 8 bits of ALLO are output to the output line 121. As a result of the conveyor check, if they do not match, an error flag is launched in the parity error launch flip-flop 14.

On the other hand, even in write mode, the 8-bit parity data at address O of parity RAM 10 is stored in mask ROM 1.
It is input to address 2. On the other hand, the new parity is
This is the output of the parity generation circuit 13. In this case, it is necessary to replace the least significant bit of address 0 outputted from the parity RAM 10 with the output logic of the parity generation circuit 13, and leave the other upper 7 bits of parity data as is. Parity addresses 82 to AO are similar and designate the 8-bit valid parity output from parity RAM 10. For example, mask ROM12
If you set AO to ALL O from A2, parity RAMl
Data conversion is performed so that the O-th bit of the output of 0 is replaced with the output logic of the parity generation circuit 13. and,
The contents of the mask ROM 12 are determined so that a total of 7 bits from the other epinodes to the 7th bit remain unchanged.

Therefore, in light mode (A2.Al, AO) = <
0.0. O), the output line 121 of the mask ROM 12
The upper 7 bits of the 8 bits are the same as the upper 7 bits of the address line 11, but only the least significant bit has the same logic as the output logic of the parity generation circuit 13.

For example, FIG. 3 shows mask ROM1 in write mode.
Address information input to 2 +8 (A') and output data (
As shown in FIG. 3 (8), addresses 7 to O are output parity data (01010101) of M10 to parity R, and the least significant bit is 1. Address 10,9°8 is Δ2. Corresponding to AI and AO, respectively, specify the least significant bit of the parity data (0,
0°0) is input, and address 11 is a new parity output from the parity generation circuit 13, and logic 0 is input. This logic O is different from the logic input to address O. Furthermore, a logic 1 representing write mode is input to address 12. When the address information shown in (A″) is input to the mask ROM 12, its output is shown in FIG.
From the top (OI O10100) as shown in B#)
The upper 7 bits are the same as from addresses 7 to 1.
In itEf, only the least significant bit becomes logic O, which is different from logic 1 at address O. The data in which only the least significant bit has been updated is written to address O of parity RAM 10 again.

In this way, when reading, the mask ROM 12 performs parity check logic, and when writing, the designated bit is updated to the logic of the output 130 of the parity generation circuit 13, while the other 7 bits are left unchanged. The correct 8-pin output data 121 corresponding to the 13-bit address information input to the mask ROM 12 is all mask R.
Stored in OMI2. That is, the logic of all answers to the 13-bit address is stored in the mask ROM 12. If the mask ROM 12 is used in this way, logical operations such as parity check and parity update can be performed with a single 64-bit mask ROM, and if the data is 8-bit data in the main memory RAM of any capacity, the 64-bit mask ROM can be used. Nino Mask R
One OM is enough. In other words, main memory RAM and parity R
No matter how large the capacity of AM10 becomes, the data is 8 bits, so addresses 0 to 7 of mask ROM12
is 8 bits. That is, a total of 13 addresses are required for the mask ROM 12, and since the data is 8 bits, the size of the mask ROM is 64.

It has no relation to the memory capacity of the main memory RAM or parity RAM10.

Next, the timing in read mode and write mode of the circuit of FIG. 1 according to the parity check method of the present invention will be explained.

The respective timing charts are shown in FIGS. 4 and 5. - The E clock on the top is a synchronous clock signal when reading or writing to the main memory RAM and parity RAM 10. Hereinafter, the word RAM refers to main memory R.
AM and parity RAM.

In the timing chart of FIG. 4 in the read mode, the falling edge of the RD double signal is a signal indicating the read state of the RAM. Do-D7 is data from the main memory RAM. The PC output is an output signal of the parity circuit 13. A
The signals from O to A15 are address lines for RAM.
Of these, three bits AO to A2 are input to addresses 8, 9 and 10 of the mask ROM, respectively. Also, π
l], the PG ratio output is input to the mask ROM, and the RD read signal is input to the output enable of the mask ROM 12 via the gate circuit 16, and when RD=O, the mask ROM 12 is enabled. AO~A2,RD
, PG ratio output are all determined, the address input of the mask ROM 12 is determined. Thereafter, the output signal of the mask ROM 12 is output after a delay time of the mask ROM 12 has elapsed. The timing of output data from the mask ROM 12 is shown at the bottom of the timing chart.

The read signal RD of the RAM is 4 times from the rising edge of the E clock.
After Or+s, it becomes a logic 0 and reading from the RAM is performed. At the rising edge of RD, a parity check is performed, and the resulting logic is latched into the parity error lunch front panel 14.

Data DO-D7 is 15Qn from the rising edge of E clock.
Output after s. Data up to DO-'D7 is input to the parity generation circuit 13, and the PC output is determined 50 ns later. After determining the PC output, the mask R has already been set.
All address inputs of OM12 have been determined. After determining the PC output, the mask ROM is processed with a delay of 100 n3.
12 is output. Therefore, there is a margin of α-100 ns before the rise of the RD signal, that is, the timing at which the parity error is latched into the flip-flop 14, and the timing in the read mode is accurately executed.

Next, the timing in the light mode will be explained using the fJS5 diagram. When writing, P of the parity generation circuit 13
It is necessary to replace it with the bit specified by Δ2 from AO among the 8-bit output validity data of the G ratio output parity RAM10 and write it into the parity RAM10 again. Therefore, the timing in the light mode is more severe than the timing in the read mode. Particularly in the write mode, reading from the mask ROM 12 is slow, which poses a problem, but it will be shown below that there is no timing problem.

Addresses AO-A15 are specified after 190 r+s from the falling edge of the E clock, and the WR multiplication signal, the write designation signal, falls 4 times after the rising edge of the E clock.
It will be after 003. Further, after the address is determined and the write mode is designated, the CPU data Do-I)7 is determined 160 nsO after the rise of the E clock. After the data from DO to D7 are determined, the PC output of the parity generation circuit 13 is determined 22n3 later. All addresses of the mask ROM 12 are determined at the time when the PG ratio output of the parity generation circuit 13 is determined. If the access time of the mask ROM 12 is 100 ns, the output of the mask ROM 12 is determined 100 ns after the output from the PC. On the other hand, writing to the parity RAM 10 occurs when the WR signal rises. This rise is E
- 20ns after the next falling edge of the clock.

The data written to the parity RAM 10 must already be determined at the rising edge of the WR multiplication signal. In the above example, from the next falling edge of the E clock, 980
The output of the mask ROM 12 has been determined three times before. Therefore, 11F3 ns before the rise of the WR double signal, the mask RO
This means that the output of M12 has been determined. Therefore, data can be written to parity RAM 1.0. Even though the data in the parity RAM 12 must be determined 50 ns before the rise of the WR multiplication signal, writing to the parity RAM 12 is possible.

[Brief Description of the Drawings] Fig. 1 is a block diagram of the structure of the parity check method of the present invention, Fig. 2 is an example of input/output data of a mask ROM using the parity check method of the present invention in read mode, and Fig. 3 4 is a diagram showing an example of input/output data of a mask ROM using the parity check method of the present invention in write mode; FIG. 4 is a timing chart diagram of the circuit of FIG. 1 according to the parity check method of the present invention in read mode; FIG. 2 is a timing chart of the parity circuit of FIG. 1 in a write mode according to the parity check method of the present invention. FIG. 10... Parity RAM. 11... Parity data, 12... Mask ROM. 13...Parity generation circuit, 14...1 parity error flag lunch stopper, 15.16...Gate circuit, 130...Output bit of parity generation circuit ())G output), Δ0 to A2 ...Parity address, 120...Read/write control signal. Patent applicant Fujitsu Kiden Ltd. Figure 2

Claims (3)

[Claims] (1) Parity generation circuit (13) that generates parity for write data and read data to main memory RAM
), a parity RAM (10) that stores parity data for write data to the main memory RAM having a bit width corresponding to the number of consecutive addresses of the main memory RAM; (10)
The parity data output from the parity generation circuit (13), the parity bit output from the parity generation circuit (13), the parity address that specifies the bit position to be valid in the parity data, and the address signal that specifies read or write. In the read mode, at least the comparison result between the parity logic output from the parity generation circuit (13) and the bit specified by the parity address of the parity data is output, and in the write mode, , replacing the parity of the bit specified by the parity address among the parity data read from the parity RAM (10) with the parity output from the parity generation circuit (13), which is not specified by the parity address. A parity check system comprising: a read-only memory (12) for forming write data to the parity RAM (10) with bits at positions unchanged. (2) The read-only memory (12) has a mask RO
The parity check system according to claim 1, characterized in that it is formed of M. (3) The number of bits of each word of the parity RAM (10) is equivalent to the bit width of read/write data in the main memory RAM, and the read-only memory (12) addresses parity data with a bit width equal to the data width. The parity check method according to claim 1, wherein the parity check method is input as follows.