JPS6325985A - Semiconductor photodetector - Google Patents
Semiconductor photodetectorInfo
- Publication number
- JPS6325985A JPS6325985A JP61167825A JP16782586A JPS6325985A JP S6325985 A JPS6325985 A JP S6325985A JP 61167825 A JP61167825 A JP 61167825A JP 16782586 A JP16782586 A JP 16782586A JP S6325985 A JPS6325985 A JP S6325985A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- inp
- gainas
- electrode
- diffusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 4
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 claims abstract description 18
- 239000012535 impurity Substances 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 230000031700 light absorption Effects 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 abstract description 13
- 238000000034 method Methods 0.000 abstract description 8
- 229910004205 SiNX Inorganic materials 0.000 abstract description 6
- 229910052793 cadmium Inorganic materials 0.000 abstract description 2
- 238000003486 chemical etching Methods 0.000 abstract description 2
- 229910052725 zinc Inorganic materials 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 37
- 230000000694 effects Effects 0.000 description 3
- 230000000630 rising effect Effects 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- 101100490904 Emericella nidulans (strain FGSC A4 / ATCC 38163 / CBS 112.46 / NRRL 194 / M139) alnA gene Proteins 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier
- H01L31/103—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PN homojunction type
- H01L31/1035—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier being of the PN homojunction type the devices comprising active layers formed only by AIIIBV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022416—Electrodes for devices characterised by at least one potential jump barrier or surface barrier comprising ring electrodes
Abstract
Description
【発明の詳細な説明】
〔半既要〕
本発明は、 ＩｎＰ／ ＧａＩｎＡｓ ＰＩＮ型ホトダ
イオードにおいて、Ｐ側コンタクト抵抗を低減するため
、ＩｎＰ窓層を一部除去し、ＧａＩｎＡｓ光吸収層上に
直接Ｐ側コンタクトを形成することにより、コンタクト
抵抗の低減、従って順方向立ち上り電圧の低減による素
子の直列抵抗低減を行うものである。Detailed Description of the Invention [Semi-required] The present invention provides an InP/GaInAs PIN photodiode in which a part of the InP window layer is removed and a P layer is formed directly on the GaInAs light absorption layer in order to reduce the P-side contact resistance. By forming the side contacts, the series resistance of the element is reduced by reducing the contact resistance and therefore the forward rising voltage.
ＧａＩｎＡｓを光吸収層とする ＩｎＰ／ ＧａＩｎＡ
ｓ ＰＩＮ型ホトダイオードは、光通信に用いられる１
、３μｍおよび１．５５μ葎波長の光に対して高い量子
効率を有し、また素子の構造が簡単であるため製造歩留
りが高く、低コストであり、高い信頼性をもつため、数
百メガビットの中容量光通信システムにおいて重要なデ
バイスとなっている。本発明はかかる半導体受光素子に
関するものである。InP/GaInA with GaInAs as the light absorption layer
s PIN type photodiode is used for optical communication.
, has high quantum efficiency for light with wavelengths of 3 μm and 1.55 μm, and the simple structure of the device allows high manufacturing yield, low cost, and high reliability. It has become an important device in medium-capacity optical communication systems. The present invention relates to such a semiconductor light receiving element.
従来の ＩｎＰ／ ＧａＩｎＡｓ ＰＩＮ型ホトダイオ
ードは、第４図に示すように、選択的にＰ形不純物が拡
散されたＩｎＰの表面層にＰ側コンタクトを形成する構
造となっており、電極としては、信頼性の面からＡｕ／
Ｐ ｔ／ Ｔ ｉ ３層構造電極が用いられている。As shown in Figure 4, the conventional InP/GaInAs PIN type photodiode has a structure in which a P-side contact is formed on an InP surface layer in which P-type impurities are selectively diffused, and it is not reliable as an electrode. Au from a sexual perspective/
A Pt/Ti three-layer structure electrode is used.
なお、第４図において、１１はｎ”−ＩｎＰ基板、１２
はｎ−−ＩｎＰ層（バッファ層）、１３はｎ −−Ｇａ
ｌｎＡｓ層（光吸収層）、１４はｎ −ＩｎＰ窓層、１
５はｐ＋層、１６はＳ ｉ Ｎ ＸＰＱ、２０はＴｉ１
ｌＱ１７． ｐｔ膜１Ｂ、 Ａｕ１ｌＱ１９の３層
構造からなるＰ ＩＩＩ電掻、２１はＡｕＧｅＮ側電極
である。In addition, in FIG. 4, 11 is an n''-InP substrate, 12
is n--InP layer (buffer layer), 13 is n--Ga
lnAs layer (light absorption layer), 14 is n-InP window layer, 1
5 is p+ layer, 16 is S i N XPQ, 20 is Ti1
lQ17. A P III electrode has a three-layer structure of a PT film 1B and Au11Q19, and 21 is an AuGeN side electrode.
光２２はＩｎＰ窓層１４の表面から入射される。Light 22 is incident on the surface of InP window layer 14 .
第４図に示す従来構造においてｐ＋領域１５上にＡ ｕ
／ Ｐ ｔ／ Ｔ ｉ電極２０によりＰ（ＩＩＪコンタ
クトを形成する場合、
■ｐ＋領域１５の表面濃度が拡散法またはイオン注入法
によりｐ＋ドーピングを行った場合、１〜２Ｘ１０ｃｍ
−’程度と低く、
■ＩｎＰの禁制帯幅が１．３５ ｅＶと大きい、ことに
より順方向立ち上り電圧が太き（なり、従ってコンタク
ト抵抗が大きくなるという問題を住した。In the conventional structure shown in FIG. 4, A u
/ P t / Ti When forming a P (IIJ contact) with the i electrode 20, ■ When the surface concentration of the p + region 15 is p + doped by a diffusion method or an ion implantation method, it is 1 to 2 x 10 cm.
(1) The forbidden band width of InP is as large as 1.35 eV, resulting in a large forward rise voltage (and therefore a large contact resistance).
電極２０はアロイ型の電極ではなく、表面が単に接触し
ているだけであるので、バイアスがかからない太陽電池
のようなＯバイアスの場合、コンタクト抵抗が直列抵抗
に影響を及ぼし、出力のリニアリティが低入射パワーか
ら高入射パワーにわたって悪く、表面濃度を前記の値よ
りもより高くしなければならない。Since the electrode 20 is not an alloy type electrode and the surfaces are simply in contact, in the case of an O bias such as a solar cell where no bias is applied, the contact resistance will affect the series resistance and the output linearity will be low. It is poor from incident power to high incident power, and the surface concentration must be made higher than the above values.
本発明はこのような点に鑑みて創作されたもので、ＰＩ
Ｎ型ホトダイオードにおけるＰ （ＪＩＩＪ電極のコン
タクト抵抗が従来例よりも小になったデバイスを提供す
ることを目的とする。The present invention was created in view of these points, and the PI
The present invention aims to provide a device in which the contact resistance of the P (JIIJ) electrode in an N-type photodiode is smaller than that of the conventional example.
第１図は本発明実施例断面図である。 FIG. 1 is a sectional view of an embodiment of the present invention.
本発明においては、ＩｎＰ窓層１４を一部除去して、Ｇ
ａｌｎＡｓ層１３を部分的に露出させ、Ａ ｕ／ Ｐ
ｔ／ Ｔ ｉ電極２０によりＰ側コンタクトを形成する
構造となっている。In the present invention, the InP window layer 14 is partially removed and the G
The alnAs layer 13 is partially exposed and A u/P
The structure is such that a P-side contact is formed by a t/Ti electrode 20.
本発明では、ＧａｌｎＡｓ層にＡｕ／ Ｐ ｔ／ Ｔ
ｉ電極によりＰ側コンタクトを形成する。ＧａＩｎＡｓ
層は後述するようにバンドギャップがＩｎＰ層に比べて
約半分であるため、ＩｎＰ層上に形成する場合に比して
順方向立ち上り電圧およびコンタクト抵抗を小さくでき
る。In the present invention, the GalnAs layer has Au/Pt/T
A P-side contact is formed by the i-electrode. GaInAs
As will be described later, the bandgap of the layer is approximately half that of the InP layer, so the forward rising voltage and contact resistance can be reduced compared to when the layer is formed on the InP layer.
以下、図面を参照して本発明の実施例を詳細に説明する
。Embodiments of the present invention will be described in detail below with reference to the drawings.
再び第１図を参照すると、本発明実施例は、Ａｕ／Ｐｔ
／Ｔｉ電極２０のコンタクトのとり方が従来例と異なる
だけで、第４図のＰＩＮホトダイオードと同じ構成のも
のである。第１図のＰＩＮホトダイオードにおいて、電
極２０は露出されたＧａＩｎＡｓ層に接触しているが、
ＧａＩｎＡｓのバンドギャップはＩｎＰのバンドギャッ
プの半分程度と小であり、それだけでもコンタクトがと
り易い。Referring again to FIG. 1, embodiments of the present invention include Au/Pt
The structure is the same as that of the PIN photodiode shown in FIG. 4, except that the way the /Ti electrode 20 is contacted is different from the conventional example. In the PIN photodiode of FIG. 1, the electrode 20 is in contact with the exposed GaInAs layer;
The bandgap of GaInAs is small, about half that of InP, and that alone makes it easy to make contact.
そこで、表面をすべてＧａＩｎＡｓで形成することも考
えられるが、そうするとＳｉＮｘ膜１６を付けることが
ＩｎＰの場合よりも難しくなり、また図示のデバイスで
光２２は表面から入るので、光はＧａＩｎＡｓｆｆｌの
表面の近くで吸収され、光電流として流れないキャリア
がかなり多（発生する問題がある。かくして、表面層は
従来例どおりＩｎＰで構成するのである。Therefore, it is conceivable to form the entire surface with GaInAs, but in that case it would be more difficult to attach the SiNx film 16 than in the case of InP, and since the light 22 enters from the surface in the device shown in the figure, the light will not reach the surface of the GaInAsffl. There is a problem that a considerable number of carriers are absorbed nearby and do not flow as photocurrent.Therefore, the surface layer is made of InP as in the conventional case.
次に第２図を参照して第１図の実施例を形成する工程を
説明する。Next, the process of forming the embodiment of FIG. 1 will be described with reference to FIG.
先ず第２図ｆａｔに示される如く、ｎ” −ＩｎＰ基板
１１上にエピタキシャル成長によって２μｍの膜厚のｎ
−−ＩｎＰ層１２（バッファ層）、膜厚２μｍのｎ −
−ＧａｌｎＡｓ層１３、約０．５μｍの膜厚のｎ −Ｔ
ｎＰ層１４を順次形成する。First, as shown in FIG.
--InP layer 12 (buffer layer), 2 μm thick n −
-GalnAs layer 13, about 0.5 μm thick n-T
The nP layer 14 is sequentially formed.
次に、第２図（ｂ）に示される如（表面に５ｉＮｘｌｌ
ＱＩＧを形成し、ＳｉＮｘ膜１６に窓開けをなし、表面
からＺｎまたはＣｄを拡散して９１層１５を形成する。Next, as shown in Fig. 2(b),
A QIG is formed, a window is made in the SiNx film 16, and Zn or Cd is diffused from the surface to form a 91 layer 15.
このｐ型不純物拡散は、ＰＮ接合面がＧａｌｎＡｓ層１
３中にに形成されるようになす。This p-type impurity diffusion occurs when the PN junction surface is in the GalnAs layer 1.
3. Let it form until it forms.
次いで第２図ｆｃ）に示される如く、化学エツチングで
ｎ −ＩｎＰ層１４の電極形成部分に溝２３をＧａＩｎ
Ａｓ層が露出するまで形成し、溝２３の部分に第１図に
示したＡｕ／ Ｐ ｔ／Ｔｉ電極２０を形成する。Next, as shown in FIG. 2fc), grooves 23 are formed in the electrode forming portion of the n-InP layer 14 by chemical etching.
The As layer is formed until it is exposed, and the Au/Pt/Ti electrode 20 shown in FIG. 1 is formed in the groove 23.
コンタクトを形成するＧａＩｎＡｓ層の表面濃度は、本
発明者の実験によると、５００℃でのＺｎ拡散によると
２Ｘ１０ｃｍ−３となり、濃度の面からの問題はなく、
順方向立ち上り電圧が０．５ Ｖ以下の特性を示すコン
タクトが形成された。According to experiments by the present inventor, the surface concentration of the GaInAs layer forming the contact is 2X10cm-3 due to Zn diffusion at 500°C, and there is no problem from the concentration point of view.
A contact exhibiting a forward rising voltage of 0.5 V or less was formed.
上記の方法に代えて、第２図（ａ）の工程が終った後に
第３図ｆａ）に示す如＜ ＩｎＰ層１４に溝２３を形成
する。Instead of the above method, after the process shown in FIG. 2(a) is completed, grooves 23 are formed in the InP layer 14 as shown in FIG. 3fa).
次いで第３図（ｂｌに示す如（ＳｉＮｘ膜１６を付け、
しかる後にＺｎ拡散でｐ＋層１５を形成する。Next, as shown in FIG.
Thereafter, a p+ layer 15 is formed by Zn diffusion.
かかる方法によると、直接ＧａＩｎＡｓの表面に拡散を
なすので、表面濃度が更に高くなり、より良好なコンタ
クトがとれるようになる。溝２３のところで拡散が深く
ならないかの懸念があったが、本発明者の実験によると
、Ｃｄ＋ Ｚｎの拡散常数はＧａＩｎＡｓではＩｎＰの
１／３程度であるので、図にはやや誇張して溝の下の拡
散部分に段差を付けて示すが、拡散の底はさほど深くな
（、見かけ上はぼ平坦な底が作られた。なお、溝のとこ
ろで拡散が僅かばかり深くなっていても、光吸収につい
てはほとんど問題のないことが実験で確認された。According to this method, since diffusion is performed directly on the surface of GaInAs, the surface concentration becomes higher and better contact can be made. There was a concern that the diffusion would become deep at the groove 23, but according to the inventor's experiments, the diffusion constant of Cd+Zn is about 1/3 of that of InP in GaInAs, so the groove is slightly exaggerated in the figure. Although the diffusion part at the bottom is shown with a step, the bottom of the diffusion is not very deep (an apparently flat bottom was created. Note that even if the diffusion is slightly deeper at the groove, the light Experiments have confirmed that there is almost no problem with absorption.
以上述べてきたように本発明によれば、従来技術を変更
することなく、ただＩｎＰ窓層を工；・チングするだけ
の容易な工程で順方向特性の改良が出来、低コンタクト
抵抗なＰ側電極が形成できる効果がある。As described above, according to the present invention, the forward characteristics can be improved through a simple step of simply etching the InP window layer without changing the conventional technology, and the P side with low contact resistance can be improved. This has the effect of forming electrodes.
第１図は本発明実施例断面図、
第２図（ａ） 、 （ｂ） 、 （Ｃ）は本発明の工程
の断面図、第３図（ａ）、（ｂｌは第２図の工程の変形
例の断面図、第４図は従来例断面図である。
第１図ないし第４図において、
１１はｎ” −ＩｎＰ基板、
１２はｎ−−ＩｎＰ層、
１３はｎ−−ＧａｌｎＡｓ層、
１４はｎ −ＩｎＰ層、
１５はｐ＋層、
１６はＳｉＮｘ膜、
１７はＴｔ膜、
１８はｐｔ膜、
１９はＡｕ膜、
２０はＰ側電極、
２１はＡｕＧｅＮ側電極、
２２は光、
２３は溝である。
代理人 弁理士 久木元 彰
復代理人 弁理士 大 菅 義 之
茅２ＬＴ−ｎＪす４りｊ清にFig. 1 is a cross-sectional view of an embodiment of the present invention, Fig. 2 (a), (b), and (C) are cross-sectional views of the process of the present invention, and Fig. 3 (a) and (bl are cross-sectional views of the process in Fig. 2). 4 is a sectional view of a conventional example. In FIGS. 1 to 4, 11 is an n''-InP substrate, 12 is an n--InP layer, 13 is an n--GalnAs layer, 14 is n-InP layer, 15 is p+ layer, 16 is SiNx film, 17 is Tt film, 18 is PT film, 19 is Au film, 20 is P side electrode, 21 is AuGeN side electrode, 22 is light, 23 is It's a ditch. Agent: Patent attorney Akifuku Kuki Agent: Patent attorney Yoshio Osuga
Claims (1)
ファ層（１２）、ｎ＾−−ＧａＩｎＡｓ光吸収層（１３
）、ｎ＾−ＩｎＰ窓層（１４）が積層され、ｎ−ＩｎＰ
窓層（１４）表面より選択的にＰ形不純物がドープされ
、ｐｎ接合が光吸収層（１３）中に形成されてなるＰＩ
Ｎ型ホトダイオードにおいて、 前記ドーピングが行われたＩｎＰ窓層（１４）の一部が
選択的に除去されて溝（２３）が形成され、光吸収層（
１３）の表面に直接接触するＰ側電極（２０）が形成さ
れてなることを特徴とする半導体受光素子。[Claims] On the n^+-InP substrate (11), an n^--In buffer layer (12), an n^--GaInAs light absorption layer (13)
), n^-InP window layer (14) is laminated, and n-InP
PI in which P-type impurities are selectively doped from the surface of the window layer (14) and a pn junction is formed in the light absorption layer (13).
In the N-type photodiode, a portion of the doped InP window layer (14) is selectively removed to form a groove (23), and a light absorption layer (23) is formed.
13) A semiconductor light-receiving element characterized in that a P-side electrode (20) is formed in direct contact with the surface of the semiconductor light-receiving element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61167825A JPS6325985A (en) | 1986-07-18 | 1986-07-18 | Semiconductor photodetector |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61167825A JPS6325985A (en) | 1986-07-18 | 1986-07-18 | Semiconductor photodetector |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6325985A true JPS6325985A (en) | 1988-02-03 |
Family
ID=15856792
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61167825A Pending JPS6325985A (en) | 1986-07-18 | 1986-07-18 | Semiconductor photodetector |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6325985A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0258878A (en) * | 1988-08-25 | 1990-02-28 | Nec Corp | Semiconductor photo detector array |
| EP0399361A2 (en) * | 1989-05-24 | 1990-11-28 | Siemens Aktiengesellschaft | Opto-electronic device with optical absorber surface in a III-V material |
-
1986
- 1986-07-18 JP JP61167825A patent/JPS6325985A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0258878A (en) * | 1988-08-25 | 1990-02-28 | Nec Corp | Semiconductor photo detector array |
| EP0399361A2 (en) * | 1989-05-24 | 1990-11-28 | Siemens Aktiengesellschaft | Opto-electronic device with optical absorber surface in a III-V material |
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