JPS63259700A - Recording control circuit for voice recorder/reproducer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] (a) Industrial application field The present invention converts a recording signal obtained from a microphone into a digital signal and stores it in a semiconductor memory circuit, and also stores it in the semiconductor memory circuit during playback operation. The present invention relates to an audio recording and reproducing device that reads out a signal, converts it into an analog signal, and emits the sound through a speaker.

(B) Conventional Technology Cassette-type table recorders that use a magnetic tape called a cassette tape have become popular as devices for recording and playing back audio. Devices such as cassette tape recorders that use magnetic tape as a means of recording audio signals have the advantage of being able to perform long recording operations, but they are difficult to miniaturize. Since it requires a mechanism to drive the magnetic tape, there is a problem in that the failure rate is high. As an improved device in this respect, the audio signal is converted into a digital signal and stored in a semiconductor memory, and during playback operation, the signal stored in the semiconductor memory is read out, converted into an analog signal, and then emitted through a speaker. A technology has been developed to do this, and examples of such technology include, for example,
There is one disclosed in Japanese Patent No. 2800.

(c) Problems to be Solved by the Invention The technology disclosed in the above-mentioned publication uses a semiconductor memory as a means for recording audio signals, which eliminates the need for a drive mechanism such as a tape recorder, and the device It has the advantage of being smaller and lowering the failure rate. However, such a device has the problem of poor operability since it is necessary to perform a recording operation after specifying an address. The present invention aims to provide an audio recording/playback device that is improved in this respect.

(d) Means for solving the problem The recording control circuit of the present invention has an ADPC control circuit during recording and playback operations.
An ADPCM analysis and synthesis circuit that performs speech analysis and speech synthesis using the M method, a semiconductor memory circuit that is removably attached to the main body, and writing of digital signals output from the ADPCM analysis and synthesis circuit into the semiconductor memory circuit. an address control circuit that controls operations, readout operations of signals stored in the semiconductor memory circuit, and write operations of index data to the semiconductor memory circuit;
It is composed of a control circuit that controls the operations of a CM analysis and synthesis circuit, a semiconductor memory circuit, and an address control circuit.

(*) Effect The present invention writes the recording end position, which is the use position of the memory, into the semiconductor memory circuit as index data when the recording operation is being performed, and also after the semiconductor memory circuit is attached to the main body or after power is supplied. When a recording operation is performed without performing any other operation, the recording operation can be started from the recording end position.

(F) Embodiment The circuit shown in FIG. 1 is an embodiment of the present invention, FIG. 2 is a diagram for explaining the invention in detail, and FIG. 3 is an embodiment of a display. In the circuit shown in Fig. 1, (1) is a microphone that is in an operating state during recording operation and converts an acoustic signal into an electrical signal; (2) is a microphone (1) that converts an acoustic signal into an electrical signal;
) is input with a recording signal converted into an electrical signal and amplifies the signal; (3) is a recording amplifier circuit into which the recording signal amplified by the recording amplifier circuit (2) is input and which also amplifies the signal; This is a low-pass filter that blocks high-frequency signals. (4) is A- which converts the analog signal passed through the low-pass filter (3) into a digital signal.
The D converter (5) is an ADPCM that performs digital processing using a method called adaptive differential pulse code modulation.
The analysis and synthesis circuit (6) is the ADPCM analysis and synthesis circuit (
A D-A converter (7) converts the digital signal processed by the D-A converter (5) into an analog signal;
) into which the reproduced signal converted into an analog signal is input, and a low-pass filter (8) which cuts off unnecessary high-frequency signals; (8) receives the reproduced signal that has passed through the low-pass filter (7), and amplifies the signal. The reproducing amplifier circuit (9) is a speaker to which the signal amplified by the reproducing amplifier circuit (8) is applied and emits the signal. (10) is the ADPCM analysis and synthesis circuit (
5) a control unit that controls the voice analysis operation and voice synthesis operation; (11) is an external circuit that will be described later and the control unit (10);
and a data I10 buffer circuit that controls input/output operations of signals between the ADPCM analysis and synthesis circuit (5). In such a circuit, an A-D converter (4), an ADPCM analysis and synthesis circuit (5), a D-A converter (6), and a control section (10).
) and the data I10 buffer circuit (11) constitute an audio processing circuit (Tsubo), but such a circuit may be, for example, LSI'MSM625B manufactured by Oki Electric Industry Co., Ltd., and its details are omitted. do. (13) is a data 110 buffer circuit (
11) RAM, which is a semiconductor memory that stores the digital signals output from the RAM and writes the memory consumption time as index data; (14) is the RAM;
This is an address control circuit that controls the write operation, read operation, and index data write operation of signals of M(13>), and is incorporated in a card-type container together with the RAM (13).The container ( (13) is removable from the main body of the audio recording/playback device, and has a backup battery (not shown) built into it that maintains the memory operation of the RAM (13). 16)
is a control circuit that controls the operations of the audio processing circuit, RAM (13), address control circuit (14), and the like. Reference numeral (17) is a recording operation switch that is pressed and closed by the recording operation, and when the recording operation switch (17) is closed, the audio signal is stored in the RAM (13). (18) is a regeneration operation switch that is pressed and closed by the regeneration operation, and when the regeneration operation switch (18) is closed, the signal stored in the RAM (13) is read and reproduced. It will be done. (19)
, (20) and (21) are a fast-forward operation switch, a rewind operation switch, and a stop operation switch that can be pressed and closed during fast-forward operation, rewind operation, and stop operation. (22) is a clock circuit, (23) is the clock circuit (22)
The clock display signal outputted from the control circuit (16)
a display selection circuit that selects a display signal output from the
(24) is a drive circuit that drives the display device (25) based on the display signal selected by the display selection circuit (23). (26) is a display selection switch that selectively changes the content displayed on the display (25), and each time the switch is fully pressed, the content that can be displayed on the display (25) is changed from clock display to counter display to remaining content. It has the effect of switching in the order of amount time display → consumption time display → clock display. (27) is a correction operation switch that is operated when correcting the time of the clock circuit (22), and (28) is a reset switch that resets the count value to zero when pressed and closed while the counter display is being performed. This is a control switch for use. (29) is a battery built into the main body of the audio recording/playback device, and (30) is a power switch, which supplies power from the battery (29) to the control circuit (16) etc. when in the closed state. It has the effect of In addition, the clock circuit (22), the clock circuit (
22) The circuit for displaying the time on the display (25) using a signal that can be outputted from the power switch (30)
) is configured so that power is supplied from the battery (29) regardless of the opening/closing operation of the battery (29).

The present invention is constructed as described above, and its operation will be explained next. If the sampling frequency in the audio processing circuit (equipment) is 8 KHz and the number of quantization bits is 4, the bit rate will be 32 bits/second, and if the capacity of the RAM (13) is 4 Mbits, it will be stored for about 128 seconds. I can do it. In the present invention, the speech analysis and synthesis processing by the ADPCM analysis and synthesis circuit (5) and the write operation to the RAM (13) accompanying the processing are performed in phrases of 250 milliseconds. In other words, the audio processing circuit (婬)
The analysis and synthesis operation by the ADPCM analysis and synthesis circuit (5) is started by a start signal output from the control unit (10) incorporated in the control unit (10), and after 250 milliseconds, the control unit (
10) The speech analysis and synthesis operation is stopped by the stop signal outputted from. When a signal is written to the RAM (13), that is, during a recording operation, the signal that has been analyzed and processed by the ADPCM analysis and synthesis circuit (5) for the aforementioned 250 milliseconds is sent to the data I10 buffer circuit (11) and then R
AM (13) and address control circuit (1
By the control operation 4), the data is written into the RAM (13) while the address is specified. In addition, during the readout operation of the signal from the RAM (13), that is, during the reproduction operation, the above-mentioned 2
The signal synthesized by the ADPCM analysis/synthesis circuit (5) for 50 milliseconds is input to the DA converter (6) and converted into an analog signal. In this way, the RAM by the audio processing circuit (12) and address control circuit (14)
The control operation (13) is performed, and next, each operation in this embodiment will be explained with reference to FIG.

When the user performs a recording operation after closing the power switch (29), power is supplied to the recording amplifier circuit (2), and the recording operation switch (17) is pressed and closed, and the control circuit (16) A control operation for recording is performed.The recording signal converted into an electrical signal by the microphone (1) is input to the recording amplifier circuit (2), where it is amplified and then passed through the low-pass filter (3) to the audio processing circuit (2). The recording signal input to the audio processing circuit (12) is converted into a digital signal by the A-D converter (4), and the analysis operation by the ADPCM analysis and synthesis circuit (5) is performed as described above. This is done for 250 milliseconds each.

Further, the signal analyzed and processed by the ADPCM analysis and synthesis circuit (5) is outputted to the RAM (13) through the data I10 buffer circuit (11) and is sent to the address control circuit (
14) is written into the RAM (13). Then, while the recording operation is being performed, the above-mentioned ADP
CM analysis and synthesis circuit・Analysis operation by (5) and RAM (
The write operation to RAM (13) will be repeated until a stop operation is performed or until the capacity of RAM (13) is exhausted. Figure 2 (a) explains such a recording operation, in which a signal that has been subjected to audio analysis processing using the ADPCM method is divided into phrases (il (b), (c), etc.). The analysis operation by the ADPCM analysis and synthesis circuit (5) starts at point (A>) of each phrase, and stops at point (B). B) The interval is 250 milliseconds.The recording operation is performed in this way, but each time the recording operation of each phrase is performed, the memory usage position is set in a part of the index memory provided in the RAM (13). The index data is written as index data.Even if the container (15) is removed from the main body of the audio recording/playback device, the index data is retained together with the audio signal by the backup battery.For example, as shown in FIG. In a), when the phrases (a), (b) and (8) are recorded, if the stop operation switch (21) is pressed and closed to cancel the recording operation, the phrases ((), (b) and (h) are recorded. ) is written to a part of the index memory.In this state, the power switch (
30), the power supply to the control circuit (16) etc. is cut off, but the signals and data written in the RAM (13) are retained by the backup battery. When the power switch (30) is closed after the RAM (13) in which the audio signal has been recorded in this manner is installed in the main body, power is supplied to the control circuit (16) etc. as described above, and the control circuit ( 16), the index data written in the RAM<13) is read out. If a recording operation is performed in such a state, the above-mentioned recording operation will be started, but the writing operation of the audio signal to the RAM (13) will start from the phrase (Ni) which is the next phrase after the above-mentioned recording end position. ). That is, if a recording operation is performed after closing the power switch (30), the writing operation of the audio signal will be performed following the part of the memory that has been written up to that point.

The recording operation in this embodiment is performed as described above, but the reproduction operation will now be explained. When the power switch (30) is closed after installing the RAM (13), the control circuit (16)
), etc., and the index data written in the RAM (13) is read out by the control circuit (16). For example, by a recording operation, as shown in FIG.
When the RAM (13) in which audio signals from phrases (a) to (*) shown in the figure are written is installed, the control circuit (16)
), it is recognized that the audio signal has been written up to the position of the phrase (*).

In such a state, when a playback operation is performed, power is supplied to the playback amplifier circuit (8) and the playback operation switch (
18), the press-closed control circuit (16) performs a control operation for regeneration. However, such a playback operation can be started from the point after the phrase (*) mentioned above, but since no audio signal is written at that position, the playback operation must be performed after performing the rewind operation described below. After rewinding to the position of phrase (A), the playback operation is performed. The signals stored in the RAM (13) are read out by the control operation of the address control circuit (14) and are input to the ADPCM analysis and synthesis circuit (5) through the data I10 buffer circuit (11). The digital signal input to the ADPCM analysis and synthesis circuit (5) is converted into two signals by the ADPCM analysis and synthesis circuit (5).
After being synthesized for 50 milliseconds each, the D-A converter (6)
is applied to the signal and converted into an analog signal. The signal converted into an analog signal by the DA converter (6) is
The reproduction amplifier circuit (8) is passed through the low-pass filter (7).
), the sound is amplified and then emitted by the speaker (9). While the reproduction operation is being performed, the reading operation from the RAM (13) and the synthesis operation by the ADPCM analysis and synthesis circuit (5) are repeated until a stop operation is performed or the capacity of the RAM (13) is exhausted. It turns out. FIG. 2(b) shows such a playback operation, in which the A
A speech synthesis processing operation is performed by the DPCM analysis and synthesis circuit (5), and a reproduction operation is performed. (A) of each phrase
The synthesis operation by the ADPCM analysis and synthesis circuit (5) starts at point (B), and the synthesis operation stops at point (B).
-(B) is 250 milliseconds.

The recording and reproducing operations are performed as described above, but the operations when fast forwarding and rewinding operations are performed will now be described. When the fast-forward operation is performed, the fast-forward operation switch (19) is closed and power is supplied to the reproduction amplifier circuit (8). When the fast-forward operation switch (19) is fully closed, the control circuit (16) performs a control operation to read signals from the RAM (13) and ADPCM.
The synthesis operation by the analysis and synthesis circuit (5) is performed as shown in FIG. 2(c). As is clear from the figure, the beginning parts (A) to (C) of each phrase that have been analyzed during the recording operation.
) The readout and synthesis processing operations are performed only during the period ( ) and the sound is emitted from the speaker (9). If the interval between (A) and <C> is set to 174, or 62.5 milliseconds between each phrase (A) and (B), it will be played back at four times the speed as compared to the playback operation described above. However, unlike a tape recorder, the frequency of the signal emitted from the speaker (9) does not become high, so the reproduced signal can be heard, albeit fragmentarily. The operation when performing the fast forward operation is performed in this way, but the operation when the rewind operation is performed will be explained next. When the rewinding operation is performed, the rewinding operation switch (20) is closed and power is supplied to the reproducing amplifier circuit (8). When the rewind operation switch (20) is closed, the control circuit (1
According to the control operation by 6), the reading operation of the signal from the RAM (13) and the synthesis operation by the ADPCM analysis and synthesis circuit (5>) are performed as shown in FIG. 2(d).As is clear from the figure, the recording operation The readout and synthesis processing operation is performed only between the beginning parts (A) to (C) of each phrase that has been subjected to time analysis processing, and the sound is emitted from the speaker (9), but the order of the phrases in which the readout operation is performed is is in the opposite direction to the direction during recording operation. Thus (A) ~ (
C) If the interval between each phrase (A) and (B) is set to 174, or 62.5 milliseconds, the rewinding speed will be four times that of the playback operation described above.
Unlike a tape recorder, not only does the frequency of the signal emitted from the speaker (9) not become high, but the signal is emitted in the form of words, so the reproduced signal can be heard, albeit in fragments. By performing the aforementioned fast-forwarding and rewinding operations, it is possible to find the playback operation position and recording operation position.

In addition, when the fast-forwarding operation state and the rewinding operation state are in place, by pressing and closing the stop operation switch (21), it is possible to switch to the stop state.

Each operation in this embodiment is performed as described above, and next, the display operation will be explained with reference to FIG. 3. FIG. 3 shows an example in which a liquid crystal is used as the display (25). First, the clock display operation will be explained. Such display operation is
This is done by operating the display selection switch (26), and when the clock is displayed, the display section (31) provided corresponding to the position where "clock" is printed becomes active.

When the clock display becomes operational, the AM display section (32),
Afternoon display section (33), first display section (34) that displays the time
, a second display section (35) that displays minutes, and a colon section (36) that blinks every second are activated to display the time. In this state, a signal from the clock circuit (22) is input to the drive circuit (24) through the display selection circuit (23), and the time is displayed on the display (25) by the drive operation of the drive circuit (24). Can be displayed. In addition, in this state, the time can be corrected by operating the correction operation switch (27). Although the display operation as a clock is performed in this way, other display operations will be explained next.

When a recording operation and a playback operation are performed, the above-mentioned recording operation and playback operation are performed, but in such a state, the recording display section (37) and the playback display section (38) are in the operating state and each operation is performed. display that the When the display selection switch (26) is operated to display the counter during such recording and playback operation, the display section (39) provided corresponding to the position where the counter is printed will be displayed. becomes operational. When the counter display operation is performed, the number display elements forming the first display section (34) and the second display section (35) display the count value. When the counter display is in the operating state, the count signal output from the control circuit (16) is input to the drive circuit (24) through the display selection circuit (23), and the count value is changed by the drive operation by the drive circuit (24). is displayed on the display (25). The counting signal outputted from the control circuit (16) is performed based on the address signal controlled during the self-loading operation to the RAM (13) and the read operation from the RAM (13). For example, during the recording operation, the count value is increased by one based on the address signal controlled by the address control circuit (14) during the writing operation of the phrase (RI) and the writing operation of the phrase (*), and the display (25) The count value displayed on the display (25) will change every second.In other words, if the count signal output from the control circuit (16) is set to change every second, the count value displayed on the display (25) will change every second. The count value displayed in will display the recording time.In addition, during playback operation, the same goes for reading operation of phrase (A) and phrase (*).
When the count value is increased by one based on the address signal controlled by the address control circuit (14) during the read operation, the count value displayed on the display (25) will change every second. In other words, if the count signal output from the control circuit (16) is set to change every second, the count value displayed on the display (25) will indicate the playback time. The counter display operation is performed during the recording operation and the playback operation as shown in FIG. The operation shown in FIG.
If the count value is increased by one based on the address signal controlled by 4), the count value displayed on the display (25) will change every 174 seconds.

In other words, as mentioned above, the fast-forward operation is played back at four times the speed compared to the recording and playback operations, but the display (2
Since the count value displayed in 5) also increases at four times the speed, a counter display operation can be performed in a fast forward operation state. Further, the counter display operation during the rewinding operation is performed in the same manner as during the fast forwarding operation, although the count value decreases, so a description thereof will be omitted.

The display operation as a counter is performed as described above, but next, the display operation of the remaining amount time will be explained. When the container (long) is attached to the main body of the audio recording and playback device, if you operate the display selection switch (26) to display the remaining amount, the remaining amount and the printed position will be displayed. Display provided! (4O) becomes operational. In such a state, the display selection circuit (2) is switched from the control circuit (16).
The signal output to 3) is output based on the signal obtained from the RAM (13). That is, the remaining time is calculated by the control circuit (16) from a signal indicating the memory usage position, which is index data written in the RAM (13), and the capacity of the memory, and the signal representing the remaining time is selected for display. It is output to the circuit (23). The signal representing the remaining amount of time is sent to the drive circuit [2] through the display selection circuit (23).
4), the remaining amount of time is displayed on the display (25) by the drive operation by the drive circuit (24).

In this case, the minutes are displayed on the first display section (34) constituting the display device (25), and the second display section (34)
5), the seconds can be displayed completely, but at this time, the minute display section (41) and second display section (42> provided at the lower right side of the first display section (34) and second display section (35), respectively) are displayed. When it is in operation, the minutes and seconds are displayed on the first display section (34
) and the second display section (35) to make the user aware of what is being done. In addition, when recording, playback, fast forwarding, or rewinding operations are performed in such a state, the second display section (35) and the first display section (35) will be displayed in response to the operation.
4) changes, and R A M (1
3) Remaining time is displayed.

The operation of displaying the remaining amount time is performed as described above, but next, the operation of displaying the consumed time will be explained.

When the container (15) is attached to the main body of the audio recording and playback device, if the display selection switch (26) is operated to display the consumption time, a display will be displayed corresponding to the consumption amount and the printed position. The displayed display section (43) becomes operational. In such a state, the signal output from the control circuit (16) to the display selection circuit (23) is RAM (
13) is output based on the signal obtained from. That is, R.A.
The control circuit (16) reads the index data written in the M (13), which is a signal indicating the memory usage position, and based on the read signal, the display selection circuit (23) generates a signal representing the consumed time. ) can be output. A signal representing the time consumed is applied to the drive circuit (24) through the display selection circuit (23), and the drive circuit (24)
The consumed time is displayed on the display (25) by the driving operation. In this case as well, the consumed time is displayed by the operation of the first display section (34), the second display section (35), the minute display section (41), and the second display section (42) that constitute the display device (25). displayed on the display (25). Furthermore, when recording, playback, fast-forwarding, or rewinding operations are performed in such a display state, the values on the second display section (35) and the first display section (34) change in accordance with the operations. RA in state
The time consumed by M(13) is displayed.

As described above, since the remaining time and consumed time of the RAM (13) can be displayed on the display (25), recording and playback operations can be performed while checking the number that can be displayed on the display (25). This can prevent mistakes in recording.

Note that the recording and playback time can be increased by increasing the capacity of RAM (13) or by setting the sampling frequency low. In addition, the analysis and synthesis time during recording and playback operations was set to 250 milliseconds, and the synthesis time during fast forward and rewind operations was set to 62.5 milliseconds, but the times are not limited. Although the value is set to change every second, it is possible to change the value in various ways, such as changing every 0.5 seconds. In addition, a display (25
) is provided with a display section to display that the recording operation and playback operation are in progress, but it is also possible to provide a display section or the like to indicate that fast-forwarding or rewinding operation is being performed.

(g) Effects of the Invention The recording control circuit of the present invention converts a recording signal obtained from a microphone into a digital signal, stores it in a semiconductor memory circuit that is detachable from the main body, and also stores it in a semiconductor memory circuit that is detachable from the main body. In an audio recording/playback device configured to read out a stored signal, convert it into an analog signal, and emit the sound through a speaker, when recording is being performed, the recording end position, which is the memory usage position, is detected by a semiconductor device. The recording operation is started from the end position when the recording operation is performed without performing any other operation after writing the index data into the memory circuit and after the semiconductor memory circuit is attached to the main body or after power supply is supplied. The present invention has a very large effect since it is possible to use the memory capacity efficiently and has excellent operability.

[Brief explanation of drawings]

The circuit shown in FIG. 1 is an embodiment of the present invention, FIG. 2 is a diagram for explaining the invention in detail, and FIG. 3 is an embodiment of a display. Explanation of main drawing numbers (1)... Microphone, (2)... Recording amplifier circuit, (5)... ADPCM analysis and synthesis circuit, (8)
... reproduction amplifier circuit, (9) ... speaker,
(L8)...Audio processing circuit, (13>...RAM
, (14)...address control circuit, (16)...
・Control circuit, (22>...clock circuit, (23)・
...Display selection circuit, (24)...Drive circuit, (2
5)...Indicator, (29)...Battery, (30)
...Power switch.

Claims (1)

[Claims] (1) Convert the recording signal obtained from the microphone into a digital signal and store it in a semiconductor memory circuit that is removably attached to the main body. During playback operation, the signal stored in the semiconductor memory circuit is read out and then converted into an analog signal. In an audio recording/playback device configured to convert the ADPCM into sound and emit the sound from a speaker, during recording and playback operations, the ADPCM
an ADPCM analysis and synthesis circuit that performs speech analysis and speech synthesis according to a method, a write operation of a digital signal output from the ADPCM analysis and synthesis circuit to the semiconductor memory circuit, and a read operation of the signal stored in the semiconductor memory circuit. and an address control circuit that controls the writing operation of index data to the semiconductor memory circuit, and the ADPCM according to the recording operation, playback operation, and high-speed feed operation.
It consists of a control circuit that controls the operation of an analysis/synthesis circuit, a semiconductor memory circuit, and an address control circuit, and when a recording operation is performed, it writes the recording end position of the semiconductor memory circuit as index data, and also writes the recording end position of the semiconductor memory circuit as index data. A voice recording and playback device characterized in that when a recording operation is performed without performing any other operation after being attached to the device or after power is supplied, the recording operation is started from the recording end position based on the index data. Recording control circuit.