JPH0670756B2 - Recording control circuit of voice recording / playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention converts a recording signal obtained from a microphone into a digital signal and stores the digital signal in a semiconductor memory circuit, and the semiconductor memory circuit during a reproducing operation. The present invention relates to a voice recording / reproducing device in which a signal is read out, converted into an analog signal and then emitted from a speaker.

(B) Conventional technology As a device for recording and reproducing voice, a cassette type tape recorder using a magnetic tape called a cassette tape has become widespread. An apparatus using a magnetic tape as a means for recording an audio signal like such a cassette type tape recorder has an advantage that it can perform a recording operation for a long time, but it is difficult to downsize the apparatus. There is a problem that the failure rate is high because a mechanism for driving the magnetic tape to run is required. As a device improved in this respect, an audio signal is converted into a digital signal and stored in a semiconductor memory, and at the time of a reproducing operation, a signal stored in the semiconductor memory is read out and then converted into an analog signal and sound is emitted from a speaker. The technology developed in this way has been developed.
There is one disclosed in the publication.

(C) Problems to be Solved by the Invention In the technology disclosed in the above-mentioned publication, since a semiconductor memory is used as a means for recording an audio signal, a drive mechanism such as a tape recorder becomes unnecessary, and It has the advantage that it can be downsized and the failure rate can be reduced. However, such a device has a problem of poor operability because it is necessary to perform a recording operation after designating an address. The present invention intends to provide a voice recording / reproducing apparatus in which such a point is improved.

(D) Means for Solving the Problems The recording control circuit of the present invention is detachable from the main body and the ADPCM analysis / synthesis circuit that performs voice analysis and voice synthesis in the ADPCM system during recording and playback operations. Semiconductor memory circuit, write operation of the digital signal output from the ADPCM analysis / synthesis circuit to the semiconductor memory circuit, read operation of a signal stored in the semiconductor memory circuit, and writing of index data to the semiconductor memory circuit It is composed of an address control circuit for controlling the operation and a control circuit for controlling the operation of the ADPCM analysis / synthesis circuit, the semiconductor memory circuit and the address control circuit according to a recording operation, a reproducing operation and a high speed feed operation.

(E) Operation The present invention writes the recording end position, which is the use position of the memory when the recording operation is performed, into the semiconductor memory circuit as index data, and after mounting the semiconductor memory circuit on the main body or supplying power. When a recording operation is performed later without performing another operation, the recording operation is started from the recording end position.

(F) Embodiment The circuit shown in FIG. 1 is an embodiment of the present invention, FIG. 2 is a diagram for explaining the operation of the present invention, and FIG. 3 is an embodiment of a display. In the circuit shown in FIG. 1, (1) is a microphone that is in an operating state during a recording operation and that converts an acoustic signal into an electric signal, and (2) is a recording signal that is converted into an electric signal by the microphone (1). A recording amplifying circuit for inputting and amplifying the signal, and (3) is a low-pass filter for intercepting unnecessary high frequency signals while receiving the recording signal amplified by the recording amplifying circuit (2). (4) is an AD converter for converting an analog signal passed through the low pass filter (3) into a digital signal, and (5) is an ADPCM for digital processing by a method called ADPCM, that is, adaptive differential pulse code modulation.
Analysis and synthesis circuit, (6) is the ADPCM analysis and synthesis circuit (5)
A DA converter for converting the digital signal processed by the above into an analog signal, and (7) receives the reproduction signal converted into the analog signal by the DA converter (6) and is an unnecessary high frequency signal Low-pass filter to cut off
(8) is a reproduction amplification circuit for inputting the reproduction signal that has passed through the low-pass filter (7) and amplifies the signal, and (9) is applied with the signal amplified by the reproduction amplification circuit (8). And a speaker that emits the signal. (10) is a control unit for controlling the voice analysis operation and voice synthesis operation of the ADPCM analysis / synthesis circuit (5), and (11) is an external circuit described later and the control unit (10) and ADPCM analysis / synthesis circuit (5). It is a data I / O buffer circuit that controls the input / output operation of signals between and. In such a circuit, A
-D converter (4), ADPCM analysis and synthesis circuit (5), DA
The converter (6), the control unit (10) and the data I / O buffer circuit (11) constitute an audio processing circuit ( 12 ). Such a circuit is, for example, an LSI "MSM6258" manufactured by Oki Electric Industry Co., Ltd. "
Etc. may be used and the details thereof are omitted. RAM (13) is a semiconductor memory that stores the digital signal output from the data I / O buffer circuit (11) that constitutes the audio processing circuit ( 12 ) and that has the memory consumption time written as index data. (14) is the RAM (13)
Is an address control circuit for controlling the signal writing operation, the reading operation, and the index data writing operation, and is incorporated in the card type container ( 15 ) together with the RAM (13). The container ( 15 ) is attachable to and detachable from the main body of the audio recording / playback apparatus, and the RAM (1
A backup battery (not shown) that holds the memory operation of 3) is incorporated. (16) is a control circuit for controlling the operations of the voice processing circuit ( 12 ), the RAM (13), the address control circuit (14), etc. (17) is a recording operation switch which is pressed and closed by a recording operation. When the recording operation switch (17) is closed, the operation of storing the audio signal in the RAM (13) is performed. (18) is a reproduction operation switch which is pressed and closed by a reproduction operation, and when the reproduction operation switch (18) is closed, the RAM (13)
The read / write operation of the signal stored in is performed.
(19), (20) and (21) are operation switches for fast-forwarding which are pressed and closed at the time of fast-forwarding operation, rewinding operation and stop operation,
It is an operation switch for rewinding and an operation switch for stop.
(22) is a clock circuit, (23) is a display selection circuit for selecting a clock display signal output from the clock circuit (22) and a display signal output from the control circuit (16), (24) Is a drive circuit for driving the display (25) based on the display signal selected by the display selection circuit (23). (26) is a display selection switch for selectively switching the content displayed on the display (25), and the content displayed on the display (25) is displayed every time the switch is closed by a clock display → a counter display. →
It has the function of switching the display of remaining time → consumption time display → clock display. (27) is a correction operation switch that is operated when the time of the clock circuit (22) is adjusted, and (28) is a reset that resets the count value to zero when the counter display is pressed and closed. Operation switch. (29) is a battery incorporated in the body of the audio recording / reproducing device, (30) is a power switch, and supplies power from the battery (29) to the control circuit (16) and the like when in the closed state. Has the effect of Also a clock circuit (22),
A display (2 with a signal output from the clock circuit (22)
The circuit for displaying the time on 5) is configured to be supplied with power from the battery (29) regardless of the opening / closing operation of the power switch (30).

The present invention is configured as described above, and the operation will be described below. If the sampling frequency in the audio processing circuit ( 12 ) is 8 KHz and the number of quantization bits is 4, the bit rate will be 32 Kbits / sec. If the capacity of the RAM (13) is 4 Mbits, store it for about 128 seconds. Can be done. In the present invention, the voice analysis / synthesis processing by the ADPCM analysis / synthesis circuit (5) and the writing operation to the RAM (13) associated with the processing are divided into phrases every 250 milliseconds. That is, the analysis / synthesis operation by the ADPCM analysis / synthesis circuit (5) is started by the start signal output from the control unit (10) incorporated in the audio processing circuit ( 12 ) and
After a millisecond, the voice analysis / synthesis operation is stopped by the stop signal output from the control unit (10). And RAM (13)
When writing a signal to, that is, during a recording operation,
The signal analyzed and processed by the ADPCM analysis / synthesis circuit (5) for 250 milliseconds passes through the data I / O buffer circuit (11) to R.
The data is output to the AM (13) and written into the RAM (13) while the address is specified by the control operation of the address control circuit (14). In addition, during the reading operation of the signal from the RAM (13), that is, during the reproducing operation, the signal processed by the ADPCM analysis / synthesis circuit (5) for 250 milliseconds is input to the DA converter (6). Converted into an analog signal. The control operation of the RAM (13) by the voice processing circuit ( 12 ) and the address control circuit (14) is performed as described above. Next, each operation in this embodiment will be described with reference to FIG. When the user performs a recording operation after closing the power switch (29), power is supplied to the recording amplification circuit (2) and the recording operation switch (17) is pressed and closed, and the control circuit (16) A control operation for recording is performed. The recording signal converted into an electric signal by the microphone (1) is input to the recording amplification circuit (2) and amplified, and then input to the audio processing circuit ( 12 ) through the low pass filter (3). The recording signal input to the audio processing circuit ( 12 ) is converted into a digital signal by the AD converter (4) and the analysis operation by the ADPCM analysis / synthesis circuit (5) is performed for 250 milliseconds each. Done. The signal analyzed and processed by the ADPCM analysis / synthesis circuit (5) is a data I / O buffer circuit (1
It is output to the RAM (13) through the address control circuit (1
It is written to RAM (13) by the control operation of 4). Then, while the recording operation is performed, the analysis operation by the ADPCM analysis / synthesis circuit (5) and the write operation to the RAM (13) described above are repeated until a stop operation is performed or the capacity of the RAM (13) is exhausted. Will be done. FIG. 2 (a) is for explaining such a recording operation.
The signal that has undergone speech analysis processing by the method is a phrase (a),
The data is written into the RAM (13), separated by (b), (c). The analysis operation by the ADPCM analysis / synthesis circuit (5) is started at point (A) of each phrase, and the analysis operation is stopped at point (B), but the interval between (A) and (B) is 250 milliseconds. Although the recording operation is performed in this manner, the memory use position is written as index data in the index memory section provided in the RAM (13) every time the recording operation of each phrase is performed. Then, even if the container ( 15 ) is detached from the main body of the audio recording / reproducing apparatus, such index data is held together with the audio signal by the backup battery. For example, FIG. 2 (a)
When the phrases (a), (b) and (c) are recorded, the stop operation switch (21) is pressed and closed to cancel the recording operation, and the phrases (a), (b) and (c) are recorded.
The data indicating the position where is written is written in the index memory unit. In such a state, when the power switch (30) is opened, the power supply to the control circuit (16) is cut off, but the signals and data written in the RAM (13) are retained by the backup battery. . When the power switch (30) is closed after the RAM (13) in which the voice signal is recorded in this manner is attached to the main body, power is supplied to the control circuit (16) and the control circuit (16) as described above. The index data written in the RAM (13) is read by the 16). Then, when a recording operation is performed in such a state, the recording operation described above is started, but the RAM (1
The writing operation of the audio signal to 3) is performed from the phrase (d) which is the next phrase after the recording end position described above. That is, if the recording operation is performed after the power switch (30) is closed, the writing operation of the audio signal is performed following the memory section that has been written.

The recording operation in this embodiment is performed as described above, and the reproducing operation will be described next. When the power switch (30) is closed after mounting the RAM (13), power is supplied to the control circuit (16) and the RAM (1
The index data written in 3) is read. For example, a RAM (1) in which voice signals are written from phrases (a) to (e) shown in FIG.
When wearing 3), the control circuit (16) recognizes that the voice signal has been written up to the position of the phrase (e). In such a state, when a reproducing operation is performed, power is supplied to the reproducing amplifier circuit (8) and the reproducing operation switch (18) is pressed and closed to perform a control operation for reproduction by the control circuit (16). . However, such a reproducing operation is started after the above-mentioned phrase (e), but since no audio signal is written at that position, the reproducing operation is performed after the rewinding operation which will be described later. For example, after rewinding to the position of the phrase (a), the reproducing operation is performed. The signal stored in the RAM (13) is read by the control operation of the address control circuit (14) and is input to the ADPCM analysis / synthesis circuit (5) through the data I / O buffer circuit (11). The digital signal input to the ADPCM analysis / synthesis circuit (5) is the AD signal.
The PCM analysis / synthesis circuit (5) synthesizes each 250 msec, and then it is applied to the DA converter (6) to be converted into an analog signal. The signal converted into the analog signal by the DA converter (6) is input to the reproduction amplifier circuit (8) through the low-pass filter (7), amplified, and then emitted by the speaker (9). Then, while the reproducing operation is being performed, the reading operation from the RAM (13) and the synthesizing operation by the ADPCM analysis / synthesizing circuit (5) are repeatedly performed until a stop operation is performed or the capacity of the RAM (13) is exhausted. It will be. FIG. 2 (b) shows such a reproducing operation, and the phrases (a), (b), and
According to (C) ..., the voice synthesis processing operation is performed by the ADPCM analysis / synthesis circuit (5) and the reproduction operation is performed. The synthesizing operation by the ADPCM analysis / synthesizing circuit (5) is started at the point (A) of each phrase, and the synthesizing operation is stopped at the point (B), but the interval between (A) and (B) is 250 milliseconds.

The recording operation and the reproducing operation are performed as described above. Next, the operation when the fast-forward operation and the rewind operation are performed will be described. When the fast-forward operation is performed, the fast-forward operation switch (19) is closed and power is supplied to the reproducing amplifier circuit (8). When the fast-forwarding operation switch (19) is closed, the RAM (1
The reading operation of the signal from 3) and the synthesizing operation by the ADPCM analysis / synthesizing circuit (5) are performed as shown in FIG. 2 (c). As is apparent from the figure, the reading and synthesizing operation is performed only between the beginning portions (A) to (C) in each phrase analyzed during the recording operation, and the sound is emitted from the speaker (9). If such phrases (A) to (C) are set to 1/4 of each phrase, that is, (A) to (B), that is, 62.5 msec, the phrase is reproduced at a speed four times higher than that at the time of the reproducing operation. However, unlike the tape recorder, since the frequency of the signal emitted from the speaker (9) does not increase, the reproduced signal can be heard although it is fragmentary. Although the operation is performed when the fast-forward operation is performed as described above, the operation when the rewind operation is performed will be described next. When the rewinding operation is performed, the rewinding operation switch (20) is closed and power is supplied to the reproducing amplifier circuit (8). When the rewinding operation switch (20) is closed, the control operation of the control circuit (16) causes the reading operation of the signal from the RAM (13) and the synthesizing operation of the ADPCM analyzing / synthesizing circuit (5) as shown in FIG. This is performed as shown in d). As is clear from the figure, only the beginning (A) to (C) of each phrase analyzed during the recording operation is read and synthesized, and the sound is emitted from the speaker (9). The order of the phrases in which the reading operation is performed is opposite to the direction in the recording operation. Each phrase between (A) and (C), that is, (A)
If it is set to 1/4 between 6 and 62.5 milliseconds, it will be rewound and played back at a speed 4 times faster than the playback operation described above, but unlike the tape recorder, the sound will be emitted from the speaker (9). Not only does the frequency of the reproduced signal not increase, but it is also emitted as a word, so the reproduced signal can be heard although it is fragmented. By performing the fast-forwarding operation and the rewinding operation described above, the reproducing operation position and the recording operation position can be found. Further, in the fast-forwarding operation state and the rewinding operation state, if the stop operation switch (21) is pressed and closed, the stop state can be switched.

While each operation in this embodiment is performed as described above, the display operation will be described below with reference to FIG. FIG. 3 uses a liquid crystal as the display (25). First, the clock display operation will be described. Such a display operation is performed by operating the display selection switch (26), but when the clock display state is reached, the display section (31) provided corresponding to the position printed with the clock is in the operating state. become. When such a clock display operation state is entered, the morning display (3
2), afternoon display (33), first display (3
4), the second display unit (35) that displays the minute and the colon unit (36) that blinks every one second are activated to display the time. In such a state, the signal from the clock circuit (22) is input to the drive circuit (24) through the display selection circuit (23), and the time is displayed on the display (25) by the drive operation by the drive circuit (24). Is displayed. Further, in such a state, the time can be corrected by operating the correction operation switch (27). Although the display operation as a clock is performed in this manner, other display operations will be described next. When the recording operation and the reproducing operation are performed, the recording operation and the reproducing operation described above are performed. In this state, the recording display section (37) and the reproduction display section (38) are in the operating state and each operation is performed. Is displayed. When the display selection switch (26) is operated to display the counter in the recording operation and the reproduction operation state, the display section (39) provided corresponding to the position printed with the counter. Becomes active. When the counter display operation is performed, the numeric display elements forming the first display section (34) and the second display section (35) display the count value. The counter signal output from the control circuit (16) in the counter display operation state is input to the drive circuit (24) through the display selection circuit (23), and the count value is output by the drive operation of the drive circuit (24). Is displayed on the display (25).
The counting signal output from the control circuit (16) is
This is performed based on the address signal controlled during the write operation to the RAM (13) and the read operation from the RAM (13).
For example, during the recording operation, during the phrase (a) writing operation and during the phrase (e) writing operation, the address control circuit (1
If the count value is incremented by 1 based on the address signal controlled by 4), the count value displayed on the display (25) will change every second. That is, if the count signal output from the control circuit (16) is set to change every second as described above, the count value displayed on the display (25) indicates the recording time.
Also, during the reproducing operation, the count value is incremented by 1 based on the address signal controlled by the address control circuit (14) during the phrase (a) reading operation and the phrase (e) reading operation. The count value displayed on the container (25) will change every second. That is, if the counting signal output from the control circuit (16) is set to change every second in this way, the display (25)
The count value displayed in indicates the playback time. As described above, the counter display operation is performed during the recording operation and the reproduction operation, but the counter display operation is similarly performed during the fast-forward operation and the rewind operation. That is, during the fast-forward operation, the operation shown in FIG. 2 (c) is performed as described above, but the address control circuit (14) is used during the read operation of the beginning of the phrase (a) and during the read operation of the beginning of the phrase (e). When the count value is incremented by 1 on the basis of the address signal controlled by), the count value displayed on the display (25) changes every 1/4 second. That is, the fast-forward operation is reproduced at a speed four times higher than that at the time of recording and reproducing operation as described above.
Since the count value displayed on the display (25) also increases at a speed four times higher, the counter display operation in the fast-forward operation state can be performed. In the counter display operation during the rewinding operation, although the count value is decreased, the operation is performed in the same manner as the fast forward operation, and the description thereof will be omitted.

The display operation as the counter is performed as described above. Next, the display operation of the remaining time will be described. When the container ( 15 ) is attached to the main body of the audio recording / playback device, the display selection switch (26) is operated to display the remaining time. The provided display section (40) is in the operating state. In such a state, the control circuit (16) changes the display selection circuit (23).
The signal output to (1) is output based on the signal obtained from the RAM (13). That is, the remaining time is calculated by the control circuit (16) from the signal indicating the used position of the memory, which is the index data written in the RAM (13), and the capacity of the memory, and the signal indicating the remaining time is displayed and selected. Circuit (2
It is output to 3). The signal indicating the remaining time is applied to the drive circuit (24) through the display selection circuit (23), and the remaining time is displayed on the display (25) by the driving operation of the drive circuit (24). And in this case indicator (25)
Minutes are displayed on the first display section (34) and seconds are displayed on the second display section (35), and at this time, the first display section (34) and the second display section (35) are displayed. The minute display section (41) and the second display section (42) respectively provided on the lower right side of the display are in the operating state, and the display operation of the minute and the second is performed by the first display section (34) and the second display section (35) Let the user know what is being done by. In addition, when recording, reproduction, fast-forwarding and rewinding operations are performed in such a state, the values of the second display section (35) and the first display section (34) change corresponding to the operation, and the state The remaining time of the RAM (13) in is displayed.

The remaining time display operation is performed as described above. Next, the consumed time display operation will be described. When the container ( 15 ) is attached to the main body of the audio recording / playback device, the display selection switch (26) is operated to display the consumption time. The display section (43) is turned on. The signal output from the control circuit (16) to the display selection circuit (23) in such a state is output based on the signal obtained from the RAM (13). That is, a signal indicating the use position of the memory, which is the index data written in the RAM (13), is read by the control circuit (16), and a signal indicating the consumption time is displayed on the basis of the read signal. 23) is output. The signal indicating the consumption time is the display selection circuit (2
3) is applied to the drive circuit (24), and the drive circuit (2
The consumption time is displayed on the display (25) by the driving operation by 4). In this case as well, the consumption time is displayed by the operation of the first display section (34), the second display section (35), the minute display section (41) and the second display section (42) which constitute the display device (25). It is displayed on the container (25). Further, when recording, reproduction, fast-forwarding and rewinding operations are performed in such a display state, the values of the second display section (35) and the first display section (34) change corresponding to the operations, The consumption time of RAM (13) in the state is displayed.

As described above, since the remaining time and consumption time of the RAM (13) can be displayed on the display (25), the display unit (2)
If you record and play while checking the numbers displayed in 5), you can prevent recording mistakes.

The recording / playback time can be extended by increasing the capacity of the RAM (13) or setting the sampling frequency low. In addition, the analysis and synthesis time during recording and playback is 25
0 ms, 6 minutes of composite time during fast forward and rewind operation
Although it is set to 2.5 milliseconds, the time is not limited. Although the count value during counter display operation is changed every 1 second, it can be changed variously such as every 0.5 seconds. Further, the display unit (25) is provided with a display unit for displaying the recording operation and the reproduction operation state, but it is also possible to provide a display unit for displaying that the fast forward or rewind operation is being performed.

(G) Effect of the Invention The recording control circuit of the present invention converts a recording signal obtained from a microphone into a digital signal and stores the digital signal in a semiconductor memory circuit that can be attached to and detached from the main body, and at the same time, in the semiconductor memory circuit during reproduction operation. In a voice recording / reproducing apparatus configured to read a stored signal, convert it to an analog signal, and emit the sound through a speaker, a semiconductor device is used as a recording end position, which is a memory use position when a recording operation is performed. In addition to writing the index data in the memory circuit, the recording operation is started from the end position when the recording operation is performed without any other operation after the semiconductor memory circuit is attached to the main body or after the power is supplied. The capacity of the memory can be used efficiently and the operability is excellent, and the present invention has a very great effect. Is played.

[Brief description of drawings]

The circuit shown in FIG. 1 is an embodiment of the present invention, FIG. 2 is a diagram for explaining the operation of the present invention, and FIG. 3 is an embodiment of a display. Description of main figure numbers (1) …… Microphone, (2) …… Amplification circuit for recording, (5) …… ADPCM analysis / synthesis circuit, (8) …… Amplification circuit for reproduction, (9) …… Speaker, ( 12 ) …… Voice processing circuit, (13) …… RAM, (14) …… Address control circuit,
(16) …… Control circuit, (22) …… Clock circuit, (23) ……
Display selection circuit, (24) …… Drive circuit, (25) …… Display unit, (29) …… Battery, (30) …… Power switch.

Claims (1)

[Claims] 1. A recording signal obtained from a microphone is converted into a digital signal and stored in a semiconductor memory circuit which can be attached to and detached from a main body, and after reading a signal stored in the semiconductor memory circuit during a reproducing operation. In a voice recording / playback device configured to convert into an analog signal and emit sound through a speaker, during recording and playback operations, ADPC
ADPCM analysis / synthesis circuit for performing speech analysis and speech synthesis by M method, writing operation of the digital signal output from the ADPCM analysis / synthesis circuit to the semiconductor memory circuit, and reading of signal stored in the semiconductor memory circuit An address control circuit for controlling the operation and an operation of writing index data to the semiconductor memory circuit, and controlling the operations of the ADPCM analysis / synthesis circuit, the semiconductor memory circuit and the address control circuit according to a recording operation, a reproducing operation and a high speed feed operation. The recording end position of the semiconductor memory circuit is written as index data when the recording operation is being performed, and the other operation is not performed after the semiconductor memory circuit is attached to the main body or after the power is supplied. When a recording operation is performed, recording is performed from the recording end position based on the index data. A recording control circuit for a voice recording / reproducing apparatus, which is characterized in that a sound operation is started.