JPH0769714B2 - Voice recording / playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention converts a recording signal obtained from a microphone into a digital signal and stores the digital signal in a semiconductor memory and a signal stored in the semiconductor memory during a reproducing operation. The present invention relates to a voice recording / reproducing device which is read and then converted into an analog signal and emitted by a speaker.

(B) Conventional technology Cassette type tape recorders that use magnetic tapes called cassette tapes have become widespread as a device for recording and reproducing sound. An apparatus using a magnetic tape as a means for recording an audio signal like such a cassette type tape recorder has an advantage that it can perform a recording operation for a long time, but it is difficult to downsize the apparatus. There is a problem that the failure rate is high because a mechanism for driving and driving the magnetic tape is required. As a device improved in this respect, an audio signal is converted into a digital signal and stored in a semiconductor memory, and at the time of a reproducing operation, a signal stored in the semiconductor memory is read out and then converted into an analog signal and sound is emitted from a speaker. The technology developed in this way has been developed.
There is one disclosed in Japanese Patent No. 0.

(C) Problems to be Solved by the Invention In the technology disclosed in the above-mentioned publication, a semiconductor memory is used as a means for recording an audio signal, so that a drive mechanism such as a tape recorder is unnecessary, and the device is small in size. It has the advantage that it can reduce the cost and failure rate. In such a technique, since the time for recording by designating an address is long, there is a problem that the memory portion stored in a non-recording portion, that is, a signalless portion is increased, and the capacity of the semiconductor memory cannot be used efficiently. is there. Further, since only the recording operation and the reproducing operation are performed, there is a problem that it takes time to search for necessary information. The present invention intends to provide a voice recording / reproducing apparatus in which such a point is improved.

(D) Means for Solving the Problems The voice recording / reproducing apparatus of the present invention uses ADPC during recording and reproducing operations.
ADPCM analysis / synthesis circuit for performing speech analysis and speech synthesis by M method, writing operation of digital signal output from the ADPCM analysis / synthesis circuit to semiconductor memory circuit, and reading operation of signal stored in the semiconductor memory circuit Address control circuit for controlling the recording operation switch, playback operation switch, high-speed feed operation switch and stop operation switch corresponding to the ADPCM analysis and synthesis circuit,
It comprises a semiconductor memory circuit and a control circuit for controlling the operation of the address control circuit.

(E) Operation The present invention performs the voice analysis / synthesis processing operation by the ADPCM analysis / synthesis circuit and the storage operation in the semiconductor memory circuit in a short time, and at the same time, only the beginning of each of the signals divided in the storage operation during the high-speed feed operation. Is to be played.

(F) Embodiment The circuit shown in FIG. 1 is an embodiment of the present invention, and FIG. 2 is a diagram for explaining the operation of the present invention. In the circuit shown in the figure, (1) is a microphone that converts an acoustic signal into an electric signal, and (2) is a recording amplifier that receives the recording signal converted into the electric signal by the microphone (1) and amplifies the signal. A circuit (3) is a low-pass filter for inputting the recording signal amplified by the recording amplifying circuit (2) and blocking unnecessary high frequency signals.
(4) is an AD converter for converting an analog signal passed through the low pass filter (3) into a digital signal,
(5) is an ADPCM analysis / synthesis circuit that performs digital processing by a method called ADPCM, that is, adaptive differential pulse code modulation,
(6) is a DA converter for converting the digital signal processed by the ADPCM analysis / synthesis circuit (5) into an analog signal, and (7) is converted into an analog signal by the DA converter (6). A low-pass filter for inputting a reproduction signal and blocking an unnecessary high-frequency signal, (8) a reproduction amplifier circuit for inputting a reproduction signal that has passed through the low-pass filter (7) and amplifying the signal, (9) ) Is a speaker to which the signal amplified by the reproduction amplifying circuit (8) is applied and which emits the signal. (10) is a control unit for controlling the analysis operation and the combining operation of the ADPCM analysis / synthesis circuit (5), and (11) is between an external circuit and the control unit (10) and the ADPCM analysis / synthesis circuit (5). A data I / O buffer circuit that controls signal input / output operations. In such a circuit, the AD converter (4), the ADPCM analysis / synthesis circuit (5), the DA converter (6), the control unit (10) and the data I / O buffer circuit (11) are audio processing circuits. ( 12 ) is constituted, but such a circuit may use, for example, LSI "MSM6258" manufactured by Oki Electric Industry Co., Ltd., and the details thereof will be omitted. (13) is a RAM which is a semiconductor memory for storing digital signals output from the data I / O buffer circuit (11) constituting the audio processing circuit ( 12 ), and (14) is a signal to the RAM (13). An address control circuit for controlling the write operation and the read operation of (1), (15) is a control circuit for controlling the operation of the voice processing circuit ( 12 ), the RAM (13) and the address control circuit (14). (16) is a recording operation switch that is pressed and closed when the audio signal is stored in the RAM (13), and (17) is pressed when the signal stored in the RAM (13) is read and reproduced. Playback operation switch that is closed, (18) operation switch for fast-forwarding that is pressed and closed during fast-forward operation, (19) operation switch for rewinding that is pressed and closed during rewinding operation, and (20) is stopped It is a stop operation switch that is pressed and closed during operation.

The present invention is configured as described above, and the operation will be described below. If the sampling frequency in the audio processing circuit ( 12 ) is 8 KHz and the number of quantization bits is 4, the bit rate will be 32 Kbits / sec. If the capacity of the RAM (13) is 1 Mbits, store it for about 32 seconds. Can be done. In the present invention, the analysis / synthesis processing by the ADPCM analysis / synthesis circuit (5) and the writing operation to the RAM (13) accompanying the processing are performed every 250 milliseconds. That is, the analysis / synthesis operation by the ADPCM analysis / synthesis circuit (5) is started by the start signal output from the control unit (10) incorporated in the voice processing circuit ( 12 ), and the control unit (10) is 250 milliseconds later. The analysis / synthesis operation is stopped by the stop signal output from the above. Then, during the operation of writing the signal to the RAM (13), that is, during the recording operation, the signal analyzed and processed by the ADPCM analysis / synthesis circuit (5) in the 250 ms is passed through the data I / O buffer circuit (11) to the RAM (13 ) And the RAM (1) by the control operation of the address control circuit (14).
It is written while the address is specified in 3). Also RAM
During the reading operation of the signal from (13), that is, the reproducing operation,
The signal synthesized by the ADPCM analysis / synthesis circuit (5) in the 250 ms is input to the DA converter (6) and converted into an analog signal. This way voice processing circuit ( 12 )
The control operation of the RAM (13) by the address control circuit (14) is performed, and each operation in this embodiment will be described below. When a recording operation is performed, power is supplied to the recording amplification circuit (2) and the recording operation switch (16) is pressed and closed, and the control operation for recording by the control circuit (15) is performed. The recording signal converted into an electric signal by the microphone (1) is input to the recording amplification circuit (2) and amplified, and then input to the audio processing circuit ( 12 ) through the low pass filter (3). The recording signal input to the audio processing circuit ( 12 ) is converted into a digital signal by the AD converter (4) and the analysis operation by the ADPCM analysis / synthesis circuit (5) is performed for 250 milliseconds each. Done. The signal analyzed and processed by the ADPCM analysis / synthesis circuit (5) is output to the RAM (13) through the data I / O buffer circuit (11) and written in the RAM (13) by the control operation of the address control circuit (14). Be done. Then, while the recording operation is being performed, the above-mentioned ADPC
Until the analysis operation by the M analysis / synthesis circuit (5) and the write operation to the RAM (13) are stopped or the RAM (13)
It will be repeated until the capacity of is exhausted. FIG. 2 (a) is for explaining such a recording operation,
The analysis operation by the ADPCM analysis / synthesis circuit (5) starts at point (A) and the analysis operation stops at point (B).
The interval between (B) and (B) is 250 milliseconds. The recording operation is performed in this manner, and the reproducing operation will be described next. When a reproducing operation is performed, power is supplied to the reproducing amplifier circuit (8) and the reproducing operation switch (17) is pressed and closed, and a control operation for reproduction by the control circuit (15) is performed.
The signal stored in the RAM (13) is read out by the control operation of the address control circuit (14) and the data is read.
It is input to the ADPCM analysis / synthesis circuit (5) through the I / O buffer circuit (11). The digital signal input to the ADPCM analysis / synthesis circuit (5) is subjected to synthesis processing by the ADPCM analysis / synthesis circuit (5) for 250 milliseconds each, and then D-
It is applied to the A converter (6) and converted into an analog signal. The signal converted into the analog signal by the DA converter (6) is input to the reproduction amplifier circuit (8) through the low-pass filter (7), amplified, and then emitted by the speaker (9). During the reproduction operation, the read operation from the RAM (13) and ADPCM
The synthesizing operation by the analysis and synthesizing circuit (5) is repeatedly performed until the stop operation is performed or until the signal written in the RAM (13) is lost. Figure 2 (b) shows
This reproduction operation is explained, and in point (A) ADPC
The synthesis operation by the M analysis / synthesis circuit (5) is started (B).
The combining operation stops at that point, but the interval between (A) and (B) is 25.
0 milliseconds.

The recording operation and the reproducing operation are performed as described above. Next, the fast-forwarding and rewinding operations will be described. When the user performs a fast-forward operation, the fast-forward operation switch (18) is closed and power is supplied to the reproducing amplifier circuit (8). When the fast-forward operation switch (18) is closed, the RAM (1
The operation of reading the signal from 3) and the combining operation by the ADPCM analysis / combination circuit (5) are performed as shown in FIG. 2 (c). As is clear from the figure, only the beginning (A)-(C) of the parts (A)-(B) that have been analyzed during the recording operation are read out and combined, and the sound is emitted from the speaker (9). Is sounded. Between (A) and (C)
If it is set to 1/4 of the period (B), that is, 62.5 milliseconds, it will be played back at a speed four times faster than the playback operation described above, but unlike the tape recorder, the speaker (9)
Since the frequency of the emitted signal does not increase, the reproduced signal can be heard although it is fragmented. The fast-forward operation is performed as described above, and the rewinding operation will be described next. When the rewinding operation is performed, the rewinding operation switch (19) is closed and power is supplied to the reproducing amplifier circuit (8). When the rewinding operation switch (19) is closed, the reading operation of the signal from the RAM (13) and the synthesizing operation by the ADPCM analysis / synthesizing circuit (5) become the second.
This is performed as shown in FIG. As is clear from the figure, only the beginning (A)-(C) of the parts (A)-(B) that have been analyzed during the recording operation are read out and combined, and the sound is emitted from the speaker (9). Although it is sounded, the read operation is in the opposite direction to the direction during the recording operation. Between (A) and (C) is 1/4 between (A) and (B), that is, 62.
If it is set to 5 milliseconds, it will be rewound and played back at 4 times speed, but unlike the tape recorder, not only the frequency of the signal emitted from the speaker (9) will not rise, but it will also be emitted as words. Therefore, the reproduced signal can be heard although it is fragmentary.

The recording / playback time can be extended by increasing the capacity of the RAM (13) or setting the sampling frequency low. Also, if the RAM (13) can be converted into an IC card, that is, the RAM (13) by incorporating it in a container called an IC card, the RAM (1
Even if the capacity of 3) is small, it can be used as a recording means instead of a tape recorder. Further, the analysis and synthesis time during the recording and reproducing operations was set to 250 milliseconds, and the synthesis time during the fast-forwarding and rewinding operations was set to 62.5 milliseconds, but the time is not limited.

(G) Effect of the Invention In the voice recording / reproducing apparatus of the present invention, the voice analysis / synthesis processing operation by the ADPCM analysis / synthesis circuit and the storage operation in the semiconductor memory circuit are performed in a predetermined time interval. If the recording operation is canceled, the storage operation of the memory circuit can be immediately stopped, and therefore, the capacity of the semiconductor memory circuit can be effectively used. During fast-forwarding and rewinding operations, that is, high-speed feeding operation, high-speed feeding operation is performed by reproducing only the beginning of each signal divided in a predetermined time during storage operation. The present invention has the advantage that it can be searched for as if to

BRIEF DESCRIPTION OF THE DRAWINGS The circuit shown in FIG. 1 is an embodiment of the present invention, and FIG. 2 is a diagram for explaining the operation of the present invention. Description of main figure numbers (1) …… Microphone, (2) …… Amplification circuit for recording, (5) …… ADPCM analysis / synthesis circuit, (8) …… Amplification circuit for reproduction, (9) …… Speaker, ( 12 ) …… Voice processing circuit, (13) …… RAM, (14) …… Address control circuit,
(15) …… Control circuit, (16) …… Recording operation switch,
(17) …… Operation switch for playback, (18) …… Operation switch for fast forward, (19) …… Operation switch for rewind, (20)
...... Operation switch for stop.

Claims (1)

[Claims] 1. A recording signal obtained from a microphone is converted into a digital signal and stored in a semiconductor memory circuit, and at the time of a reproducing operation, a signal stored in the semiconductor memory circuit is read out and then converted into an analog signal to a speaker. In a voice recording / reproducing device configured to emit sound by means of the above, an ADPCM analysis / synthesis circuit that performs voice analysis and voice synthesis in the ADPCM system during recording and reproduction operations, and the digital signal output from the ADPCM analysis / synthesis circuit. An address control circuit for controlling a writing operation to a semiconductor memory circuit and a reading operation of a signal stored in the semiconductor memory circuit, and a recording operation switch, a reproduction operation switch, a high-speed feed operation switch, and a stop operation switch. Operation of the ADPCM analysis / synthesis circuit, semiconductor memory circuit, and address control circuit corresponding to switching A control circuit for controlling, the voice analysis and synthesis processing operation by the ADPCM analysis and synthesis circuit and the storage operation to the semiconductor memory circuit are performed in a predetermined time interval, and at the beginning of each of the signals delimited during the high speed feed operation and the storage operation. An audio recording / playback device characterized in that only the playback is performed.