JPS63259898A - Display circuit for sound recording/reproducing device - Google Patents

Abstract

PURPOSE:To easily detect desired information by changing the count value which is displayed by the control signal based on the memory writing/reading actions. CONSTITUTION:In a sound recording state the count value is increased by one based on the address signal which is controlled an address control circuit 14 when a phase is written for each analyzing process. Thus the count value displayed on a display device 25 varies per second. Then the counting signal outputted from a control circuit 16 is set so that this counting signal varies per second. Thus the displayed count value shows the sound recording time. At the same time, the counting signal outputted from the circuit 16 is set so that it varies per second in a reproduction state. Thus the count value displayed on the device 25 shows the reproducing time.

Description

Detailed Description of the Invention (a) Industrial Application Field The present invention converts a recording signal obtained from a microphone into a digital signal and stores it in a semiconductor memory, and also converts the signal stored in the semiconductor memory during playback operation. The present invention relates to an audio recording and reproducing device that converts the audio into an analog signal after reading the audio and outputs the audio through a speaker.

(B) Conventional Technology Cassette tape recorders, which use magnetic tape called cassette tape, have become popular as devices for recording and playing back audio. Devices such as cassette-type recorders that use magnetic tape as a means of recording audio signals have the advantage of being able to perform long recording operations, but it is difficult to miniaturize the device. Additionally, since it requires a mechanism to drive the magnetic tape, there is a problem of a high failure rate. As an improved device in this respect, the audio signal is converted into a digital signal and stored in a semiconductor memory, and during playback operation, the signal stored in the semiconductor memory is read out, converted into an analog signal, and then emitted through a speaker. A technology has been developed to do this, and examples of such technology include, for example,
There is one disclosed in Japanese Patent No. 2800.

(c) Problems to be Solved by the Invention The technology disclosed in the above-mentioned publication uses a semiconductor memory as a means for recording audio signals, which eliminates the need for a drive mechanism such as a tape recorder, and the device It has the advantage of being smaller and lowering the failure rate. With this technique, only recording and playback operations are performed, so it takes time to search for necessary information, and there are problems in that the location where each operation is being performed cannot be determined. The present invention aims to provide an audio recording/playback device that is improved in this respect.

(d) Means for solving the problem The display circuit of the present invention includes an ADPCM analysis and synthesis circuit that performs voice analysis and synthesis using the ADPCM method during recording and playback operations, and a digital signal output from the ADPCM analysis and synthesis circuit. an address control circuit that controls writing operations of signals to the semiconductor memory circuit and reading operations of signals stored in the semiconductor memory circuit; It is comprised of a control circuit that controls the operation of the memory circuit and the address control circuit, and a display that numerically displays the usage status of the semiconductor memory circuit.

(E) Function The present invention provides output from a control circuit based on a write operation to a semiconductor memory circuit and a read operation of signals stored in the semiconductor memory circuit when in each operating state of recording, playback, and high-speed forwarding. The count value displayed on the display is changed depending on the signal received.

(F) Example The circuit shown in FIG. 1 is an embodiment of the present invention, FIG. 2 is a diagram for explaining the invention in detail, and FIG. 3 is an embodiment of a display. In this circuit, (1) is a microphone that converts an acoustic signal into an electrical signal, and (2) is a recording amplifier circuit that receives a recording signal converted into an electrical signal by the microphone (1) and amplifies the signal. , (3) is a low-pass filter into which the recording signal amplified by the recording amplifier circuit (2) is input and cuts off unnecessary high-frequency signals. (4) is a low-pass filter that cuts off unnecessary high-frequency signals. An A-D converter that converts an analog signal into a digital signal, (5> is an ADPCM analysis and synthesis circuit that performs digital processing using a method called ADPCM, that is, adaptive differential pulse code modulation, and (6) is the above-mentioned ADPC.
A D7A converter (7) converts the digital signal processed by the M analysis and synthesis circuit (5) into an analog signal. A low-pass filter (8
) is a reproduction amplification circuit which receives the reproduction signal that has passed through the low-pass filter (7) and amplifies the signal; (
9) is a speaker to which a signal amplified by the reproducing amplifier circuit (8) is applied and also emits the signal. (10) is a control unit that controls the voice analysis operation and voice synthesis operation of the ADPCM analysis and synthesis circuit (5); (11)
is an external circuit described later, the control section (10), and the ADP.
This is a data I10 buffer circuit that controls the input/output operation of signals to/from the CM analysis/synthesis circuit (5). In such a circuit, an A-D converter (4), an ADPCM analysis and synthesis circuit (5), a D-A converter (6), a control section (10) and a data 10 buffer circuit (11) are connected to an audio processing circuit (Tsubo ), but such a circuit may be, for example, LSI'MSM625B manufactured by Oki Electric Industry Co., Ltd., and its details will be omitted. (13) is the audio processing circuit (length).
A RAM (14) is a semiconductor memory that stores the digital signal output from the data I10 buffer circuit (11) constituting the data input buffer circuit (11) and writes the memory consumption time as index data. an address control circuit that controls operations, read operations, and index data write operations;
It is incorporated into a card-type container together with AM (13). The container is removably attached to the main body of the audio recording and reproducing device, and the RA is contained inside the container.
A backup battery (not shown) is incorporated to maintain the memory operation of M (13). (16) is a control circuit that controls the operations of the audio processing circuit (13), RAM (13), address control circuit (14), etc. (1
Reference numeral 7) denotes a recording operation switch which is suppressed and opened by the recording operation, and when the recording operation switch (17) is closed, the audio signal is stored in the RAM (13). (18) is a regeneration operation switch that is suppressed and opened by the regeneration operation;
) is closed, the signal stored in the RAM (13) is read and reproduced. (19) , (
20) and (21) are a fast-forward operation switch, a rewind operation switch, and a stop operation switch, which are pressed and closed during a fast-forward operation, a rewind operation, and a stop operation. (22
) is a clock circuit; (23) is a display selection circuit that selects a clock display signal output from the clock circuit (22) and a display signal output from the control circuit (16); (24)
is a drive circuit that drives the display device (25) based on the display signal selected by the display selection circuit (23). (
26) is a display selection switch that selectively changes the content displayed on the display (25), and each time it is pressed and closed, the content displayed on the display (25) is changed from clock display to counter display → It has the effect of switching in the order of remaining amount time display → consumption time display → clock display. (27) is a clock circuit (
A correction operation switch 22) is operated to correct the time, and a reset operation switch (28) is pressed and closed when the counter is displayed and resets the count value to zero.

The present invention is constructed as described above, and its operation will be explained next. If the zumbling frequency in the audio processing circuit (婬) is 8 KHz and the number of quantization bits is 4, the bit rate will be 32 bits/second, and if the capacity of the RAM (13) is 4M bits, it will take about 128 seconds. In the present invention, the speech analysis and synthesis processing by the ADPCM analysis and synthesis circuit (5) and the write operation to the RAM (13) accompanying the processing are divided into phrases every 250 milliseconds. It is done. That is, the analysis and synthesis operation by the ADPCM analysis and synthesis circuit (5) is started by a start signal output from the control unit (10) incorporated in the audio processing circuit (10), and after 250 milliseconds, the control unit (10) The voice analysis and synthesis operation is stopped by the stop signal output from the voice analysis/synthesis operation. When a signal is written to the RAM (13), that is, during a recording operation, the signal analyzed and processed by the ADPCM analysis and synthesis circuit (5) for the aforementioned 250 milliseconds is transferred to the RAM (13) through the data I10 buffer circuit (11). At the same time, it is written into the RAM (13) with an address specified by the control operation of the address control circuit (<14). Also, RAM(1
3), during the readout operation of the signal from the ADPCM analysis/synthesis circuit (
The signal synthesized by 5) is sent to a D-A converter (6).
is input and converted into an analog signal. The control operation of the RAM (13) is performed by the audio processing circuit (TSUBO) and the address control circuit (14) in this manner.Next, each operation in the wooden embodiment will be explained with reference to FIG.

When the user performs a recording operation, power is supplied to the recording amplifier circuit (2), the recording operation switch (17) is pressed and closed, and the control circuit (16) performs a control operation for recording. The recording signal converted into an electrical signal by the microphone (1) is input to the recording amplifier circuit (2), amplified, and then input to the audio processing circuit (Tsubo) through the low-pass filter (3).The audio processing circuit(
The recording signal input to (a) is converted into a digital signal by the A-D converter (4) and analyzed by the ADPCM analysis and synthesis circuit (5) as described above.
It takes place every millisecond. Further, the signal analyzed and processed by the ADPCM analysis and synthesis circuit (5) is data 110.
It is output to the RAM (13) through the buffer circuit (11) and is output to the RAM (13) by the control operation of the address control circuit (14).
(13) is written. While the recording operation is being performed, the above-mentioned analysis operation by the ADPCM analysis and synthesis circuit (5) and writing operation to the RAM (13) are repeated until a stop operation is performed or the capacity of the RAM (13) is exhausted. It will be done. Figure 2 (8) explains such a recording operation, in which the signal that has been subjected to audio analysis processing using the ADPCM method is divided into phrases kui), (b), kuha), etc. It is written to TS'cRAM (13). The analysis operation by the ADPCM analysis and synthesis circuit (5>) starts at point (A) of each phrase, and stops at point (B), and the period between (A) and (B) is 250 milliseconds. The recording operation is performed in this way, but
Next, we will explain the playback operation. When a regeneration operation is performed, power is supplied to the regeneration amplifier circuit (8), the regeneration operation switch (18) is pressed and closed, and the control circuit 6) performs a control operation for regeneration. RAM (13)
The signals stored in the address control circuit (14) are read out by the control operation of the address control circuit (14) and sent to the ADPCM analysis and synthesis circuit (11) through the data I10 buffer circuit (11).
5). The ADPCM analysis and synthesis circuit (5)
The input digital signals are synthesized by the ADPCM analysis and synthesis circuit (5) for 250 milliseconds each, and then applied to the D-A converter (6) and converted into analog signals. The signal converted into an analog signal by the device (6) is input to the reproduction amplifier circuit (8) through the low-pass filter (7), where it is amplified and then emitted by the speaker (9).Then, the reproduction operation is performed. While this is being carried out, the read operation from the RAM (13) and the synthesis operation by the ADPCM analysis and synthesis circuit (5) are repeated until a stop operation is carried out or until there are no more signals written in the RAM (13). FIG. 2(b) shows such a playback operation, and the phrases (A), (A), (
According to (b), (c)..., the ADPCM analysis and synthesis circuit (5) performs the speech synthesis processing operation and performs the reproduction operation. The synthesis operation by the ADPCM analysis and synthesis circuit (5) starts at point (A) of each phrase, and the synthesis operation stops at point (B), but between (A) and (B) there are 25
It is 0 milliseconds.

Recording and reproducing operations are performed as described in section 2 below.Next, the operations when fast-forwarding and rewinding operations are performed will be explained. When the fast-forward operation is performed, the fast-forward operation switch (19) is closed and power is supplied to the reproduction amplifier circuit (8). The fast forward operation switch (19)
When the bag is closed, the control circuit (16) performs a control operation to read signals from the RAM (13) and ADPC.
The synthesis operation by the M analysis and synthesis circuit (5) is performed as shown in FIG. 2(c). As is clear from the figure, the beginning part (A) ~ < of each phrase that was analyzed during recording operation.
The readout and synthesis processing operations are performed only during the interval C>, and the sound is emitted from the speaker (9). Between (A) and (C), each phrase is 174 or 62.5 between (A) and (B).
If you set it to milliseconds, the playback will be four times faster than the playback operation described above, but Cheapleni 1
- Unlike Goo, the frequency of the signal emitted from the speaker (9) does not become high, so the reproduced signal can be heard, albeit in fragments. The operation when performing the fast forward operation is performed in this way, but the operation when the rewind operation is performed will be explained next. When the rewinding operation is performed, the rewinding operation switch (20) is closed and power is supplied to the reproducing amplifier circuit (8). When the rewind operation switch (20) is opened, the control circuit (16) performs a control operation to read out signals from the RAM (13) and perform synthesis by the ADPCM analysis and synthesis circuit (5) as shown in FIG. 2(d). ).

As is clear from the figure, only the beginning part (A) to <C> of each phrase analyzed during the recording operation is read out and synthesized, and the sound is emitted from the speaker (9). The order of the phrases in which the reading operation is performed is in the opposite direction to the direction during the recording operation.
-(C) for each phrase, i.e. 174 between (A) and (B)
In other words, if it is set to 62.5 milliseconds, it will be rewound and played back four times faster than during the playback operation described above, but unlike a tape recorder, the frequency of the signal emitted from the speaker (9) is high. Not only does it not sound, but it is also emitted as words, so the reproduced signal can be heard, albeit in fragments. As described above, each operation is performed when the fast-forwarding operation and the rewinding operation are performed, but if the stop operation switch (21) is suppressed and opened while in such an operating state, it is possible to switch to the stopped state.

Each operation in this embodiment is performed as described above, and next, the display operation will be explained with reference to FIG. 3. FIG. 3 shows an example in which a liquid crystal is used as the display (25). First, the clock display operation will be explained. Such display operation is
This is done by operating the display selection switch (26), and when the clock display state is entered, the display section (29) provided corresponding to the position where the word "clock" is printed becomes operational.

When the clock display becomes operational, the AM display section (30),
Afternoon display section (31), first display section (32) that displays the time
, a second display section (33) that displays minutes, and a colon section (34) that flashes every second are activated to display the time. In this state, a signal from the clock circuit (22) is input to the drive circuit (24) through the display selection circuit (23), and the time is displayed on the display (25) by the drive operation of the drive circuit (24). Is displayed. In addition, in this state, the time can be corrected by operating the correction operation switch (27).The display operation as a clock is performed in this way, but other display operations will be explained next.

When a recording operation and a playback operation are performed, the above-mentioned recording operation and playback operation are performed, but in such a state, the recording display section (35) and the playback display section (36) are activated and each operation is performed. display that the When the display selection switch (26) is operated to display the counter during such recording and playback operation, a display section (37) provided corresponding to the counter and the printed position will be displayed. becomes operational. When the counter display operation is performed, the number display elements forming the first display section (32) and the second display section (33) display the count value. When the count signal is in the display operation state, the count signal outputted from the control circuit (16) is input to the drive circuit (24) through the display selection circuit (23), and the drive circuit (24) is operated by the drive circuit (24). The count value is displayed on the display (25)
will be displayed. The counting signal output from the control circuit (16) is performed based on the address signal controlled during write operations to the RAM (13) and read operations from the RAM (13). For example, during the recording operation, the count value is incremented by one based on the address signal controlled by the address control circuit (14) during the write operation of the phrase (A) and the write operation of the phrase (E). ) is displayed when the count value is 1.
It will change every second. In other words, the control circuit (
If the count signal output from 16) is set to change every second, the count value displayed on the display (25) will indicate the recording time. In addition, during the playback operation, the count value is similarly increased by one based on the address signal controlled by the address control circuit (14) during the readout operation of the phrase (A) and the readout operation of the phrase (E). The count value displayed on the device (25) changes every second. That is, in this way, the count signal output from the control circuit (16) is 1.
If the count value is set to change every second, the count value displayed on the display (25) will indicate the playback time. As described above, the counter display operation is performed during the recording operation and the playback operation, but the counter display operation is similarly performed during the fast forwarding operation and the rewinding operation. That is, during the fast forward operation, the operation shown in FIG. 2(c) is performed as described above, but when the beginning of the phrase (A) is read out and the beginning of the phrase (E) is read out, the address control circuit <14>> The count value is increased by one based on the address signal controlled by the display (25
) will change every 174 seconds. That is, as mentioned above, the fast-forward operation is played back at four times the speed as compared to the recording and playback operations, but the count value displayed on the display (25) also increases at four times the speed, so it is in the fast-forward operation state. The counter display operation can be performed. Further, the counter display operation during the rewinding operation is performed in the same manner as during the fast forwarding operation, although the count value decreases, so a description thereof will be omitted.

The display operation as a counter is performed as described above, but next, the display operation of the remaining amount time will be explained. When in recording or playback mode, press the display selection switch (2).
6) to display the remaining amount time, the display section (
38) becomes operational. In this state, the signal output from the control circuit (16) to the display selection circuit (23) is output based on the signal obtained from the RAM (13). That is, the index data written in the RAM <13> is completely read by the control circuit (16), and based on the read signal, a signal representing the remaining amount of time is output to the display selection circuit (23). The signal representing the remaining amount of time is applied to the drive circuit (24) through the display selection circuit (23>), and the remaining amount of time is displayed on the display (25) by the driving operation of the drive circuit (24). In this case, the minutes are displayed on the first display section (32) constituting the display (25), and the seconds are displayed on the second display section (33). Second
The minute display section (39) and second display section (40), which are provided at the lower right side of the display section (33), are activated, and the minute and second display operations are performed on the first display section (32) and the second display section (32). Display section (
33) Make the user aware of what is being done. In addition, when recording, playback, fast forwarding, or rewinding operations are performed in such a state, the values on the second display section (33) and first display section (32) change in accordance with the operation, and the values in the second display section (33) and the first display section (32) change in accordance with the operation. The remaining time of RAM (13) is displayed.

The operation of displaying the remaining amount time is performed as described above, but next, the operation of displaying the consumed time will be explained.

When the display selection switch (26) is operated to display the consumption time during recording and playback operation, a display section (41) is provided corresponding to the position where the consumption amount is printed. becomes operational.

In such a state, the signal outputted from the control circuit (16) to the display selection circuit (23) is the same as when the remaining amount is displayed.
It is uniformly output based on the signal obtained from RAM (13). That is, the index data written in RAM (13) is read by the control circuit (16),
Based on the read signal, a signal representing the consumed time is output to the display selection circuit (23). The signal representing the consumed time is sent to the drive circuit (24) through the display selection circuit (23).
), and the consumed time is displayed on the display (25) by the drive operation by the drive circuit (24).

Also in this case, the first display section (32), second display section (33), and minute display section (39) that constitute the display device (25)
The consumed time is displayed on the display (25) by the operation of the seconds display section (40). In addition, when recording, playback, fast forwarding, or rewinding operations are performed in such a state, the second display section (33) and the first display section (32) will be displayed in response to the operation.
The value changes, and the time consumed by the RAM (13) in that state is displayed.

Note that the recording and playback time can be increased by increasing the capacity of RAM (13) or by setting the sampling frequency low. Furthermore, the analysis and synthesis time during recording and playback operations was set to 250 milliseconds, the fast forwarding and rewinding time was set to 62.5 milliseconds, but the time is not limited. Although the count value is set to change every second during the counter display operation, it is possible to make various changes such as changing every 0.5 seconds. Further, although the display device (25) is provided with a display section to indicate that the recording operation and the playback operation are in progress, it is also possible to provide a display section or the like to indicate that fast forwarding or rewinding operation is being performed.

(G) Effects of the Invention The display circuit of the present invention converts a recording signal obtained from a microphone into a digital signal and stores it in a semiconductor memory circuit, and after reading out the signal stored in the semiconductor memory circuit during playback operation. When a writing operation to a semiconductor memory circuit and a reading operation of a signal stored in the semiconductor memory circuit are performed in an audio recording/playback device configured to convert the signal into an analog signal and emit the sound through a speaker. Since the count value displayed on the display is changed in response to the operation, it has the advantage that necessary information can be found as if operating a tape recorder.

[Brief explanation of the drawing]

The circuit shown in FIG. 1 is an embodiment of the present invention, FIG. 2 is a diagram for explaining the invention in detail, and FIG. 3 is an embodiment of a display. Explanation of main drawing numbers (1)... Microphone, (2>... Recording amplifier circuit, (5)... ADPCM analysis and synthesis circuit, (8)
... reproduction amplifier circuit, (9) ... speaker,
(婬)...Audio processing circuit, (13)...RAM,
(14)...address control circuit, (16)...
・Control circuit, (22)...Clock circuit, (25>・
··display.

Claims (1)

[Claims] (1) Convert the recording signal obtained from the microphone into a digital signal and store it in a semiconductor memory circuit, and during playback operation, read out the signal stored in the semiconductor memory circuit, convert it into an analog signal, and emit it through a speaker. In a voice recording and playback device configured to produce sound, an ADPCM analysis and synthesis circuit that performs voice analysis and voice synthesis using an ADPCM method during recording and playback operations;
an address control circuit for controlling the writing operation of digital signals output from the analysis and synthesis circuit to the semiconductor memory circuit and the reading operation of the signals stored in the semiconductor memory circuit; a control circuit that controls the operations of the ADPCM analysis and synthesis circuit, semiconductor memory circuit, and address control circuit accordingly;
and a display that numerically displays the usage status of the semiconductor memory circuit, and when in each operating state, the semiconductor memory circuit is operated based on the write operation to the semiconductor memory circuit and the read operation of signals stored in the semiconductor memory circuit. 1. A display circuit for an audio recording/playback device, characterized in that a count value displayed on the display device is changed by a signal output from a control circuit.