JP3727689B2 - Digital audio recording / reproducing device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a digital audio recording / reproducing apparatus.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a digital audio recording / reproducing apparatus capable of converting an analog signal input from a microphone into a digital signal and recording it on a recording medium such as a semiconductor memory, converting the recorded signal into an analog signal, and reproducing it with a speaker is conventionally known. ing.
[0003]
In such a digital audio recording / reproducing apparatus, in order to save memory capacity, some data compression method is used in order to minimize the amount of data to be stored.
[0004]
For example, Japanese Patent Laid-Open No. 63-259700 discloses an apparatus for compressing audio information by the ADPCM method and storing it in a semiconductor memory. As a more efficient compression method, there is a CELP (Code Excited Linear Prediction) compression method called VSELP (Vector Sum Excited Linear Prediction), which is used as a standard compression method in mobile phones and the like in recent years. This compression method is an extremely efficient method of vector quantization of a sound source signal of an LPC synthesis filter using a code book having various patterns, and is the most powerful method for obtaining good sound quality even if the bit rate is reduced. one of. Since this compression method requires a large amount of computation and requires computation in real time, a DSP (Digital Signal Processor) that can compute digital signals at high speed is usually used.
[0005]
[Problems to be solved by the invention]
However, the CELP compression method described above also has a drawback that the sound quality deteriorates when the bit rate is extremely low, for example, less than half. Further, in the above-described CELP compression method, when the bit rate is lowered, the analysis calculation process during compression is usually reduced. For this reason, if the same DSP is used to calculate the CELP compression algorithm with a different bit rate, the compression algorithm with a low bit rate has a small amount of calculation processing, so that it can be processed without much use of the DSP processing capability. Become. This means that the power of the power supply is consumed unnecessarily without making full use of the DSP's arithmetic processing capability. For example, if the power supply to the DSP is a battery, the battery life is shortened. There was also.
[0006]
The digital audio recording / reproducing apparatus of the present invention has been made paying attention to such problems, and the object thereof is that there is no deterioration in sound quality even if signal processing is performed at different bit rates, and the signal processing means. It is an object of the present invention to provide a digital audio recording / reproducing apparatus capable of effectively using a current supplied to a computer.
[0007]
[Means for Solving the Problems]
In order to achieve the above object, a digital audio recording / reproducing apparatus for reading out and reproducing a digital audio signal compressed and encoded from a recording medium, A post filter in which the above filters are cascade-connected in the order of a first zero filter, a pole filter, and a second zero filter of the first order. A signal processing means for decoding a compression-encoded digital audio signal read from the recording medium, and a bit rate selected by the bit rate selection means when the digital audio signal is compression-encoded. Obtaining means, a changing means for changing an operation clock frequency of the signal processing means at the time of decoding according to the bit rate obtained by the bit rate information obtaining means, and the bit rate information obtaining means Depending on the bitrate The coefficient of the second zero filter is change And changing means .
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a digital audio recording / reproducing apparatus as an embodiment of the present invention. In the figure, a microphone 1 includes a digital signal processor (hereinafter referred to as a DSP) 5 through an amplifier (AMP) 2, a low-pass filter (LPF) 3, and an analog / digital (A / D) converter 4. Connected to one terminal. The speaker 13 is connected to the second terminal of the DSP 5 via an amplifier (AMP) 12 and a digital / analog (D / A) converter 11.
[0014]
The third terminal of the DSP 5 is connected to the first terminal of the data I / O (input / output) buffer 7, and the fourth terminal of the DSP 5 is connected to the second terminal of the data I / O buffer 7 via the control circuit 6. The third terminal of the data I / O buffer 7 is connected to the first terminal of the main control circuit 8. Further, the fifth terminal of the DSP 5 is connected with two types of crystals X1 and X2 connected in parallel and a multiplexer MPX for selecting one of these two crystals X1 and X2. The crystals X1 and X2 have different operation clock frequencies.
[0015]
The second terminal of the main control circuit 8 is grounded via the main power switch 16 and the battery BAT, the third terminal is connected to the recording button REC, the fourth terminal is connected to the playback button PL, and the fifth terminal is Connected to the stop button ST, the sixth terminal is connected to the fast forward button FF, the seventh terminal is connected to the fast reverse button REW, the eighth terminal is connected to the I mark button, and the ninth terminal is connected to the E mark button. The tenth terminal is connected to the bit rate changeover switch RATE.
[0016]
Further, the eleventh terminal of the main control circuit 8 is connected to the display 15 via the drive circuit 14, the twelfth terminal is connected to the semiconductor memory 10 as a detachable recording medium, and the thirteenth terminal is connected to the semiconductor memory 10. It is connected to the connected address control circuit 9.
[0017]
The above-mentioned I mark button and E mark button are index marks for giving some instruction to the typist or secretary, and are operated in the following cases. For example, when a sentence recorder uses this apparatus to record a plurality of sentences, by operating the I mark button I, an instruction (I) mark indicating a priority relationship between the plurality of sentences is simultaneously recorded, By voice, it is possible to instruct the priority relationship of sentences specifically for typists and secretaries. Further, by operating the E mark button, the E mark can be recorded and a typist or the like can be instructed to delimit a plurality of documents.
[0018]
Hereinafter, the internal configuration of the semiconductor memory 10 will be described. The inside of the semiconductor memory 10 is composed of a temporary recording medium part and a main recording medium part. As the temporary recording medium section, an SRAM, EEPROM, high dielectric memory, flash memory or the like that can read and write at a relatively high speed compared to the main recording medium section is used. A flash memory, a magneto-optical disk, a magnetic disk, a magnetic tape, or the like is used as the main recording medium. In this embodiment, among these, SRAM is used for the temporary recording medium section, and flash memory is used for the main recording medium section.
[0019]
By the way, the semiconductor memory 10 has a recording configuration as shown in FIG. 2 in this embodiment. That is, the memory space is largely divided into an index part 10A and an audio data part 10B. The index section 10A includes operation start position information 10A1 and operation end position information 10A2 for each of a plurality of voice message files 10B1, 10B2, 10B3,... Recorded in the voice data section 10B. Is recorded. In addition, motion position information 10A3 indicating the current motion position in the audio data portion 10B is recorded.
[0020]
The operation of the digital audio recording / reproducing apparatus having the above configuration will be described below. At the time of voice recording, an analog signal obtained from the microphone 1 is amplified by an amplifier (AMP) 2, passed through a low-pass filter (LPF) 3, and then converted into a digital voice signal by an analog / digital (A / D) converter 4. Is converted to This digital signal is input to the DSP 5. The DSP 5 compresses the digital audio signal at a predetermined bit rate under the control of the control circuit 6. The compressed digital signal is output to the main control circuit 8 via the data I / O buffer 7.
[0021]
The main control circuit 8 controls the operations of the DSP 5, the address control circuit 9, and the semiconductor memory 10 in accordance with the operation of the plurality of operation buttons and switches described above. For example, during recording, an appropriate address signal is given to the address control circuit 9 and the digital audio signal supplied from the data I / O buffer 7 is recorded in the semiconductor memory 10.
[0022]
When the digital audio signal recorded in this way is reproduced, the main control circuit 8 gives an appropriate address signal to the address control circuit 9, reads out the digital audio signal recorded in the semiconductor memory 10 and reads the data I / O buffer. 7 to be supplied to the DSP 5. The digital audio signal is expanded by the DSP 5 and then converted into an analog audio signal by a digital / analog (D / A) converter 11. This analog audio signal is amplified by an amplifier (AMP) 12 and output from a speaker 13. The main control circuit 8 controls the drive circuit 14 to display various information such as the operation mode on the display unit 15 during the recording or reproduction operation.
[0023]
Hereinafter, the operation of the digital audio recording / reproducing apparatus will be described in more detail with reference to the flowchart of FIG.
When the battery BAT is set and power is supplied to the main control circuit 8, the main control circuit 8 detects the power supply voltage and starts an operation as shown in the flowchart of FIG.
[0024]
That is, first, external conditions of the main control circuit 8 and initial setting of the internal storage unit are performed (step S1). However, at this time, the main power switch 16 for instructing power supply to the entire digital audio recording / reproducing apparatus is in the OFF state. Therefore, after completing the initial setting, the main control circuit 8 detects whether or not the main power switch 16 is in the ON state (step S2). As a result of detection, if it is detected that the main power switch 16 is in the ON state, a switch (not shown) provided between the battery BAT and each circuit for supplying power to the entire digital audio recording / reproducing apparatus is provided. Turn it on. In step S3, the memory index is read. That is, the operation start position information 10A1, the operation end position information 10A2, and other code modes and operation conditions are read from the index portion 10A of the semiconductor memory 10. At this time, based on the data read from the semiconductor memory 10, it is determined whether or not a predetermined index is normally recorded in the semiconductor memory 10 in advance, that is, whether or not the format (initialization) of the semiconductor memory 10 is normal (step S4). .
[0025]
If the memory format is normally performed, the process proceeds to step S7 to perform the process described later.
On the other hand, when an unformatted one is recorded in the semiconductor memory 10, it is determined that the data is not normal, information indicating a use condition is input to the index portion 10A of the semiconductor memory 10, and “ It is confirmed whether or not to perform memory formatting, which is a process of inputting 0 ″ (step S5). In this case, the main control circuit 8 controls the drive circuit 14 to display on the display 15 whether or not to perform memory formatting.
[0026]
Here, when a button for confirming that memory formatting is not to be performed (also used as the stop button ST) is pressed, the main control circuit 8 controls the drive circuit 14 to display 15 in the error display step of step S8. A battery BAT and each circuit for displaying that the semiconductor memory 10 is not normal and for indicating that the semiconductor memory 10 should be replaced and for supplying power to the entire digital audio recording / reproducing apparatus. A switch (not shown) provided between is turned off. Thereafter, the process waits until the main power switch 16 is turned off to replace the semiconductor memory 10 (step S9).
[0027]
If the button for confirming the memory format process (also used as the recording button REC) is pressed in step S5, the semiconductor memory 10 is formatted (step S6), and the process proceeds to step S7.
[0028]
In step S7, the drive circuit 14 is controlled to display on the display 15 that the initial setting is completed, and the current operation position is detected based on the operation position information 10A3 read from the index unit 10A (step S10). ), The drive circuit 14 is controlled, and the display 15 displays the detected current position. Thereafter, each circuit is set in a standby state while detecting whether any one of the operation buttons of the digital audio recording / reproducing apparatus is pressed (step S11).
[0029]
When it is detected that any one of the operation buttons is pressed, first, it is detected whether or not the operation is the recording button REC (step S12). If the recording button REC is pressed, the DSP 5 is controlled. The audio information input from the A / D converter 4 is compressed, and the address control circuit 9 is controlled to enter a recording process for recording in the audio data section 10B of the semiconductor memory 10 (step S13).
[0030]
If it is not the record button REC that has been operated, it is next detected whether or not the play button PL has been pressed (step S14). If the play button PL has been pressed, the address control circuit 9 is controlled to read the recorded audio data from the audio data section 10B of the semiconductor memory 10, and this is sent to the DSP 5 for decompression processing. Thereafter, the D / A converter 11 converts the signal into an analog signal and starts the reproduction process of outputting from the speaker 13 (step S15).
[0031]
When the playback button PL is not pressed, it is detected whether or not the fast forward button FF is pressed (step S16). If the fast-forward button FF has been pressed, a fast-forward process is performed in which the operation position is sequentially fast-forwarded at an appropriate speed (for example, 20 times that during reproduction) (step S17).
[0032]
If the fast-forward button FF is not pressed, it is detected whether or not the fast-return button REW is pressed (step S18). If the fast-return button REW has been pressed, a fast-return process for moving the operating position at the same speed in the direction opposite to that in the case of fast-forward is entered (step S19).
[0033]
When the stop button ST is pressed during each of the above-described steps S13, S15, S17, and S19, the processing exits from each processing and returns to step S11.
If the operated button is not a button for recording, playback, fast forward, fast reverse, etc., it is detected whether or not the main power switch 16 is OFF and various setting button states are detected (step S20). When the main power switch 16 is turned off, the address control circuit 9 is controlled to erase the information in the index section 10A of the semiconductor memory 10 and store it in a storage section (not shown) inside the main control circuit 8. The index information is transferred to the index part 10A of the semiconductor memory 10 (step S21). When this index transfer process is completed, a switch (not shown) provided between the battery BAT and each circuit is turned off (step S22), and the process returns to step S2.
[0034]
If it is determined in step S20 that the main power switch 16 is not OFF, the state of the setting button is detected, the state is stored in the internal storage unit, and the process returns to step S11. Here, the setting button is not a button actually provided separately in the digital audio recording / reproducing apparatus, but a recording button REC, a reproduction button PL, a stop button ST, a fast forward button FF, a fast reverse button REW, and an I mark button. These buttons are substituted by simultaneously pressing several of the I and E mark buttons E.
[0035]
Next, details of the recording process in step S13 of FIG. 3 will be further described with reference to the flowchart of FIG.
When it is detected that the recording button REC has been pressed, the process proceeds to this recording process. First, it is detected by the bit rate changeover switch RATE which bit rate is selected from the normal bit rate and the half bit rate (step). S31). If the normal bit rate is selected here, the crystal is switched to X1 by the multiplexer MPX (step S32). If the half bit rate is selected, the crystal is switched to X2 (step 33). Thereby, the operation clock frequency of the DSP 5 at the time of speech encoding is set. Information on the voice recording mode such as RATE selection information and recording sensitivity information at this time is transferred to the DSP 5 as a command (step 34). Then, the recording start position in the audio data section 10B of the semiconductor memory 10 is obtained based on the index information (operation position information) stored in the internal storage section, and information related to the recording start position is stored in the index section 10A as operation start position information. Write as 10A1 (step S35). Here, the DSP 5 processes a digital audio data group having a predetermined length (for example, 20 ms) as a frame, and here, digital audio data for one frame is encoded at a set operation clock frequency (step 36). The obtained encoded data for one frame is transferred to the main control circuit 8 (step 37). Then, the address where the transferred encoded data is to be written is calculated based on the operation position information stored in the internal storage unit, and is output to the address control circuit 9 (step S38). At the same time, one frame of encoded data from the DSP 5 is sent to the semiconductor memory 10 and written into the audio data section 10B under the control of the address control circuit 9 (step S39). In step S40, the recording position is updated. That is, the operation position information stored in the internal storage unit is updated, and the operation end position information 10A2 and the current operation position information 10A3 of the index unit 10A are updated according to the updated value.
[0036]
Next, it is detected whether or not the stop button ST is pressed (step S41). If not pressed, the process jumps to step S35 to execute the recording process described above. Then, when the stop button ST is pressed, the end position at that time is determined and the recording process is exited.
[0037]
Here, the DSP 5 uses a CELP encoding (analytical synthesis type encoding) method in order to encode the audio data in step S36. This CELP encoding method is a method for very efficiently vector quantizing a driving excitation signal of an LPC synthesis filter analyzed in units of frames using a code book having various waveform patterns. The data to be encoded is RATE selection information, voiced / silent voice information, LPC coefficient index information of the 10th order, and index information for generating a driving excitation signal of the LPC synthesis filter for each frame. When recording at the normal bit rate, encoding is performed at 8 Kbit / second, and at recording at the half bit rate, encoding is performed at 4 Kbit / second. Furthermore, encoding is performed so that the processing amount at this time can be processed within 20 MIPS (Million Instructions Per Second) at the normal bit rate and within 12 MIPS at the half bit rate. At this time, crystals X1 and X2 described above are used according to each bit rate.
[0038]
Next, the reproduction process in step S15 of FIG. 3 will be described in detail with reference to the flowchart of FIG.
When it is detected that the playback button PL has been pressed, the process proceeds to the playback process, and the main control circuit 8 first transfers information related to the audio playback mode such as volume volume value information from the main control circuit 8 to the DSP 5 as a command. (Step S50). Then, the read position of the audio data section 10B of the semiconductor memory 10 is obtained from the operation position information of the index information section 10A, and the drive circuit 14 is controlled and displayed on the display section 15 (step S51). Then, in order to read audio information from the audio data unit 10B of the semiconductor memory 10, an address calculated based on the operation start position information stored in the internal storage unit is output to the address control circuit 9 (step 52). The main control circuit 8 reads one frame of audio encoded data from the audio data portion 10B of the semiconductor memory 10 in accordance with this address (step 53). Next, the read voice encoded data for one frame is transferred to the DSP 5 (step S54), and the voice encoded data for one frame is synthesized (step S55).
[0039]
Next, the processing of the main control circuit 8 proceeds to step S56 and updates the reproduction position. That is, the reproduction position (operation position) information stored in the internal storage unit is updated, and the current operation position information 10A3 of the index unit 10A is updated. Thereafter, it is detected whether or not the stop button ST is pressed (step S57). If it has been pressed, the reproduction process is exited. If not, the process returns to step S53 to continue the reproduction process.
[0040]
Next, the process of synthesizing speech encoded data for one frame in step S55 will be described in detail with reference to the flowchart of FIG. A driving excitation signal is generated from speech encoded data for one frame sent to the DSP 5 (step S60), and speech synthesis processing is performed by a 10th-order LPC synthesis filter to generate a speech synthesis signal (step S61). Based on the RATE selection information at the time of speech encoding, it is determined which of the normal bit rate and the half bit rate is selected (step S62). If the normal bit rate is selected, the normal bit rate is selected. Post filter processing (noise removal processing) is performed through the speech synthesis signal through a rate post filter, that is, a noise filter for removing noise (step S64), and if the half bit rate is selected, the post for half bit rate is performed. Post-filter processing is performed through the speech synthesis signal through the filter (step S63).
[0041]
FIG. 7 is a diagram showing the configuration of the above-described post filter, and has a configuration in which three stages of filters are cascade-connected. The first-stage filter is a tenth-order zero filter 23, and includes delay units T1 to T10, multipliers M1 to M10 that multiply the audio signal delayed by each delay unit by a predetermined coefficient, and no delay. And an adder 20 for adding a multiplication result from each multiplier to the audio signal. As the coefficients of the multipliers M1 to M10, coefficients aα1 to aα10 obtained by multiplying the coefficients aexp1 to aexp10 obtained by frequency band expansion of the 10th-order LPC coefficients a1 to a10 and the weight 0.75 are used.
[0042]
The second-stage filter is a tenth-order pole filter 24, delay units T1 to T10, multipliers M11 to M20 for multiplying the audio signal delayed by each delay unit by a predetermined coefficient, and an audio signal without delay. And an adder 21 for adding the multiplication results from the multipliers. As the coefficients of the multipliers M11 to M20, coefficients aβ1 to aβ10 obtained by multiplying the coefficients aexp1 to aexp10 with the frequency band expanded by a weight of 0.5 are used. The third-stage filter is a first-order zero filter 25, a delay unit T, a multiplier M that multiplies the audio signal delayed by the delay unit T by a predetermined coefficient, and a multiplication from the multiplier M. It comprises an adder 22 for adding the value and the audio signal without delay. The primary coefficient of the multiplier M is a value b obtained by multiplying the primary coefficient aβ1 of the multiplier M11 of the second-stage pole filter 24 by a weight of 0.5.
[0043]
Here, when the normal bit rate is selected by the bit rate changeover switch RATE, it is determined whether or not the first-order coefficient b of the multiplier M of the third-stage first-order zero filter 25 is greater than 0. If it is detected and the value is larger than 0, the coefficient value b is set to 0, and if it is negative, the coefficient value b is set to the above-mentioned coefficient value b for filtering. On the other hand, when the half bit rate is selected, the post filter performs filtering using a value -b obtained by multiplying the first-order coefficient b of the multiplier M of the first-order zero filter 25 of the third stage by -1. Do. Thus, in the present embodiment, the frequency characteristics of the post filter are changed according to the selected bit rate.
[0044]
According to the above-described embodiment, since the frequency characteristics of the post filter are changed according to the selected bit rate, there is no deterioration in sound quality even if the bit rate is lowered. Further, since the operation clock frequency of the DSP 5 that performs compression encoding is changed according to the bit rate, the magnitude of the current consumption also changes accordingly. As a result, the power supply can be saved and the current supplied to the DSP 5 can be used effectively.
[0045]
As described above, the digital audio recording / reproducing apparatus of the present embodiment is a digital audio recording / reproducing apparatus that records and reproduces a digital audio signal on a recording medium (semiconductor memory 10), prior to writing to the recording medium or After reading from the recording medium, the signal processing means (DSP 5) for processing the digital audio signal at a predetermined bit rate (normal bit rate or half bit rate) and the selection means for selecting a desired bit rate (bit rate switching) Switch RATE) and changing means (main control circuit 8) for changing the processing conditions of the signal processing means (the frequency characteristics of the post filter or the operating clock frequency of the DSP 5) according to the selected bit rate. .
[0046]
Here, the signal processing means includes a noise filter (post filter) for removing noise, and changes the frequency characteristic of the noise filter in accordance with the selected bit rate. Here, the coefficient of the first-order zero filter 25 is switched between 0 or b and -b.
[0047]
Further, the signal processing means includes compression coding means (DSP 5) for performing compression coding on the digital audio signal, and changes the operation clock frequency at the time of compression coding according to the selected bit rate.
[0048]
【The invention's effect】
According to the first, second, and third aspects of the present invention, there is no deterioration in sound quality even when signal processing is performed at different bit rates, and the supply current to the signal processing means can be used effectively. it can.
[Brief description of the drawings]
FIG. 1 is a block diagram of a digital audio recording / reproducing apparatus as an embodiment of the present invention.
FIG. 2 is a diagram showing a recording configuration of a semiconductor memory.
FIG. 3 is a flowchart for explaining the overall operation of the digital audio recording / reproducing apparatus.
4 is an operation flowchart for explaining details of a recording process in the flowchart of FIG. 3;
FIG. 5 is an operation flowchart for explaining details of reproduction processing in the flowchart of FIG. 3;
6 is an operation flowchart for explaining details of synthesis processing (step S55) of speech encoded data for one frame in the flowchart of FIG. 5;
FIG. 7 is a diagram illustrating a block configuration of a post filter.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Microphone, 2, 12 ... Amplifier (AMP), 3 ... Low-pass filter (PF), 4 ... Analog / digital (A / D) converter, 5 ... Digital signal processing part (DSP), X1 ... Normal bit Crystal at rate, X2 ... Crystal at half bit rate, MPX ... Multiplexer for crystal switching, 6 ... Control circuit, 7 ... Data input / output (I / O) buffer, 8 ... Main control circuit, 9 ... Address control Circuits, 10 ... Semiconductor memory, 11 ... Digital / analog (D / A) converter, 13 ... Speaker, 14 ... Drive circuit, 15 ... Display, 16 ... Main power switch, REC ... Record button, PL ... Playback button, ST ... Stop button, FF ... Fast forward button, REW ... Fast reverse button, I ... I mark button, E ... E mark button, RATE ... Bit rate cut For example switch.

Claims (1)

A digital audio recording / reproducing apparatus that reads out and reproduces a compression-encoded digital audio signal from a recording medium,
A compressed encoded digital audio signal read from the recording medium includes a post filter in which each of the filters is cascade-connected in the order of a first zero filter, a pole filter, and a second zero filter of the first order. Signal processing means for decoding;
Obtaining means for obtaining the bit rate selected by the bit rate selecting means when the digital audio signal is compression-encoded;
Changing means for changing the operation clock frequency of the signal processing means at the time of decoding according to the bit rate acquired by the bit rate information acquiring means;
Changing means for changing the coefficient of the second zero filter according to the bit rate acquired by the bit rate information acquiring means ;
Digital audio recording and reproducing apparatus characterized by comprising a.

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