JPS63271499A - Recording control circuit for voice recorder/reproducer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] (a) Industrial application field The present invention converts a recording signal obtained from a microphone into a digital signal and stores it in a semiconductor memory circuit, and also stores it in the semiconductor memory circuit during playback operation. The present invention relates to an audio recording and reproducing device that reads out a signal, converts it into an analog signal, and emits the sound through a speaker.

(B) Conventional Technology Cassette tape recorders, which use magnetic tape called cassette tape, have become popular as devices for recording and playing back audio. Devices such as cassette tape recorders that use magnetic tape as a means of recording audio signals have the advantage of being able to perform long recording operations, but they are difficult to miniaturize. Since it requires a mechanism to drive the magnetic tape, there is a problem in that the failure rate is high. As an improved device in this respect, the audio signal is converted into a digital signal and stored in a semiconductor memory, and during playback operation, the signal stored in the semiconductor memory is read out, converted into an analog signal, and then emitted through a speaker. A technology has been developed to do this, and examples of such technology include, for example,
There is one disclosed in Japanese Patent No. 2800.

(c) Problems to be Solved by the Invention The technology disclosed in the above-mentioned publication uses a semiconductor memory as a means for recording audio signals, which eliminates the need for a drive mechanism such as a tape recorder, and the device It has the advantage of being smaller and lowering the failure rate. However, such devices have the problem of accidentally erasing information that has been recorded, such as important audio. The present invention aims to provide an audio recording/playback device that is improved in this respect.

(d) Means for solving the problem The recording control circuit of the present invention has an ADPC control circuit during recording and playback operations.
An ADPCM analysis and synthesis circuit that performs speech analysis and speech synthesis using the M method, a semiconductor memory circuit that is removably attached to the main body, and writing of digital signals output from the ADPCM analysis and synthesis circuit into the semiconductor memory circuit. an address control circuit that controls the operation, read operation of signals stored in the semiconductor memory circuit, and write operation of index data to the semiconductor memory circuit; an operation switch for recording, an operation switch for playback, and an operation switch for high-speed forwarding; , a control circuit that controls the operations of the ADPCM analysis and synthesis circuit, the semiconductor memory circuit, and the address control circuit in response to switching of the stop operation switch and the erroneous erasure prevention operation switch.

(*) Effect The present invention writes memory use data indicating the maximum recording end position into the index memory section provided in the semiconductor memory circuit during recording operation, and when the operation switch for preventing accidental erasure is switched, the index write lock data for erasure prevention in the memory section for use, thereby preventing erasing operation from the beginning of the semiconductor memory to the maximum recording end position based on the memory use data when the lock data is written. This is how it was done.

(F) Embodiment The circuit shown in FIG. 1 is an embodiment of the present invention, FIG. 2 is a diagram for explaining the invention in detail, and FIG. 3 is an embodiment of a display. In the circuit shown in Fig. 1, (1) is a microphone that is in an operating state during recording operation and converts an acoustic signal into an electrical signal; (2) is a microphone (1) that converts an acoustic signal into an electrical signal;
) is input with a recording signal converted into an electrical signal and amplifies the signal; (3) is a recording amplifier circuit into which the recording signal amplified by the recording amplifier circuit (2) is input and which also amplifies the signal; This is a low-pass filter that blocks high-frequency signals. (4) is A- which converts the analog signal passed through the low-pass filter (3) into a digital signal.
The D converter (5) is an ADPCM that performs digital processing using a method called adaptive differential pulse code modulation.
The analysis and synthesis circuit (6) is the ADPCM analysis and synthesis circuit (
A D-A converter (7) converts the digital signal processed by the D-A converter (5) into an analog signal;
) into which the reproduced signal converted into an analog signal is input, and a low-pass filter that cuts off unnecessary high-frequency signals; (8) receives the reproduced signal that has passed through the low-pass filter (7), and amplifies the signal. The reproducing amplifier circuit (9) is a speaker to which the signal amplified by the reproducing amplifier circuit (8) is applied and emits the signal. (10) is the ADPCM analysis and synthesis circuit (5
), a control unit that controls the voice analysis operation and the voice synthesis operation;
(11) is a data I10 buffer circuit that controls the input/output operation of signals between an external circuit, which will be described later, and the control section (10) and ADPCM analysis/synthesis circuit (5). In such a circuit, an A-D converter (4), an ADPCM analysis and synthesis circuit (5), a D-A converter (6), and a control section (10).
The data I10 buffer γ circuit (11) constitutes an audio processing circuit, and this circuit is, for example, LSI'MSM6258. manufactured by Oki Electric Industry Co., Ltd. etc., and the details are omitted. (13) is a data I10 buffer circuit (11) that constitutes the audio processing circuit (tsubo).
A RAM (14) is a semiconductor memory that stores digital signals output from the RAM (14) and is equipped with an index memory section in which the usage position of the memory, that is, the consumption time is written as index data. This is an address control circuit that controls operations, read operations, and index data write operations, and is built into a card-type container (long) together with the RAM (13). The container (scale) is removably attached to the main body of the audio recording and reproducing device, and the RA is contained inside the container.
A backup battery (not shown) is incorporated to maintain the memory operation of M(13). (16) is a control circuit that controls the operations of the audio processing circuit (14), RAM (13), address control circuit (14), and the like. (17)
is a recording operation switch which can be suppressed and opened by a recording operation, and when the recording operation switch (17) is closed, the audio signal is stored in the RAM (13). (18) is a regeneration operation switch that is pressed and closed by the regeneration operation, and when the regeneration operation switch (18) is closed, the reproduction operation of identifying the signal stored in the RAM (13) is performed. It is done. (19), (20
) and (21) are a fast-forward operation switch, a rewind operation switch, and a stop operation switch, which are pressed and closed during a fast-forward operation, a rewind operation, and a stop operation. In such a configuration, the audio signal is completely stored in the RAM (13) by the recording operation, but at this time, the first data indicating the maximum recording end position of the memory, that is, the maximum usable position of the memory, is written to the index memory section, and the first data is written to the index memory section. 1 data is not erased until an erase operation is performed, and when a recording operation is performed beyond the maximum recording end position of the memory, new first data is written in the index memory section. Then, when a playback operation, fast forward operation, or rewind operation is performed, second data indicating the current position where the memory read operation is being performed is written to the index memory section provided in the RAM (13). It is configured as follows. (22) is a clock circuit; (23) is a display selection circuit that selects a clock display signal output from the clock circuit (22) and a display signal output from the control circuit (16); (24) is a drive circuit that drives the display device (25) based on the display signal selected by the display selection circuit (23). (26) is the indicator (25)
This is a display selection switch that selectively changes the content displayed on the display (25), and each time it is pressed and closed, the content displayed on the display (25) changes from clock display → counter display → remaining amount time display →
It has the effect of switching in the order of consumption time display → clock display. Reference numeral (27) denotes a correction/reset operation switch which functions as a time adjustment switch when the clock is displayed and also functions as a reset switch when the counter is displayed. (28) is an erasure operation switch, and the rewind operation switch (20)
By simultaneously suppressing RAM (13)
It is configured to erase signals stored in the memory while performing a rewinding operation. (29) is a battery built into the main body of the audio recording/playback device, and (30) is a power switch, which supplies power from the battery (29) to the control circuit (16>, etc.) when in the closed state. The clock circuit (22) and the circuit for displaying the time on the display (25) using the signal output from the clock circuit (22) include the power switch (30). The structure is such that power is supplied from the battery (29) regardless of whether the RAM (13) is opened or closed. (31) is designed to prevent the signals written in the RAM (13) from being erased by mistake. This is an operation switch to prevent accidental erasure, which is suppressed when the
When the operation switch (31) is pressed and closed, the control circuit (
16) and the address control circuit (14)
Lock data for erasure prevention is written into the index memory section provided in AM (13). When the RAM (13) in which the lock data for erasure prevention is written is attached to the main body of the audio recording/playback device and a recording operation is performed, the recording operation will start from the position based on the first data, that is, the maximum usage position of the memory. However, the recording operation is not performed from the beginning of the memory to the maximum usage position. Further, the above-mentioned erase operation is also configured not to be performed. The lock data erasing operation described above is performed using the accidental erasure prevention operation switch (31).
) is configured to be carried out by suppressing and developing.

The present invention is constructed as described above, and its operation will be explained next. If the sampling frequency in the audio processing circuit (ear) is 8 KHz and the number of quantization bits is 4, the bit rate will be 32 bits/second, and if the capacity of the RAM (13) is 4 Mbits, it will be stored for about 128 seconds. I can do it. In the present invention, the speech analysis and synthesis process by the ADPCM analysis and synthesis circuit (5) and the write operation to the RAM (13) accompanying the process are performed in phrases every 250 milliseconds. That is, the analysis and synthesis operation by the ADPCM analysis and synthesis circuit (5) is started by a start signal output from the control unit (10) incorporated in the audio processing circuit (TSUBO), and after 250 milliseconds, the control unit (10) The voice analysis and synthesis operation is stopped by the stop signal output from the voice analysis/synthesis operation. When writing a signal to the RAM (13), that is, during a recording operation, the above-mentioned 25
The signal analyzed and processed by the ADPCM analysis and synthesis circuit (5) for 0 milliseconds is sent to the data I10 buffer circuit (11).
The data is outputted to the RAM (13) through the address control circuit (14) and written into the RAM (13) with an address specified by the control operation of the address control circuit (14). In addition, RAM (
13) At the time of readout operation, that is, reproduction operation of the signal from
The signals synthesized by the ADPCM analysis and synthesis circuit (5) during the aforementioned 250 milliseconds are sent to the D-A converter (6).
) and converted to an analog signal. The control operation of the RAM (13) is performed by the audio processing circuit (14) and the address control circuit (14) in this manner.Next, each operation in this embodiment will be explained with reference to FIG.

When the user performs a recording operation after closing the power switch (30), power is supplied to the recording amplifier circuit (2) and the recording operation switch (17) is suppressed and opened, and the control circuit (16) starts recording. Control operations are performed for this purpose. A recording signal converted into an electric signal by a microphone (1) is input to a recording amplifier circuit (2), amplified, and then input to an audio processing circuit (1) through a low-pass filter (3). The recorded signal input to the audio processing circuit (processor) is converted into a digital signal by the A-D converter (4), and analyzed by the ADPCM analysis and synthesis circuit (5) for 250 milliseconds each. It is done.

Further, the signal analyzed and processed by the ADPCM analysis and synthesis circuit (5) is outputted to the RAM (13) through the data I10 buffer circuit (11) and is sent to the address control circuit (
14) is written into the RAM (13). Then, while the recording operation is being performed, the above-mentioned ADP
Analysis operation by CM analysis and synthesis circuit (5) and RAM (1
3) will be repeatedly performed until a stop operation is performed or the capacity of the RAM (13) is exhausted. FIG. 2(a) explains such a recording operation, and the signal that has been subjected to voice analysis processing using the ADPCM method is a phrase (a).

(B), (Ki...) and RAM (1
3). ADPCM at point (A) of each phrase
The analysis operation by the analysis and synthesis circuit (5) is started, and (B)
The analysis operation stops at this point, but the distance between (A) and (B) is 2.
It is 50 milliseconds. The recording operation is performed in this way, but each time the recording operation of each phrase is performed, the RAM (
First data indicating the maximum usage position of the memory is written into the index memory section provided in 13).

The first data will be retained together with the audio signal by the backup battery even if the container is removed from the main body of the audio recording/playback device. For example, the second
In figure (a), when phrases (a), (b), (c) and (d) are recorded, when the stop operation switch (21) is pressed and closed to cancel the recording operation, phrase (d) is recorded. First data, which is index data indicating the written position, is written into the index memory section. In such a state, when the power switch (30) is opened, the power supply to the control circuit (16) etc. is cut off, but the RAM (1
3) The signals and first data written in are stored and held by a backup battery. When the power switch (30) is closed after the RAM (13) in which the audio signal has been recorded is installed in the main body, the control circuit (13) is activated as described above.
6) etc., the first data written in the RAM (13>) is read out by the control circuit (16).Then, if a recording operation is performed in such a state, the above-mentioned recording will occur. Operation starts, but RAM<13
) is performed from the phrase (book) that is the next phrase after the above-mentioned recording end position, and the first data written in the index memory section is rewritten one after another. . The recording operation is performed in this way, but in order to prevent the signals stored in the RAM (13) from being erased, the operation switch for preventing accidental erasure (31) should be suppressed and opened when it is in the stopped state. . When the erroneous erasure prevention operation switch (31) is suppressed and opened, erasure prevention lock data is written into the index memory section provided in the RAM (13). Further, such lock data is held by a backup battery, similar to the index data indicating the use position described above. When the RAM (13) in which such lock data is written is installed in the main body of the audio recording/reproducing device, the lock data and first data indicating the maximum usable position of the memory are read out by the control circuit (16). When a recording operation is performed in such a state, as described above, the recording operation starts from the position based on the first data, that is, the maximum usage position of the memory. Then, if you perform a rewind operation, etc., which will be described later, and perform a recording operation when the current use position is between the start of the memory and the maximum use position of the memory, the recording operation will start, but the recording start position is as described above. The first
This will be done from the maximum usage location of memory, which is the location based on the data. Therefore, the audio signal that is completely stored between the beginning of the memory and the maximum usage position of the memory will not be erased. In order to perform a new recording operation between the beginning of the memory and the maximum usage position of the memory, the operation switch (31) for preventing erroneous erasing may be suppressed and opened. When the operation switch (31) is suppressed and opened, the lock data written in the RAM (13) is erased, so if the recording operation is performed after performing this operation, the above-mentioned recording operation will be transferred to the second data. This can be done from the current position of use based on .

The recording operation in this embodiment is performed as described above, but
Next, the playback operation will be explained. When the power switch (30) is closed after the RAM (13) is installed in the main body, power is supplied to the control circuit (16) etc.
6), the first data written in the RAM (13) is read. For example, by recording operation, as shown in Fig. 2(a).
When the RAM (13) in which audio signals from phrases (a) to (*) shown in the figure are written is installed, the control circuit (16)
), it is recognized that the audio signal has been written up to the position of the phrase (*), that is, the maximum usable position of the memory. In such a state, when a regeneration operation is performed, power is supplied to the regeneration amplifier circuit (8), the regeneration operation switch (18) is suppressed and opened, and the control circuit (16) performs a control operation for regeneration. In this case, since the second data indicating the current position is not written in the RAM (13), the reproduction operation will be performed from the beginning of the memory, that is, from phrase (A). RAM (1
3) is stored in the address control circuit (14).
) and the data I1
The signal is input to the ADPCM analysis and synthesis circuit (5) through the 0 buffer circuit (11). The ADPCM analysis and synthesis circuit (
The digital signals input to 5) are synthesized by the ADPCM analysis and synthesis circuit (5) for 250 milliseconds each and then applied to the DA converter (6) where they are converted into analog signals. The signal converted into an analog signal by the D-A converter (6) is passed through a low-pass filter (7).
The signal is inputted to the reproduction amplifier circuit (8) through the amplifier circuit, is amplified, and then emitted by the speaker (9). While this reproducing operation is being performed, second data indicating the current position is written to the index memory section provided in the RAM (13). For example, the phrase ((
), (b) and (c) are stopped when playback is incorrect.
When the switch (21) is suppressed and opened to cancel the playback operation, second data, which is index data indicating the position where the playback operation of the phrase (c) was performed, is written into the index memory section. In such a state, when the power switch (30) is opened, the power supply to the control circuit (16) etc. is cut off, but the audio signal, first data and second data written in the RAM (13) are , the memory is maintained by a backup battery.Such RAM (13)
When the power switch (30) is closed after the power is connected to the main body, power is supplied to the control circuit (16) etc. as described above, and the data is written to the RAM (13) by the control circuit (16). First data and second data are read.

If a playback operation is performed in such a state, the above-mentioned playback operation will be performed, but the readout operation of the audio signal from the RAM (13) will be based on the second data, that is, the phrase following phrase (c). (d) will be carried out. The playback operation starts like this, but the phrase (*
), since no audio signal has been recorded beyond that point, the playback operation is automatically canceled and becomes stopped, and the first data and second data become the same. FIG. 2(b) shows such a reproduction operation, in which the synthesis operation by the ADPCM analysis and synthesis circuit (5) starts at point (A) of each phrase, and the synthesis operation stops at point (B). , the period between (A) and (B) is 250 milliseconds.

The recording and reproducing operations are performed as described above, but the operations when fast forwarding and rewinding operations are performed will now be described. When the fast-forward operation is performed, the fast-forward operation switch (19) is closed and power is supplied to the reproduction amplifier circuit (8). When the fast-forward operation switch (19) is closed, the control circuit (16) performs a control operation to read signals from the RAM (13) and ADPCM.
The synthesis operation by the analysis and synthesis circuit (5) is performed as shown in FIG. 2(c). As is clear from the figure, the beginning parts (A) to (C) of each phrase that have been analyzed during the recording operation.
) The readout and synthesis processing operations are performed only during the period ( ) and the sound is emitted from the speaker (9). If the period between (A) and (C) is set to 174, or 62.5 milliseconds, between each phrase (A) and (B), it will be played back at four times the speed as compared to the playback operation described above. However, unlike a tape recorder, the frequency of the signal emitted from the speaker (9) does not become high, so the reproduced signal can be heard, albeit fragmentarily. The operation when performing the fast forward operation is performed in this way, but the operation when the rewind operation is performed will be explained next. When the rewinding operation is performed, the rewinding operation switch (20) is closed and power is supplied to the reproducing amplifier circuit (8). When the rewind operation switch (20) is closed, the control circuit (1
6), the signal reading operation from the RAM (13) and the synthesis operation by the ADPCM analysis and synthesis circuit (5) are performed as shown in FIG. 2(d). As is clear from the figure, only the beginning parts (A) to (C) of each phrase analyzed during the recording operation are read out and synthesized, and the sound is emitted from the speaker (9). The order of the phrases in which the reading operation is performed is in the opposite direction to the direction during the recording operation. This way (A) ~ (
C) If the interval is set to 1/4, or 62.5 milliseconds, between each phrase (A) and (B), rewinding and playback will be four times faster than during the playback operation described above. ,
Unlike a tape recorder, not only does the frequency of the signal emitted from the speaker (9) not become high, but the signal is emitted in the form of words, so the reproduced signal can be heard, albeit in fragments. By performing the aforementioned fast-forwarding and rewinding operations, it is possible to search for the signal recorded in the RAM (13), but when such operations are performed, the current position is indicated in the same way as during the aforementioned playback operation. The second data will be written to the index memory section. Therefore, when the fast forwarding or rewinding operation is performed again after returning to the stopped state, the fast forwarding or rewinding operation will be started from the position based on the second data described above. Further, when the fast forward operation reaches the memory maximum usage position, that is, the position specified by the first data, the fast forward operation is automatically canceled and the state is stopped. Then, by pressing and closing the stop operation switch (21) in the fast-forward operation state and the rewind operation state, it is possible to switch to the stop state.

Recording, playback, fast forwarding, and rewinding operations are performed as described above, but the erasing operation will be explained next. Since such an erasing operation is performed by suppressing and opening the rewinding operation switch (20) and the erasing operation switch (28), such erasure is performed after reproduction to the above-mentioned first data position, that is, the maximum memory usage position. If you perform an operation, the RAM
The audio signal stored in (13) can be deleted. Also, when such an erase operation is performed, the RAM (13
) The first data and second data written in the index memory section provided in ) will also be erased. In this way, the erasing operation is performed from the position of the first data, but it is also possible to perform the erasing operation from the middle of the memory, and in this case, the first data is not erased. Furthermore, if an erase operation is performed from the first data position and the erase operation is canceled in the middle, the RAM (1
3) In the index memory section provided in
data and second data will be written. In this way, the RA where lock data for erasure prevention is not written is
When using M(13), the erase operation can be performed, but the RAM(13) in which the lock data is written is
If 3) is used, no erase operation is performed.

Each operation in this embodiment is performed as described above, and next, the display operation will be explained with reference to FIG. 3. FIG. 3 shows an example in which a liquid crystal is used as the display (25). First, the clock display operation will be explained. Such display operation is
This is done by operating the display selection switch (26), and when the clock display state is entered, the display section (32) provided corresponding to the position where "clock" is printed becomes operational.

When the clock display becomes operational, the AM display section (33),
Afternoon display section (34), first display section (35) that displays the time
, a second display section (36) that displays minutes, and a colon section (37) that flashes every second are activated to display the time. In this state, a signal from the clock circuit (22) is input to the drive circuit (24) through the display selection circuit (23), and the time is displayed on the display (25) by the drive operation of the drive circuit (24). In addition, in this state, the time can be corrected by operating the correction/reset operation switch (27).In this way, the display operation as a clock is performed, but then other The display operation will be explained. When the recording operation and the playback operation are performed, the above-mentioned recording operation and playback operation are performed, and in such a state, the recording display section (38) and the playback display section (39) are in the operating state. to display that each operation is being performed.When the display selection switch (26) is operated during the recording and playback operation to display the counter, the counter and the printed position will be displayed. A display section (40) provided corresponding to
becomes operational. When the counter display operation is performed, the number display elements forming the first display section (35) and the second display section (36) display the count value. When the counter display is in the operating state, a count signal output from the control circuit (16) is input to the drive circuit (24) through the display selection circuit (23), and the count value is changed by the drive operation by the drive circuit (24). is displayed on the display (25). The count signal output from the control circuit (16) is
Write operations to the AM (13) and read operations from the RAM (13) are performed based on controllable address signals.

For example, during the recording operation, the address control circuit (1) is used when writing the phrase (A) and when writing the phrase (*).
If the count value is increased by one based on the address signal that can be controlled by 4), the count value that can be displayed on the display (25) will change every second. In other words, if the count signal output from the control circuit (16) is set to change every second, the display (25)
) will display the recording time. In addition, during the playback operation, the count value is increased by one based on the address signal controlled by the address control circuit (14) during the readout operation of the phrase (E) and the readout operation of the phrase (E). (
The count value displayed in 25) changes every second. That is, if the count signal output from the control circuit (16) is set to change every second, the count value displayed on the display (25) will indicate the playback time. As described above, the counter display operation is performed during the recording operation and the playback operation, but the counter display operation is similarly performed during the fast forwarding operation and the rewinding operation. That is, during the fast-forward operation, the operation shown in FIG. 2(c) is performed as described above, but the address control circuit (14) is ), the count value displayed on the display (25) becomes 1/1.
It will change every 4 seconds. That is, as mentioned above, the fast-forward operation is played back at four times the speed as compared to the recording and playback operations, but the count value displayed on the display (25) also increases at four times the speed, so it is in the fast-forward operation state. The counter display operation can be performed. Further, the counter display operation during the rewinding operation is performed in the same manner as during the fast forwarding operation, although the count value decreases, so a description thereof will be omitted.

The display operation as a counter is performed as described above, but next, the display operation of the remaining amount time will be explained. When the container (long) is attached to the main body of the audio recording and playback device, if you operate the display selection switch (26) to display the remaining amount, the remaining amount and the printed position will be displayed. The provided display section (41) becomes operational. In such a state, the display selection circuit (2) is switched from the control circuit (16).
The signal output to 3) is output based on the signal obtained from the RAM (13). That is, the remaining time is calculated by the control circuit (16) from the first data indicating the maximum memory usage position written in the RAM (13), the second data indicating the current usage position, and the capacity of the memory. A signal representing the remaining amount of time based on the data is sent to the display selection circuit (23
) is output. A signal representing the remaining amount of time is applied to a drive circuit (24) through a display selection circuit (23), and the remaining amount of time is displayed on a display (25) by a driving operation by the drive circuit (24). In this case, the first display section (35) and the second display section (36) constituting the display device (25) display the second data, that is, the remaining amount of time based on the current usage position, and the third display section (42 ) and the fourth display section (43) display the first data, that is, the remaining time based on the memory maximum usage position.

Further, when such a display operation is being performed, the minute display sections (44) and (45) and the second display section (45) provided on the lower right side of the first display section (35) and the third display section (42) 36) and the seconds display section (46>(47>) provided on the lower right side of the fourth display section (43) are in operation to make the user aware that minutes and seconds are being displayed. .and,
When recording, playback, fast-forwarding, or rewinding operations are performed in such a display state, the second display section (36) and the first display display the remaining amount of time based on the current use position in response to the operation. The value of the third display section (35) changes, but the value of the third display section (42), which displays the remaining amount of time based on the maximum memory usage position, changes.
) and the values in the fourth display section (43) do not change until the first data is rewritten by the recording or erasing operation described above.

The operation of displaying the remaining amount time is performed as described above, but next, the operation of displaying the consumed time will be explained.

When the container (15) is attached to the main body of the audio recording/playback device, when the display selection switch is operated to display the consumption time, the display selection switch is displayed corresponding to the consumption amount and the printed position. The display section (48) becomes operational.

In this state, the signal output from the control circuit (16) to the display selection circuit (23) is output based on the signal obtained from the RAM (13).

That is, the control circuit (16) reads first data indicating the maximum memory usage position written in the RAM (13) and second data indicating the current usage position, and consumes the memory based on the read signal. A signal representing time is output to a display selection circuit (23). A signal representing the time consumed is applied to the drive circuit (24) through the display selection circuit (23), and the time consumed is displayed on the display (25) by the drive operation by the drive circuit (24). In this case as well, the first display section (35) forming the display device (25)
, the second display section (36), the minute display section (44) and the second display section (46) display the time consumed at the current use position, and the third display section (42) and fourth display section (43).
, the minutes display section (45), and the seconds display section (47), the time consumed at the maximum memory usage position is displayed. In addition, when recording, playback, fast forwarding, and rewinding operations are performed in this display state, a second display section (3
6) and the first display part (35) change, but the values of the third display part (42>) and the fourth display part (43), which display the consumption time based on the maximum memory usage position, are as described above. The first data does not change until it is rewritten by a recording or erasing operation.

As described above, the clock display operation, counter display operation, remaining amount time display operation, and consumption time display operation are performed by the display device (25).Next, the operation when the above-mentioned erasing operation is performed will be explained. Rewind operation switch (20
) and the erasing operation switch (28) are suppressed and opened to enter the erasing operation state, but when in such a state, the display section (
49) flashes to indicate that the erase operation is being performed. In addition, when in such a state, the first display section (35
), second display section (36), third display section (42) and fourth display section
The value on the display section (43) changes in response to the rewinding operation for erasing.

Each display operation by the display device (25) is performed as described above.Next, the display operation of lock data will be explained.

If the accidental erasure prevention operation switch (31) is pressed and closed while the container is attached to the main body of the audio recording/playback device, the index data provided in the RAM (13) will be deleted as described above. Lock data for erasure prevention is written to the memory section. RA of such lock data
When a write operation to M (13) is performed, the control circuit (
16) outputs a signal indicating that the lock data write operation has been performed. The display signal is input to the drive circuit (24) regardless of the above-described selection operation of the display selection circuit (23), and is provided in the display (25) by the drive operation of the drive circuit (24). The lock display section (50) becomes operational. Therefore, the user can recognize that the lock data has been written to the RAM (13) by pressing the erroneous erasure prevention operation switch (31) and that the recording operation cannot be performed. . Further, when the lock display section (50) is in the operating state, the operation switch (3) for preventing erroneous erasure is activated.
When 1) is pressed and closed, the lock data written in R'A M (13) is erased and the lock display section (50) becomes inactive. Therefore, the user can recognize that the lock data deletion operation has been performed and that the recording operation can be performed. In this way, the operation is performed when the RAM (13) is installed in the main body, but next, the R
The operation when A M (13) is attached to the main body will be explained. After installing such a RAM (13) into the main body, when the power switch (30) is closed, the control circuit (16)
) reads out the lock data, and as a result, the control circuit (16) outputs a signal to display the lock data, and as a result, the lock display section (50) provided on the display (25) becomes in the operating state. Become. The display operation by the lock display unit (50) is performed regardless of whether it is in the clock display state, counter display state, remaining time display state, or consumption time display state, so the user must turn the power switch (30) on. ), it is possible to recognize that a RAM (13) is installed in which a signal that must not be erased is recorded. Therefore, the user operates the display selection switch (26) to set the display (25) to R.
The remaining time of the AM (13) is displayed, and if the remaining time is short, the RAM (13) is converted and a recording operation is performed.

As described above, the display (25) displays the remaining time, consumed time, and whether or not the erasing operation is possible based on the index data and lock data obtained from the RAM (13). Recording mistakes can be prevented by performing recording and playback operations while checking the displayed content.

Note that the recording and playback time can be increased by increasing the capacity of the RAM (<13) or by setting the sampling frequency low. In addition, the analysis and synthesis time by the ADPCM analysis and synthesis circuit (5) during recording and playback operations was 250 ms,
Although the synthesis time during fast-forwarding and rewinding operations is set to 62.5 milliseconds, the time is not limited. Although the count value is set to change every second during the counter display operation, it is possible to change the count value in various ways, such as changing every 0.5 seconds. Further, although the display device (25) is provided with a display section to indicate that the recording operation and the playback operation are in progress, it is also possible to provide a display section or the like to indicate that fast forwarding or rewinding operation is being performed. Furthermore, although the erasing operation is performed while rewinding, it is also possible to perform the erasing operation while fast forwarding.

(g) Effects of the Invention The recording control circuit of the present invention converts a recording signal obtained from a microphone into a digital signal, stores it in a semiconductor memory circuit that is detachable from the main body, and also stores it in a semiconductor memory circuit that is detachable from the main body. In an audio recording/playback device configured to read out a stored signal, convert it to an analog signal, and emit the sound through a speaker, the maximum recording end is stored in the index memory section provided in the semiconductor memory circuit during recording operation. In addition to writing memory use data indicating the position, lock data for preventing erasure is written in the index memory section when the operation switch for preventing accidental erasure is switched, and the semiconductor memory circuit in which the lock data is written is installed. When the semiconductor memory is in use, the erase operation is prevented from the beginning of the semiconductor memory to the maximum recording end position based on the memory usage data, that is, the erase operation is prevented only from the recorded portion of the semiconductor memory circuit. , so you can record to the rest of the memory. Therefore, the present invention has the great effect of being able to solve the problem of accidentally erasing important information recorded in a semiconductor memory circuit, and also making it possible to effectively use the memory capacity.

[Brief explanation of the drawing]

The circuit shown in FIG. 1 is an embodiment of the present invention, FIG. 2 is a diagram for explaining the invention in detail, and FIG. 3 is an embodiment of a display. Explanation of main drawing numbers (1)... Microphone, (2)... Recording amplifier circuit, (5)... ADPCM analysis and synthesis circuit, (8)
... reproduction amplifier circuit, (9) ... speaker,
(婬)...Audio processing circuit, (13)...RAM,
(14)...address control circuit, (16)...
・Control circuit, (22)...Clock circuit, (25)・
...Indicator, (29)...Battery, (30)...
Power switch, (31)... Operation switch for preventing accidental erasure.

Claims (1)

[Claims] (1) Convert the recording signal obtained from the microphone into a digital signal and store it in a semiconductor memory circuit that is removably attached to the main body. During playback operation, the signal stored in the semiconductor memory circuit is read out and then converted into an analog signal. In an audio recording/playback device configured to convert the ADPCM into sound and emit the sound from a speaker, during recording and playback operations, the ADPCM
an ADPCM analysis and synthesis circuit that performs speech analysis and speech synthesis according to a method, a write operation of a digital signal output from the ADPCM analysis and synthesis circuit to the semiconductor memory circuit, and a read operation of the signal stored in the semiconductor memory circuit. and an address control circuit for controlling the writing operation of index data to the semiconductor memory circuit, and for switching an operation switch for recording, an operation switch for playback, an operation switch for high-speed forwarding, an operation switch for stopping, and an operation switch for preventing accidental erasure. A control circuit correspondingly controls the operations of the ADPCM analysis and synthesis circuit, the semiconductor memory circuit, and the address control circuit, and indicates the maximum recording end position in an index memory section provided in the semiconductor memory circuit during recording operation. When memory use data is written and the operation switch for preventing accidental erasure is switched, lock data for erasure prevention is written in the index memory section, and thus, when the lock data is written, the semiconductor memory is 1. A recording control circuit for a voice recording/playback device, characterized in that erasing operations are prevented from the beginning to the maximum recording end position based on the memory usage data.