JPS6325931A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the variation of the characteristics of an element due to charged particles, ultraviolet rays, etc. by forming a screening film screening charged particles, ultraviolet rays, etc. onto the element on a semiconductor substrate. CONSTITUTION:Screening films 17 screening charged particles, ultraviolet rays, etc. are shaped onto elements on a semiconductor substrate 1. The screening films 17 consisting of a polycrystalline silicon film are formed onto resistance elements R for constituting a flip-flop circuit in a memory cell for a device such as a static RAM through insulating films 16. The screening film 17 may also be shaped by a high melting-point metallic film composed of Mo, W, Ta, Ti, etc. besides the polycrystalline silicon film, or may also be formed by these silicide films. Accordingly, the increase of trap levels in the resistance elements R by ultraviolet rays generated at the time of plasma etching for shaping data lines DL and ashing for removing a mask used for the plasma etching can be prevented, thus reducing the variation of the electrical characteristics of the elements.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and is particularly applicable to technology for preventing or reducing changes in device characteristics caused by charged particles, ultraviolet rays, etc. It is related to effective technology. .

[Conventional technology]

A memory cell of a static RAM (hereinafter referred to as S-RAM) consists of a flip-flop circuit and a selection element. A technology related to a 5-RAM in which the load element of the flip-flop circuit is constructed from a polycrystalline silicon film is disclosed in Japanese Patent Application No. 59-18.
It is described in No. 0533.

[Problem that the invention seeks to solve]

The inventor of the present invention discovered the first problem as a result of studying the resistance element made of the polycrystalline silicon film.

When patterning an aluminum film formed on a semiconductor substrate to form a data line by plasma etching, for example, or by plasma ashing or ashing using oxygen excited by ultraviolet rays, etc., a mask made of a resist film used for patterning. When the polycrystalline silicon film is removed by (hereinafter simply referred to as asher), a trap level is generated in the resistance element made of the polycrystalline silicon film. Therefore, electrical characteristics such as standby leakage current and threshold value of the resistance element vary.

An object of the present invention is to reduce changes in device characteristics caused by charged particles, ultraviolet rays, and the like.

The above and other objects and novel features of the present invention will become clear from the description in Kikiri J1 and the accompanying drawings.

[Means for solving interlayer points]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a shielding film that shields charged particles, ultraviolet rays, and the like is provided on an element on a semiconductor substrate.

[Effect]

According to the above-described means, the device is not exposed to charged particles, ultraviolet rays, or the like, so that fluctuations in the electrical characteristics of the device due to the formation of trap levels can be reduced.

[Example ■]

First, the structure of the memory cell of this embodiment will be explained, and then the manufacturing method will be explained.

Ru. Fig. 1 is a plan view of the memory cell with the data line of 5-RAM removed, Fig. 2 is a plan view of the entire memory cell including the data line, and Fig. 3 is a section line A-A in Fig. 2. FIG. Note that insulating films other than the field insulating film are not shown in FIGS. 1 and 2 in order to make the configuration of the memory cell easier to see.

In FIGS. 1 to 3, reference numeral 1 denotes a semiconductor substrate made of p-type single-crystal silicon, and a field isolation film 2 made of a silicon oxide film and an Il film 2 are provided on its surface so as to define a memory cell pattern. ing.

A P-type channel stopper region 3 is provided below the field insulating film 2.

One memory cell consists of two N-channel M I 5FE
A flip-flop circuit consisting of a drive MISFET (driving MISFET) and two resistance elements, and an N-channel MISFET as a selection element at each of its two output terminals (nodes).
It is configured by providing an S FET.

The driving M I S FET has a gate insulating film 4 made of a silicon oxide film formed by oxidizing the surface of a semiconductor substrate l, and a gate electrode 5 made of a first layer polycrystalline silicon film, for example.
．． A square semiconductor region 6. which forms part of the source and drain regions and is provided at the end on the channel region side. sauce,
Furthermore, the diagonal semiconductor region 6 is provided below the edge portion of the gate pole 5. Therefore, in FIGS. 1 and 2, the lead line indicating the n-type semiconductor region 6 indicates the vicinity of the edge of the gate electrode 5. The n - type semiconductor region 6 is defined by a sidewall spacer 9 made of a silicon oxide film and provided on the side surface of the gate electrode 5 . The gate electrode 5 is arranged so that it can form a cross-connection of a flip-flop circuit.
Other driving MIS extending over the field insulating film 2
It is connected to the drain region of the FET through an opening 13 formed by selectively removing the gate insulation 11!4. gate f
l! On the surface of the semiconductor substrate 1 to which the pole 5 is connected, an n4 type semiconductor region 8 is provided by diffusion from the gate electrode 5. This n-type semiconductor region 8 constitutes a part of the drain region. As shown in Figure 1, the drive MIS
In a predetermined part of the source region of the FET.

For example, the conductive layer made of the first layer of polycrystalline silicon film, 11
1 is an opening 13 formed by selectively removing the gate 8 [4].
connected through. A circuit ground potential Vss, for example 0.sup., is applied to the source region through the conductive layer 11. On the surface of the semiconductor substrate 1 to which the conductive layer 11 is connected, an n° type semiconductor region 8 is provided by diffusion therefrom.

The resistance element R, which is the load element of the flip-flop circuit, is
The layout is such that it overlaps with the gate voltage pi5 of each driving M I S FET.

The resistance element R is made of, for example, a second layer polycrystalline silicon film. between the resistance element R and the gate ff electrode 5.

For example, insulation made of silicon oxide film by CVD
It is insulated. One end of the resistive element is connected to the upper surface of the gate electrode 5 and the surface of the drain region through the connecting hole 5 by a conductive layer 812 made of a polycrystalline silicon film formed integrally therewith. The other end is connected to a power supply potential Vcc, for example 5V, through the conductive layer 12.

The selection MISFET includes a gate insulating film 4, for example, a polycrystalline silicon film of the first layer, a gate electrode 10 formed integrally with the word AWL, and an n-type semiconductor region 6.
．． It is composed of an n3 type semiconductor region 7. Two choices M
Selection of one of the I S FETs M I S FE
The source or drain region of T is connected to one driving M I S
It is formed integrally with the drain region of the FET. The source and drain regions of the other selection MISFET are the source of the driving MISFET.

Separated from the drain region.

In this embodiment, for example, a third
A shielding film 17 made of a polycrystalline silicon film is provided. The shield [17] is for shielding high-energy light such as ultraviolet rays that is irradiated onto the resistance element R during the manufacturing process of the semiconductor integrated circuit device. Therefore, the shielding film 17 has a size that allows the resistance element R to be hidden thereunder.

Since the resistance element R is arranged in such a layout that it overlaps the gate electrode 5, the gate electrode 5 is also hidden under the shielding film 17. Further, the gate insulating film 4 under the gate electrode 5 is also hidden under the shielding film 17. This means that the shielding film 17 protects not only the resistive element R but also the gate electrode 5 and the gate insulating film 4 from irradiation with ultraviolet rays. The shielding film 17, the resistance element R, and the conductive layer 12 are insulated by an insulating film 16 made of, for example, a silicon oxide film formed by CVD. The shielding film 17 is covered with an insulating film 18 made of, for example, a phosphosilicate glass (PSG) film produced by CVD. DL and n1 are data lines made of an aluminum film formed by sputtering, for example, and the connection hole 19
It is connected through the n-type semiconductor region 7, which is part of the source or drain region of the selected M I S FET.

Next, the one-piece manufacturing method will be explained.

4 to 7 are cross-sectional views of the same portion as FIG. 3 of the memory cell in the manufacturing process.

As shown in FIG. 4, a gate insulating film 4 is formed on a semiconductor substrate 1 made of P-type single crystal silicon. Opening 13, gate electrode 5
．． 10 (word line WL), conductive layer 11, n' type semiconductor region 8, i type semiconductor region 6, side wall spacer 9.
An n-type semiconductor region 7 is formed. Furthermore, for example, CVD
A contact hole 15 is formed by selectively removing the insulating film 14 on the drain region of the drive MISFET. After this, the conductive layer 12
In order to form the resistor element R, a polycrystalline silicon film is formed on the entire surface of the semiconductor substrate 1 by, for example, CVD,
This is patterned into a pattern in which the conductive layer 12 and the resistive element R are combined by etching using a mask made of a resist film (not shown). Note that in this step, impurities for lowering the resistance are not introduced into the portion that will become the conductive layer 12.The polycrystalline silicon film 12 is inserted into the predetermined upper end of the gate ff1wAs and the surface of the semiconductor substrate 1 through the connection hole 15. is connected to.

Next, as shown in FIG. 5, an insulating film 16 made of a silicon oxide film is formed over the entire surface of the semiconductor substrate 1 by, for example, CVD so as to cover the polycrystalline silicon film 12.

Next, as shown in FIG. 6, a polycrystalline silicon film is formed on the entire surface of the semiconductor substrate 1 by, for example, CVD, and this is patterned by plasma etching using a mask made of a resist film to form a shielding film 17. Form. The pattern of the shielding film 17 is such that the resistance element R is hidden therebelow, as shown in FIG. The mask made of the resist film used for etching is removed using an asher after buttering.

Next, as shown in FIG. 5, using the shielding film 17 as a mask, an n-type impurity such as As is introduced into a predetermined portion of the polycrystalline silicon film 12 by ion implantation to lower the resistance thereof. Note that the resist mask used when the polycrystalline silicon film 17 is subjected to butterfly jigging may be used as the mask for As introduction. Therefore, the portion into which the n-type impurity is not introduced becomes the resistance element R. Resistance element R is defined by shielding film 17.

Even before the shielding film is formed, the trap level increases if it is damaged by plasma. However, since the shielding film 17 is made of a polycrystalline silicon film, that is, a film that can be subjected to high-temperature heat treatment, N2 gas or Ar gas is used to activate As introduced by ion implantation.
Annealing at about 50° C. can be performed. This annealing can eliminate the trap level.

Next, as shown in FIG. 3, an absolute film 41B made of a PSG film is formed on the entire surface of the semiconductor substrate 1 by, for example, CVD. Next, the selection M I S at the time of reading
Insulating film 1B on the drain region of FET, 16.14. The silicon oxide film 4 is removed to form a contact hole 19. 6 Next, an aluminum film is formed on the entire surface of the semiconductor substrate 1 by, for example, sputtering, and this is plasma etched using a mask made of a resist film (not shown). The data lines DL and DL are formed by patterning. Ultraviolet light is generated during this plasma etching.

Since this light is shielded by the shielding film 17, the resistor element R is not irradiated with this light, that is, the generation of a trap level in the low resistance element R can be prevented.

Furthermore, the mask made of the resist film used to form the data lines DL and DL is removed by ashing.

During this ashing, ultraviolet rays are generated, but since they are blocked by the shielding film 17, the resistance element R is not irradiated. That is, an increase in the trap level of the resistance element R can be prevented.

After forming data IDL and DL, data line DL.

Annealing is performed to improve the connection between the masonry and the n-type semiconductor region 7, which is the source or drain region, but since the data DL and DL are made of aluminum film, this must occur at a low temperature of about 450°C. In other words, it is difficult to eliminate the trap level in the resistance element R by this annealing.

As explained above, by providing the shielding film 17 on the resistive element R, the plasma etching for forming the data lines DL and DL and the removal of the mask made of the resist film used for this etching are performed. Since it is possible to prevent an increase in the trap level in the resistance element R due to the ultraviolet rays generated during ashing, it is possible to improve the electrical characteristics of the resistance element R, such as standby leak current and threshold value.

The shielding film 17 is not limited to a polycrystalline silicon film, but may be a film of a high melting point metal such as Mo, W, Ta, or Ti, or a silicide film thereof. Further, the shielding film 17 may have a thickness that is sufficient to absorb ultraviolet rays generated during patterning of the data lines DL, DL and when assuring the resist film.

Gate electrode 5 of drive MISFET, gate voltage Vi10 of selection MISFET and word line WL, drive MISFET
The circuit ground potential VsS, for example Ov, is applied to the source region of the FET.
The conductivity NJ11 for applying is 1Mo, W, Ta, T
It may be formed by a high melting point metal film such as i or a silicide film of the high melting point metal.

[Example ■]

8 is a cross-sectional view of the memory cell shown in FIG. 9 taken along line A--A, and FIG. 9 is a plan view of the memory cell in Example (2).

Note that insulating films other than the field insulating film 2 are not shown in FIG. 9 in order to make the configuration of the memory cell easier to see.

In Example 2, a shielding film 17 is provided over the entire area of the memory cell array to prevent characteristic fluctuations of the resistive element R due to charged particles and ultraviolet rays. Figure 9 is.

In order to make it easier to see the structure of the memory cell, a portion of the shield 1B17 is not shown.

As shown in FIGS. 8 and 9, the shielding film 17 is.

The connection hole 19 for connecting the data LADL, DL to the source or drain region of the selected MISFET is removed to form an opening 20. Although not shown in the figure, the shielding film 17 is set to the same potential as the semiconductor substrate 1, that is, the circuit ground potential Vss, for example, Ov. An insulating film 21 (side wall spacer) made of a silicon oxide film is formed on the side surface of the opening 20 by, for example, CVD. The insulating film 21 is for insulating the data lines DL, DL and the shielding film 17 made of a conductive film.

Since the shielding film 17 covers the entire area of the memory cell array, not only the resistance element R but also the gate insulating film 4. It is possible to prevent the trap level from increasing due to charged particles or ultraviolet rays in the gate electrode 5.10 (word line WL).

Next, the manufacturing method will be explained.

10 and 11 are cross-sectional views of the same part as FIG. 8 of the memory cell in the manufacturing process.As shown in FIG. 10, the 2Mth polycrystalline silicon film is A conductive layer 12 and a resistive element R are formed. In this embodiment, before forming the insulating film 16, an n-type impurity such as H1i4 (As) is added to lower the resistance of the conductive layer 12.
) ion implantation. A mask made of a resist film is used for the ion implantation. This mask is removed after ion implantation. Next, an insulating film 1 made of a silicon oxide film is deposited on the entire surface of the semiconductor substrate 1 by, for example, CvD.
form 6.

Next, a connection hole for connecting the shielding film 17 to the ground potential of the circuit is formed, for example, around the memory cell array.

Next, as shown in FIG. 11, a shielding film 17 made of, for example, a polycrystalline silicon film is formed over the entire surface of the semiconductor substrate 1 by, for example, CVD. The polycrystalline silicon film that is the shielding film 17 is doped with an n-type impurity, such as arsenic (A
s) is introduced by ion implantation.

Next, as shown in FIG. 8, an insulating film 18 made of a PSG film is formed over the entire surface of the semiconductor substrate 1 by, for example, CVD. Next, the insulating rS18, the shielding film 17, and the insulating film 1 on the drain region of the selected MISFET during readout.
6. Forming the connection hole 19 by removing 14 and gate insulation #4 Next, a silicon oxide film is formed on the entire surface of the semiconductor substrate 1 by, for example, CVD, and this is etched into the semiconductor substrate by reactive ion etching. 1 is etched until the top surface of the opening 19 is exposed, and an insulating film (
8 Next, an aluminum film that will become the data lines DL and DL is formed on the entire surface of the semiconductor substrate 1 by sputtering, for example. 0 Next, this aluminum film is formed using a mask made of a resist film. Data line D is patterned by plasma etching.
L.

Form DL. The mask made of the resist film used for etching is removed by ashing. Although charged particles and ultraviolet rays are generated during the plasma etching and ashering, since the resistive element R is covered with the shielding film 17, it is not irradiated with the charged particles and ultraviolet rays. In other words, the state in the resistive element R is This can be prevented from increasing.

This means that 1 selection M r S FET, drive MISFE
Gate insulating film for forming T4. Gate electrode 5.1
The same applies to 0 or word fiWL.

As explained above, according to this embodiment, it is possible to prevent variations in the electrical characteristics of not only the resistive element R but also the gate insulating film 4 and the gate electrode 5.10 (word 1WL) due to charged particles or ultraviolet irradiation. Can be done.

Note that the shielding film 17 is not limited to a polycrystalline silicon film, and may be composed of a film of a high melting point metal such as MOlW, Ta, or Ti, or a silicide film of the high melting point metal.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, by providing the shielding Ff1 film on the semiconductor substrate, the elements on the semiconductor substrate are not irradiated with charged particles or ultraviolet rays, so that the electrical characteristics of the elements can be improved.

[Brief explanation of the drawing]

Figure 1 is an example! 2 is a plan view of the 5-RAM memory cell excluding the data line.
FIG. 3 is a plan view of a memory cell including a data line. FIG. 3 is a sectional view taken along the line A--A in FIG. 2. 4 to 7 are cross-sectional views of the same portion as FIG. 3 of the memory cell in the manufacturing process. 8 is a cross-sectional view of the memory cell taken along the line AA in FIG. 9, and FIG. 9 is a plan view of the memory cell of Example H. 10 to 11 are cross-sectional views of the same portion as FIG. 8 of the memory cell in the manufacturing process. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Field insulating film, 3...
...Channel stopper region, 4...Gate insulating film, 5
, 10... Gate electrode, 6.7, 8... Semiconductor region, 9... Side wall spacer, 11.12...
conductive layer. 13.15.19... Connection hole, 14.16.18...
- Insulating film, 17... Shielding film (for example, polycrystalline silicon film), 20... Opening, 21... Insulating film (side wall spacer), DL, DL... Data line, WL...
Word figure 1

Claims (1)

[Scope of Claims] 1. A semiconductor integrated circuit device, characterized in that a shielding film for shielding charged particles, ultraviolet rays, etc. is provided on an element on a semiconductor substrate. 2. The semiconductor integrated circuit device is a static RAM, and the shielding film is provided via an insulating film over a resistance element for configuring a flip-flop circuit of a memory cell, and the length of the resistance element is A semiconductor integrated circuit device according to claim 1, characterized in that: 3. The shielding film is provided in an upper layer of a resistive element constituting a flip-flop circuit of a memory cell of a static RAM, and covers the entire memory cell array area. semiconductor integrated circuit devices. 4. The semiconductor integrated circuit device according to claim 1, wherein the shielding film is made of a conductive film having a higher melting point than an aluminum film.