JPH065816A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To enhance data holding characteristics of a memory cell by reducing a density of a boundary level in an isolation part of diffused layers of transistors for constituting the cell. CONSTITUTION:An element active region 13 formed of a diffused layer 14 of a transistor 32 is continuously formed in a direction perpendicular to an extending direction of a W-polyside layer 23 of a word line, and the layer 14 are isolated by a P-N junction between a pair of adjacent non-selected word lines 23b in its perpendicular direction. A transistor 33 having the line 23b as a gate electrode is formed in a depletion type. Thus, a density of a boundary level in the isolation part is lower than that of the case that the layers 14 are isolated by an SiO2 film, etc., formed by a selectively oxidizing method.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device called a DRAM having a folded bit line structure.

[0002]

7 and 8 show a folded bit line structure D.
7 shows a pattern of an element active region in a conventional example of a RAM. In this conventional example, the surface of the Si substrate 11 is
Si for element isolation after being oxidized by OCOS (selective oxidation) method
Although the O ₂ film 12 is formed, the element active region 13 surrounded by the SiO ₂ film 12 has the extending direction of the word line (not shown) as the short side direction and is perpendicular to the extending direction. To form an isolated rectangle whose long side is the same direction
The O ₂ film 12 is patterned.

The diffusion layer 14 of the transistor constituting the memory cell is formed in the element active region 13. However, since the element active region 13 is an isolated rectangle as described above, the diffusion layers 14 may be arranged in any direction. Also in the SiO ₂ film 12
Are separated by.

[0004]

However, the boundary portion 1 between the end portion of the element active region 13 in the long side direction and the SiO ₂ film 12 is formed.
5, stress is likely to be concentrated during oxidation by the LOCOS method,
At the boundary portion 15, the density of interface states is high. This interface state becomes the generation / recombination center 16, and the diffusion layer 14 near room temperature
Is a dominant cause of junction leakage between the Si substrate 11 and the Si substrate 11. For this reason, in the conventional example shown in FIGS. 7 and 8, the data retention characteristic of the memory cell was not sufficient.

[0005]

According to another aspect of the semiconductor memory device of the present invention, a memory cell is composed of a transistor 32 and a capacitor 44, and a pair of the word lines 23 extends in the extending direction of the word line 23. The memory cells arranged in the current direction are sequentially formed with a selected word line portion 23a and a non-selected word line portion 23b, and are paired adjacent to each other in the direction perpendicular to the extending direction. In the semiconductor memory device in which the word lines 23 are sequentially the selected word line portion 23a and the non-selected word line portion 23b with respect to the memory cells arranged in the right angle direction, The element active region 13 in which the diffusion layer 14 is formed is continuously formed in the perpendicular direction, and the pair of the non-selection wires adjacent to each other in the perpendicular direction. Between lead wire portion 23b, the diffusion layer 14
It is characterized in that they are separated by a PN junction.

According to another aspect of the semiconductor memory device of the present invention, the transistor 33 having the non-selected word line portion 23b as a gate electrode is used.
Is a depletion type.

[0007]

According to the semiconductor memory device of claim 1, the word line 23 is used.
Since the diffusion layers 14 of the transistor 32 are separated by the PN junction between the pair of unselected word line portions 23b that are adjacent to each other in the direction perpendicular to the extending direction, the oxidation formed by the selective oxidation method. The interface state density in the separation portion is lower than that in the case where the separation is performed by the film 12 or the like.

According to another aspect of the semiconductor memory device of the present invention, since the semiconductor substrate 11 under the non-selected word line portion 23b is originally in the inversion state, the depletion state which occurs during the transition from the accumulation state to the inversion state does not occur. No depletion layer is formed on the semiconductor substrate 11 below the selected word line portion 23b.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. The same components as those in the conventional example shown in FIGS. 7 and 8 are designated by the same reference numerals.

1 and 5 show this embodiment. In order to manufacture this embodiment like this, S is formed by the LOCOS method or the like.
The element isolation SiO ₂ film 12 is formed on the surface of the i-substrate 11, and the element active region 13 surrounded by the SiO ₂ film 12 is formed. The pattern of the element active region 13 is shown in FIG. Stripe as shown.

Next, as shown in FIG. 2, a SiO ₂ film 17 as a sacrificial oxide film having a film thickness of several hundred nm is formed on the element active region 13.
A resist 18 is formed on the surface of the Si substrate 11 and is patterned on the Si substrate 11 so as to cover only a region of the element active region 13 through which a selected word line portion to be formed later and a region in the vicinity thereof. Then, using the resist 18 and the SiO ₂ film 12 as a mask, the concentration of N-type impurities 21 such as As ⁺ , Phos ⁺ , Sb ^+, etc. on the surface of the element active region 13 is 10 ¹⁵ to 10 ¹⁸ cm ^−3. SiO ₂ film 1
Ion implantation is performed through 7.

As a result, as shown in FIG. 3, the diffusion layer 14 is formed by the impurities 21. After that, HF etc.
After removing the O ₂ film 17 and forming a SiO ₂ film 22 as a gate oxide film on the surface of the element active region 13 by thermal oxidation,
As shown in FIGS. 3 and 5, in the memory cell array portion, the gate electrode to be the word line is formed of the W-polycide film 23 or the like.

Of the W-polycide film 23, the portion passing through the region covered with the resist 18 becomes the gate electrode of the access transistor, that is, the selected word line portion 23a for operating the memory cell. . Also, W
-A portion of the polycide film 23 that passes through a region that is not covered with the resist 18 becomes an unselected word line portion 23b that does not participate in the operation of the memory cell.

Thereafter, as shown in FIGS. 3 and 5, a resist 24 which covers only the region between the non-selected word line portions 23b in the element active region 13 is patterned, and the resist 24 is patterned.
And the W-polycide film 23 and the SiO ₂ film 12 are masked, and N-type impurities 25 such as Phos ⁺ , As ⁺ , Sb ⁺
Is ion-implanted at a dose of about 10 ¹² to 10 ¹⁴ cm ⁻² .

As a result, as shown in FIG. 4, the diffusion layer 14 and the impurities 25 already formed form the diffusion layer 14 in the element active region 13 except under the selected word line portion 23a. After that, a SiO ₂ film 26 having a film thickness of several hundreds nm is deposited by the CVD method, and RIE is performed on the entire surface of the SiO ₂ film 26 so that the side wall formed of the SiO ₂ film 26 is W-.
It is formed on the side portion of the polycide film 23. And this Si
The O ₂ film 26 is used as an LDD spacer, and a transistor (not shown) in the peripheral circuit section has an LDD structure.

After that, as shown in FIGS.
The resist 27 having a pattern opposite to that of 4 is patterned, that is, the resist 27 which opens only the region between the non-selected word line portions 23b in the element active region 13. Then, the resist 27, the W-polycide film 23, and the Si
By masking the O ₂ films 12 and 26, ions of P type impurities 28 such as B ⁺ and BF ₂ ⁺ are formed so that the concentration on the surface of the element active region 13 becomes about 10 ¹⁷ to 10 ¹⁹ cm ^−3. inject. If necessary, the ion implantation may be performed while changing the acceleration energy of the impurity 28.

As a result, the conductivity type of the region between the non-selected word line portions 23b in the element active region 13 is inverted, and
As shown in, the P-type diffusion layer 31 is formed in this region. As is apparent from FIG. 1, the selected word line section 2
The transistor 32 having 3a as a gate electrode is an enhancement type, and the transistor 33 having a non-selected word line portion 23b as a gate electrode is a depletion type.

After that, a PSG film having a film thickness of several hundreds nm, an SiO ₂ film containing no impurities, or an S film having a film thickness of several tens nm is used.
The interlayer insulating film 34 is formed of an iN film or a film combining these. Then, a polycrystalline Si film 35 containing impurities is formed on the entire surface, and an opening 36 is formed in a contact portion between the storage node electrode of the capacitor and the diffusion layer 14 in the polycrystalline Si film 35.

After that, a SiO ₂ film 37 is formed on the entire surface,
The entire surface of the SiO ₂ film 37 and the interlayer insulating film 34 are etched back, and the side wall made of the SiO ₂ film 37 is opened 36.
A contact hole 38 which is formed on the inner peripheral surface of and reaches the diffusion layer 14 while being surrounded by the side wall is opened in the interlayer insulating film 34 and the like. Therefore, the contact hole 38 is reduced in size in a self-aligned manner with respect to the opening 36 by the width of the side wall made of the SiO ₂ film 37.

Moreover, the opening 36 has a width W due to misalignment.
-When approaching the polycide film 23, the W-polycide film 23
Since the side wall made of the SiO ₂ film 37 becomes high and wide due to the step due to, the contact hole 38 does not approach the W-polycide film 23 as much as the opening 36, and the contact hole 38 and the W-polycide film 23 are not formed. The interlayer breakdown voltage between them is secured. That is, the opening of the contact hole 38 using the side wall made of the SiO ₂ film 37 has the effect of reducing the misalignment or the effect of increasing the alignment margin.

Thereafter, a polycrystalline Si film 41 containing impurities is formed on the entire surface so as to contact the diffusion layer 14 through the contact hole 38, and the polycrystalline Si films 41 and 35 are processed into a pattern of the storage node electrode. . Then, the dielectric film 42
And a polycrystalline Si film 43 containing impurities are sequentially formed on the entire surface, and these are processed into a pattern of a plate electrode to complete a capacitor 44.

After that, the interlayer insulating film 45 is formed of a PSG film or a BPSG film having a film thickness of several hundreds of nm, or a film combining these films. Then, a bit line contact hole 46 reaching the diffusion layer 14 is opened in the interlayer insulating film 45 or the like, and a bit line is formed by the W-polycide film 47 or the like.
Then, the DRAM is completed through a conventionally known process such as formation of Al wiring (not shown).

By the way, in the above embodiment, it is possible to omit the ion implantation of the impurity 21. However, if the impurity 21 is not ion-implanted, the transistor 33 becomes an enhancement type, and a depletion layer is formed in the element active region 13 under the W-polycide film 23 during the transition from the accumulation state to the inversion state. The depletion layer increases the junction leak between the diffusion layer 14 and the Si substrate 11, and deteriorates the data retention characteristic of the memory cell.

Further, in this embodiment, as is clear from FIG. 1, the P-type diffusion layer 31 does not overlap the W-polycide film 23, but impurities 28 for forming this diffusion layer 31 are not included. If the amount is too large, as shown in FIG.
It overlaps with the polycide film 23. As a result, a gate control diode is formed, and the diffusion layer 14 and the Si substrate 1 are formed.
The junction leak between the memory cell and the memory cell 1 increases, and the data retention characteristic of the memory cell also deteriorates.

On the other hand, as described above, the opening of the contact hole 38 using the side wall made of the SiO ₂ film 37 has the effect of reducing the misalignment or the effect of increasing the alignment margin. The W-polycide film 23 is the SiO ₂ film 12.
In the upper high position, this effect is less. However, as apparent from FIGS. 1 and 5, in the present embodiment, the non-selected word line portion 23b is also located on the element active region 13,
The above effect can be utilized to the maximum extent, and the memory cell area can be reduced.

[0026]

In the semiconductor memory device according to the first aspect of the present invention, since the density of the interface state in the separation portion between the diffusion layers of the transistors constituting the memory cell is low, the density of generation / recombination centers in this separation portion is low. Is also low. Therefore, the junction leak between the diffusion layer of the transistor and the semiconductor substrate via the generation / recombination center is small, and the data retention characteristic of the memory cell is excellent.

In the semiconductor memory device of the second aspect, since the depletion layer is not formed on the semiconductor substrate below the non-selected word line portion,
The junction leakage between the diffusion layer of the transistor and the semiconductor substrate is further reduced, and the data retention characteristic of the memory cell is further excellent.

[Brief description of drawings]

1 shows an embodiment of the invention of the present application, which is indicated by I in FIG.
It is a sectional side view in the position which follows the -I line.

FIG. 2 is a side cross-sectional view showing the initial process for manufacturing an example, taken at the same position as in FIG.

FIG. 3 is a side sectional view showing a step that follows FIG.

FIG. 4 is a side sectional view showing a step that follows FIG.

FIG. 5 is a plan view of an example.

FIG. 6 is a side sectional view for explaining a problem that may occur in one embodiment.

FIG. 7 is a plan view of an element active region in a conventional example of the present invention.

8 is a side sectional view taken along a line VIII-VIII in FIG.

[Explanation of symbols]

 13 Device Active Region 14 Diffusion Layer 23 W-Polycide Film 23a Selected Word Line Section 23b Non-Selected Word Line Section 32 Transistor 33 Transistor 44 Capacitor

Claims (2)

[Claims] 1. A memory cell is composed of a transistor and a capacitor, and a pair of the word lines in the extending direction of the word line are sequentially selected word with respect to the memory cells arranged in the extending direction. Line portions and non-selected word line portions, and a pair of the word lines that are adjacent to each other in the direction orthogonal to the extending direction are both aligned with the memory cells arranged in the orthogonal direction. In a semiconductor memory device in which the selected word line portion and the non-selected word line portion are sequentially formed, an element active region in which a diffusion layer of the transistor is formed is continuously formed in the orthogonal direction. The semiconductor memory device, wherein the diffusion layers are separated from each other by a PN junction between a pair of the unselected word line portions that are adjacent to each other in the orthogonal direction. 2. The semiconductor memory device according to claim 1, wherein the transistor using the non-selected word line portion as a gate electrode is a depletion type.