KR940008229B1 - Nonvolatile process compatible with a digital and analog double level metal mos process - Google Patents

Abstract

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Description

Nonvolatile Process and Nonvolatile Transistor Components Compatible with Digital and Analog Dual Level Metal MOS Processes

Those skilled in the art will readily understand the advantages and features of the present invention by reading the following detailed description in conjunction with the drawings.

1 is a schematic cross-sectional view illustrating the floating gate transistor construction of the present invention with a precision metal gate capacitor that can be effectively manufactured by the disclosed process for fabricating the transistor construction.

2A-2G are schematic cross-sectional views that aid in an understanding of the process for fabricating the floating gate transistor construction and precision capacitor of FIG.

Background of the Invention

FIELD OF THE INVENTION The present invention relates generally to metal-oxide-semiconductor (MOS) floating gate transistor constructions, and in particular to single or dual level metal floating gate transistor constructions including metal programming gates, polysilicon access gates and polysilicon floating gates. A process for manufacturing a floating gate transistor is disclosed.

Floating gate transistors are intended to remain "on" or "off" without any bias power to the circuit. Therefore, the floating gate transistor is used as a nonvolatile memory element so that data is stored by appropriately programming the floating gate transistor in an on or off state. Each state of the floating gate transistor is sensed by an appropriate read circuit. Floating gate IGFETs are described in the physics of semiconductor devices, Sze, Johe Wiley & Sons, pages 550-555, 1969.

Known floating gate constructions include polysilicon floating gates and polysilicon control / access gates partially overlying and extending beyond the floating gate. These gates are separated by a "interpoly" oxide layer. Typically, the floating gate is formed by a first polysilicon layer process and the control / access gate is formed by a second polysilicon layer process, which is also used to form certain standard transistor gates (ie, non-floating). do.

Consideration for the above-mentioned constructs is that oxides between polysilicon will leak if hot oxide processing is not used. However, this high temperature oxide processing has been shown to degrade the tunnel oxide below the floating gate. Therefore, conservation and sustainability must be complementary.

Another consideration to be taken of the above-mentioned constructs is that the fabrication processing typically used determines the standard gate oxide thickness depending on the thickness required for the oxide between polysilicones. It will be difficult to use more advanced processes for thin film gate oxides.

Other known constructs are similar to the constructs described above except that the gate function is reversed. That is, the first polysilicon layer gate is used as the control / access gate and the second polysilicon layer gate is used as the floating gate. This construction effectively permits tunnel oxide formation after oxide formation between polysilicones, thus allowing the formation of high quality polysilicon oxides without damaging the tunnel oxides. In addition, this construction allows for the simultaneous formation of oxides between the polysilicon and the oxide under the floating gate (distinguishable from the tunnel oxide), thus providing a consistent capacitive coupling between the control / access gate and the floating gate.

However, the capacitive coupling coefficient is reduced because the control / access gate cannot capacitively couple the control / access gate in the second polylayer floating gate configuration to the floating gate region that must be extended. In addition, since the size of the control / access gate in the channel region is inevitably reduced and narrow, the control / access gate can have a high resistance which makes the access time slower.

Another thing to consider with the above known construction is that the control gate is also used as an access gate, resulting in loss of charge on the floating gate after repeating the read operation and reducing the preservation of the floating gate construction. This configuration also allows the "read" state of the floating gate transistor to have various different states of "on" instead of "off" or "on". Accurate reference devices are required to be able to read several different "on" states, which complicates the design.

Summary of the Invention

Therefore, it is an advantage of the present invention to provide a floating gate transistor construction having improved capacitive coupling and improved oxide between the floating gate and the access gate.

Another advantage is to provide a floating gate transistor construction that prevents significant changes in the floating gate potential during read operations.

It is another advantage to provide floating gate transistor constructions with reduced access time.

The above-described advantages and features and other advantages and features are in part based on the semiconductor substrate, the access gate dielectrically separated from the substrate, and the first portion and dielectrically separated from the substrate by the floating gate oxide and tunnel oxide regions. Provided by a floating gate transistor construction of the present invention that includes a floating gate that lies in place and has a second portion that is genetically isolated from an access gate. The metal control gate overlies the floating gate and is dielectrically separated from the floating gate.

Other features of the present invention include forming a gate oxide layer over a semiconductor substrate, forming an access gate over the gate oxide layer, and forming an oxide layer between polysilicon over the access gate and floating over the laterally adjacent substrate oxide. A process for fabricating a floating gate transistor comprising forming a gate oxide layer. After the tunnel oxide region is formed in the floating gate oxide layer, a floating gate is formed over the oxide between the polysilicon, the floating gate oxide, and the tunnel oxide. An oxide layer is formed over the floating gate and a metal control gate is formed over it.

details

In the following detailed description and various forms of the drawings, like elements are denoted by like reference numerals.

Referring to FIG. 1, a partial cross section of an integrated circuit 10 including a silicon substrate 11 is schematically illustrated, which may be of any suitable conductivity type and will be described as N type in this specification. An illustrative example is shown with the non-volatile N ^- channel floating gate transistor 20 and the precision capacitor 30 formed in each of the P ^- wells 12, 14 in the N ^- substrate 11. To facilitate understanding, the floating gate transistor construction and the precision capacitor construction will be described separately.

The nonvolatile floating gate transistor 20 includes an N ⁺ source and drain region 13 formed in the device region of the P ^- well 12. The field oxide region 15 separates and surrounds the device region of the P ^- well 12. A polysilicon access gate 17 is formed over an access gate oxide layer 19 disposed on the P well. It should also be noted that the gate of the standard (ie non-floating) transistor is formed along the polysilicon access gate 17.

The floating gate transistor 20 further includes a polysilicon floating gate 21 comprising two floating gate portions 21a, 21b of different heights connected by the transition portion 21c. The floating gate portion 21a is disposed on the floating gate oxide layer 23 formed on the substrate 11, and the floating gate portion 21b is disposed at least partially on the polysilicon access gate 17 so as to at least partially lie therein. 17) on the oxide layer 25 between the polysilicon formed above. In addition, the transition portion 21c is separated from the access gate 17 by the oxide layer 25 between polysilicon.

The thin film tunnel oxide region 24 is formed in the floating gate oxide layer 23, and the downwardly extending portion of the floating gate portion 21a is disposed above the tunnel oxide region 24.

The oxide layer 27 may be formed on the polysilicon floating gate 21, and the selective nitride layer 29 may be formed on the oxide layer 27. The metal control gate 31 is disposed above the floating gate 21, for example, is disposed on the nitride layer 29 if the nitride layer 29 is used, the oxide layer (if the nitride layer 29 is not used) 27). The metal control gate 31 is formed as part of the patterned first metallization layer 32 formed on the deposited phosphorus doped phase (PVX) layer 34 having an opening towards the metal gate 31. The metal gate 31 is patterned with a second metallization layer 33 patterned by a conductor 35 disposed in a via formed in the oxide layer 37 between the metals separating the first and second patterned metallization layers. Is conductively connected. Alternatively, the interconnection of the metal gates 31 can be made in the first metallization layer 32.

Referring to precision capacitor 30, it includes N ⁺ region 111 in P ⁻ well 14 between field oxide regions 15. The N ⁺ region 111 is well formed simultaneously with the source and drain regions 13 of the floating gate transistor 20 and includes a lower plate of the precision capacitor 30. Another plate of capacitor 30 is a metal capacitor gate 113 that is dielectrically separated from the N ⁺ region by capacitor oxide layer 115. The metal capacitor gate is formed through the openings in the PVX layer 34 as part of the patterned first metallization layer 32 and is patterned by the conductors 117 formed in the vias in the oxide layer 37 between the metals. It is electrically conductively connected to the metallization layer 33.

The nonvolatile floating gate transistor 20 and the precision capacitor 30 described above may be formed according to the following process steps.

Gate oxide and field oxide regions 15 are suitably formed in a suitably doped substrate. For example, a first cover layer of polysilicon is formed on the exposed oxide surface by standard low pressure chemical vapor deposition. The deposited polysilicon layer is doped with a suitable impurity such as phosphorus, for example, according to known techniques by ion implantation or diffusion. The gates of the standard transistors as well as the polysilicon access gates 17 are determined by a suitably patterned photoresist mask, and unnecessary portions of the polysilicon layer are etched, for example, by polysilicon plasma etching. The exposed gate oxide is then etched, for example by oxide plasma etching, to expose the unprotected surfaces of the P ^- wells 12, 14. After the photoresist, the resulting composition is shown in Figure 2a.

Oxide 25 and floating gate oxide 23 between polysilicones are formed, for example, by oxidation at relatively high temperatures of at least 1050 in dry oxygen providing low leakage oxide. This resulting construct is shown in Figure 2b.

The region 24 of the tunnel oxide is defined by a suitably patterned photoresist layer, and the floating gate oxide exposed by the photoresist pattern is etched into the substrate 11 by, for example, plasma etching or wet etching. do. Then, the thin film tunnel oxide 24 is increased.

A second cover layer of polysilicon is formed on the exposed oxide surface, for example, by canoned low pressure chemical vapor deposition. The deposited polysilicon layer is doped with a suitable impurity such as phosphorus upon ion implantation. The doped polysilicon layer is then oxidized to form an oxide thin film layer.

If a nitride layer 29 over the polysilicon floating gate 21 is used, the silicon nitride cover layer is deposited on the oxide thin film layer, for example, by standard low pressure chemical vapor deposition.

The floating gate region is then defined by a suitably patterned photoresist mask, and the oxide on the nitride layer and the second polysilicon layer (if a nitride layer is used), for example, by nitride / oxide plasma etching. Is etched. The second polysilicon layer is then etched, for example by polysilicon plasma etching, to form the floating gate 21. The resulting etched construct is shown in FIG. 2C.

Then, the source and drain regions 13 of the floating gate transistor and the lower capacitor plate 111 of the precision capacitor are formed, for example, by phosphorus ion implantation in accordance with known techniques, the structure of which is shown in FIG. Is shown.

An overlying layer of phosphorus doped oxide (PVX) is deposited on the exposed surface of the wafer, for example by low pressure low temperature chemical vapor deposition. The opening for contact, the metal control gate 31 of the floating gate transistor, and the metal gate 113 of the precision capacitor are defined by a suitably patterned photomask, which, for example, causes the metal control gate 31 to It can be patterned to overlap the associated polysilicon floating gate 21. That is, the metal control gate 31 is not limited to being on the nitride region 29. If there is an opening in the metal control gate 31 that overlaps the associated polysilicon floating gate 21, certain edge portions of the floating gate 21 may be exposed when etched. The wafer is then etched to make this opening, for example, by plasma etching. In particular, PVX is etched up to the silicon substrate in the precision capacitor region, the nitride layer 29, and the portion of the polysilicon access gate 17 that is not protected by nitride in the floating gate transistor region. The resulting composition after removal of the photoresist is shown schematically in FIG. 2E.

The etched PVX is recycled and at the same time the capacitor oxide 115 of the given precision capacitor is increased by oxidation during the recycle. In addition, some exposed edges of the polysilicon floating gate 21 and exposed regions of the access gate 17 are oxidized during recycling. This resulting construction is schematically illustrated in FIG. 2F.

After the PVX recycle, the metallization cover layer is applied to the recycled etched PVX 34 by, for example, sputtering. The desired pattern of the first metallization layer 32 comprising the metal control gate 31 of the floating gate transistor and the metal gate 113 of the precision capacitor is determined by a suitably patterned photoresist mask formed on the metallization layer. The metal control gate 31 can be patterned to overlap the associated floating gate 21 to provide maximum capacitive coupling. The metallization layer is then subjected to photoresist mask and etching processing to remove unnecessary metallization. The resulting composition after removal of the photoresist is shown schematically in FIG. 2G.

After etching the first metallization layer, an oxide capping layer is deposited on the patterned first metallization layer to form an intermetallic oxide layer 37. If desired, the position of the via opening, including via openings for the metal control gate 31 formed in the first metallization layer 32, is determined by a suitably patterned photoresist formed on the oxide layer. The oxide layer is etched by, for example, an oxide plasma.

The metallization cover layer is then applied by sputtering, for example, to form the second metallization layer 33 and to fill the via openings. The second metallization layer 33 is patterned according to photoresist masking and etching, and prevents possible interference due to source and drain lines formed in the first metallization layer 32 in some memory implementations. And interconnection of (31). This resulting construct after removal of the photoresist is shown schematically in FIG.

It should be noted that the interconnection of the metal control gate 31 may also be provided in the first metallization layer 32. In addition, the device described above can be implemented by single metal layer processing.

The above-described, but it is on the N ⁺ channel devices, components and processes disclosed is P ^- can be implemented in a channel device, and N ⁺ channel device and a P ^- It may be implemented with a CMOS process, including both the channel device is It will be easily understood by those skilled in the art.

Although what has been described above relates to the formation of floating gate transistors in the transistor region, it should be noted that polysilicon plates or two-terminal capacitors having metal and polysilicon plates may be formed. In particular, the polysilicon access gates and associated "floating gates" (which do not float in this configuration) form capacitors with suitable via openings and connections in the first metallization layer. The metal gate and associated "floating gate" may also form a capacitor with appropriate via openings and connections to the "floating gate" in the first and second metallization layers. Such metal / polysilicon capacitors provide high capacitance per unit area.

In addition, metal contacts may be provided to other “floating gates”, for example, to form specialized transistors that include reference transistors, if desired.

The description of non-volatile floating gate transistors with low-leakage polysilicon oxides and floating gate oxides with optimized tunnel oxides has been described above, which provides reliable retention and high duration. In addition, the thickness of the standard (non-floating) gate oxide does not depend on the thickness of the oxide and the floating gate oxide between polysilicon, which makes it possible to use improved thinner non-floating gate oxide processing. The disclosed floating gate transistor also provides a high coupling coefficient from the control gate to the floating gate, which allows for a programmable low voltage.

Separate control gates and access gates are effectively provided, which eliminates the "read disturb" effect (i.e. loss of charge stored on the floating gate as a result of many read operations) and (e.g., without a reference cell Allows a simpler detection technique. In particular, the metal gate can be grounded during a read operation in which the access gate is pulsed high, which is a significant voltage change on the floating gate due to the high capacitance between the metal control gate and the floating gate, and access associated with the floating gate. This prevents significant voltage changes on the floating gate due to the relatively low capacitance between the gates. Preventing significant voltage changes on the floating gate prevents the "read disturb" effect.

In addition, separate control gates and access gates are effectively used for programming. In particular, the metal control gate can be connected to each polysilicon access gate during programming to increase the capacitance between the floating gate and an effective control gate including the metal gate and the access gate. Higher capacitance provides higher coupling coefficients, which require lower programming voltages.

It should be noted that for certain memory array applications, the control gate and access gate of each row are permanently connected and the disclosed floating gate transistor configuration provides reduced access time. In this application, the access gates of a given row include a continuous polysilicon strip extending across all floating gate transistors in that row, and the metal control gates of that row are connected together by metal. The connection between the metal gate and the polysilicon access gate can be made, for example, by standard contacts located along the row between the access gate associated with the metal gate. This construction effectively lowers the resistance of the polysilicon in locations, making the maximum series resistance much lower, and reducing access time. Additionally, this configuration is best suited for the lowest programming voltage due to the high capacitive coupling resulting from having both gates next to the floating gate. However, it should be noted that the advantages of separate control gates and access gates are not valid for this configuration.

The disclosed process provides compatible nonvolatile and analog device processing and can be compatible with existing CMOS processes. This process allows the production of better tunnel oxide and insulating oxide between the polysilicon layers.

While descriptions and examples of specific embodiments of the present invention have been described above, various modifications and changes may be made by those skilled in the art without departing from the scope and principles of the invention as defined by the following claims.

Claims (7)

A semiconductor substrate, an access gate dielectrically separated from the substrate, a first portion dielectrically separated from the substrate by an oxide layer comprising a tunnel oxide region, and at least partially overlying and accessing the access gate dielectrically from the access gate A floating gate having a second portion separated, and a metal control gate overlying and floating from the floating gate. The nonvolatile transistor construction of claim 1, wherein the access gate comprises a polysilicon layer. 3. The non-volatile transistor construction of claim 2 wherein the floating gate comprises a polysilicon layer. The non-volatile transistor construction of claim 1 wherein the metal gate is patterned in the first metallization layer. 5. The nonvolatile transistor construction of claim 4, further comprising a second metallization layer, wherein the metal gate is conductively connected to the second metallization layer. A semiconductor substrate, a polysilicon access gate dielectrically separated from the substrate, a first portion dielectrically separated from the substrate by a floating gate oxide layer and a tunnel oxide region, and at least partially overlying the polysilicon access gate And a polysilicon floating gate having a second portion dielectrically isolated from the silicon access, and a metal control gate overlying and floating from the floating gate. Forming a gate oxide layer on the semiconductor substrate, forming a polysilicon access gate on the gate oxide layer, forming an oxide layer between polysilicon on the polysilicon access gate, and laterally adjacent the gate oxide layer And forming a floating gate oxide layer having a tunnel oxide region, forming a polysilicon floating gate having a first portion disposed over the floating gate oxide and a second portion disposed over the oxide between the polysilicon, the floating Forming an insulating layer over the gate, and forming a metal gate over the oxide layer over the floating gate.