JPS63258071A - Manufacture of thin-film transistor - Google Patents

Manufacture of thin-film transistor

Info

Publication number
JPS63258071A
JPS63258071A JP9274187A JP9274187A JPS63258071A JP S63258071 A JPS63258071 A JP S63258071A JP 9274187 A JP9274187 A JP 9274187A JP 9274187 A JP9274187 A JP 9274187A JP S63258071 A JPS63258071 A JP S63258071A
Authority
JP
Japan
Prior art keywords
material layer
gate material
layer
gate
film transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9274187A
Other languages
Japanese (ja)
Inventor
Satoru Ito
悟 伊藤
Masaki Yasunaga
安永 正記
Kazuya Okabe
岡部 和弥
Yasuhiko Kasama
泰彦 笠間
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alps Alpine Co Ltd
Original Assignee
Alps Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alps Electric Co Ltd filed Critical Alps Electric Co Ltd
Priority to JP9274187A priority Critical patent/JPS63258071A/en
Publication of JPS63258071A publication Critical patent/JPS63258071A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To improve the characteristics of a thin-film transistor and thereby enhance the yield and reliability of products incorporating thin-film transistors by a method wherein a gate material layer is formed on a substrate, reverse spattering is accomplished for the conversion of the surface into a damaged layer, and then etching is accomplished for the construction of a gate electrode. CONSTITUTION:A gate material layer 8 is formed on a substrate 2, the gate material layer 8 is exposed to reverse spattering for the formation of a damaged layer 9, and the gate material layer 8 is subjected to etching for the construction of a gate electrode 3. For example, on a glass substrate 2, a gate material layer 8 is formed of molybdenum or the like by spattering. A process follows wherein the upper layer of the gate material layer 8 is subjected to reverse spattering for the formation of a damaged layer 9. Next, the gate material layer 8 is subjected to etching for the construction of a gate electrode 3 of a prescribed geometry, when the resultant gate electrode 3 is provided with a roundish surface. An insulating film 4, semiconductor film 5, source electrode 6, and drain electrode 7 are formed for the completion of a thin-film transistor 1.

Description

【発明の詳細な説明】 「産業上の利用分野」 この発明は、アクティブマトリックス液晶表示素子のス
イッチング素子などに\用いられる薄膜トランジスタ(
TPT)の製造方法に関する。
Detailed Description of the Invention "Field of Industrial Application" This invention is directed to thin film transistors used in switching elements of active matrix liquid crystal display devices.
TPT).

「従来の技術」 従来より、アクティブマトリックス液晶表示素子のスイ
ッチング素子などに用いられる薄膜トランジスタとして
、例えば第5図に示すような構造のものが知られている
。この図において符号lは薄膜トランジスタである。こ
の薄膜トランジスタlは、ガラス基板2上に形成された
ゲート電極3と、上記ガラス基板2上にゲート電極3を
覆って形成された絶縁膜4と、該絶縁膜4上に形成され
た半導体膜5と、該半導体膜5上に形成されたソース電
極6およびドレイン電極7とからなっている。
"Prior Art" Conventionally, a thin film transistor having a structure as shown in FIG. 5, for example, has been known as a thin film transistor used as a switching element of an active matrix liquid crystal display element. In this figure, reference numeral 1 indicates a thin film transistor. This thin film transistor l includes a gate electrode 3 formed on a glass substrate 2, an insulating film 4 formed on the glass substrate 2 to cover the gate electrode 3, and a semiconductor film 5 formed on the insulating film 4. and a source electrode 6 and a drain electrode 7 formed on the semiconductor film 5.

ところで、このような構造の薄膜トランジスタlを作製
するには、まずガラス基板2上にスパッタリングによっ
てモリブデンなどからなるゲート材層を形成し、次に該
ゲート材層にフォトリソグラフィー・エツチングなどの
エツチングを施してゲートバス(図示せず)と共に所定
形状のゲート電極3を形成し、次いでガラス基板2上に
上記ゲート電極3を覆って絶縁膜4を被覆形成し、その
後この絶縁、膜4上に半導体膜5を被覆形成し、さらに
この半導体膜S上にソース電極6およびドレイン?!i
t&7をそれぞれ形成して薄膜トランジスタ1を得る。
By the way, in order to fabricate a thin film transistor l having such a structure, first a gate material layer made of molybdenum or the like is formed on the glass substrate 2 by sputtering, and then the gate material layer is subjected to etching such as photolithography or etching. A gate electrode 3 having a predetermined shape is formed together with a gate bus (not shown), and then an insulating film 4 is formed on the glass substrate 2 to cover the gate electrode 3, and then a semiconductor film is formed on the insulating film 4. A source electrode 6 and a drain electrode 6 are further formed on this semiconductor film S. ! i
T&7 are formed respectively to obtain the thin film transistor 1.

「発明が解決しようとする問題点」 しかしながら、上記薄膜トランジスタlにあっては、ゲ
ート電極4がフォトグラフィー・エツチングなどのエツ
チングによって形成されるため、その断面形状が第5図
に示すように角張った状態に形成され、したがってゲー
ト電極3の隅部3a。
``Problems to be Solved by the Invention'' However, in the thin film transistor 1 described above, since the gate electrode 4 is formed by etching such as photography etching, its cross-sectional shape is angular as shown in FIG. corner 3a of the gate electrode 3.

3a上の絶縁膜4a、4aの膜厚が薄くなり、また上記
隅部3a、3aに電界が集中することから、隅部3a、
3a上の絶縁膜4a、4aでの電流の漏れが大きくなる
という問題があった。また、このように電流の漏れの大
きい薄膜l・ランジスタが液晶表示素子などに用いられ
ると、この液晶表示素子などが正常に作動せず、よって
液晶表示素子など上記薄膜トランジスタを用いた製品の
歩留りが低下するという問題があった。
The thickness of the insulating films 4a, 4a on the corners 3a becomes thinner, and the electric field concentrates on the corners 3a, 3a.
There was a problem in that current leakage in the insulating films 4a, 4a on the insulating films 3a increased. Furthermore, if thin film transistors with large current leakage are used in liquid crystal display devices, etc., the liquid crystal display devices will not operate properly, and this will reduce the yield of products using the thin film transistors, such as liquid crystal display devices. There was a problem with the decline.

この発明は上記事情に鑑みてなされたもので、その目的
とするところは、薄膜トランジスタの特性の向上を図り
、さらにこの薄膜トランジスタを用いた製品の歩留りと
信頼性の向上を図ることにある。
The present invention has been made in view of the above circumstances, and its purpose is to improve the characteristics of thin film transistors and further improve the yield and reliability of products using these thin film transistors.

「問題点を解決するための手段」 この発明は上記問題点を解決するため、基板にゲート材
層を形成し、次いでこのゲート材層に逆スパッタリング
を施して表面にダメージ層を形成し、その後肢ゲート材
層にフォトリソグラフィー・エツチングなどのエツチン
グを施してゲート電極を形成し、薄膜トランジスタを形
成するようにしノこものである。
"Means for Solving the Problems" In order to solve the above problems, the present invention forms a gate material layer on a substrate, then performs reverse sputtering on this gate material layer to form a damaged layer on the surface, and then A thin film transistor is formed by performing etching such as photolithography and etching on the limb gate material layer to form a gate electrode.

したがってこの発明の薄膜トランジスタの製造方法では
、ゲート材層に逆スパッタリングを施すことによりゲー
ト材層上層部に機械的に脆弱なダメージ層を形成するこ
とができ、よってその後、エツチングを施してゲート電
極を形成した際に、このゲート電極の上層部が脆弱なダ
メージ層からなっているためその隅部の角が自然に削れ
、これによりその上層部が丸みを帯びた角の無いゲート
電極を形成することができる。
Therefore, in the method for manufacturing a thin film transistor of the present invention, a mechanically weak damaged layer can be formed in the upper layer of the gate material layer by performing reverse sputtering on the gate material layer, and then etching is performed to form the gate electrode. When formed, the upper layer of this gate electrode consists of a fragile damaged layer, so its corners are naturally shaved off, thereby forming a gate electrode with no rounded corners. Can be done.

「実施例」 以下、第1図ないし第4図を利用してこの発明の薄膜ト
ランジスタの製造方法の一例を詳しく説明する。なお、
これらの図において第5図に示す構成要素と同一の要素
には同一の符号を付す。
"Example" Hereinafter, an example of the method for manufacturing a thin film transistor of the present invention will be described in detail using FIGS. 1 to 4. In addition,
In these figures, the same elements as those shown in FIG. 5 are given the same reference numerals.

まず、第1図に示すようにガラス基板2上に、スパッタ
リングによってモリブデン、タンタル、アルミニウム、
クロム、チタンなどからなるゲート材層8を形成する。
First, as shown in FIG. 1, molybdenum, tantalum, aluminum, etc. are sputtered onto a glass substrate 2.
A gate material layer 8 made of chromium, titanium, etc. is formed.

次に、このゲート材層8の上に第2図に示すように逆ス
パッタリングを施して、ゲート材層8上層部にダメージ
層9を形成する。ここで逆スパッタリングとは、ゲート
材層8自身をターゲツト材とし、これに第2図中矢印で
示すように加速したイオンを衝突させ、ゲート材層8上
層部から該ゲート材層8を構成する原子あるいは分子を
外部に放出せしめることをいう。また、ダメージ層9と
は、上述の如く逆スパッタリングが施され、ゲート材層
8上層部から原子あるいは分子が放出されてその結晶構
造に損傷を受け、これにより機械的強度が脆弱になった
層をいう。
Next, as shown in FIG. 2, reverse sputtering is performed on this gate material layer 8 to form a damaged layer 9 on the upper layer of the gate material layer 8. Here, reverse sputtering refers to using the gate material layer 8 itself as a target material and colliding accelerated ions with it as shown by the arrows in FIG. 2 to form the gate material layer 8 from the upper layer of the gate material layer 8. It refers to releasing atoms or molecules to the outside. Furthermore, the damaged layer 9 is a layer in which the reverse sputtering has been performed as described above, and atoms or molecules are emitted from the upper layer of the gate material layer 8 and its crystal structure has been damaged, resulting in weak mechanical strength. means.

そして、ゲート材層8に逆スパッタリングを施ず場合、
例えばアルゴンなどのイオン圧力(スパッタ圧力)をI
Ps程度とし、ゲート材層8上層部をスパッタせしめる
And when reverse sputtering is not performed on the gate material layer 8,
For example, the ion pressure (sputtering pressure) of argon, etc.
The upper layer of the gate material layer 8 is sputtered at approximately Ps.

次いで、このダメージ層9を形成したゲート材層8にエ
ツチングを施して、第3図に示すように所定形状のゲー
ト電極3を形成する。ここでエツチングとしては、ホト
レジストを塗布し、これにマスクパターンを転写し、さ
らに上記レジストのパターンを用いてその下地の膜(本
発明の例ではゲート材層8 )を加工(エツチング)し
、レジストを除去する周知のフォトリソグラフィー・エ
ツチングなどによって行なわれる。また、この場合に形
成されたグート?1f極3は、その上層部が機械的に脆
弱なダメージ層9となっていることから、エツチングが
施された際に自然に隅部3a、3aの角が削れ、よって
その上層部が丸みを帯びた形状となる。
Next, the gate material layer 8 on which the damaged layer 9 has been formed is etched to form a gate electrode 3 having a predetermined shape as shown in FIG. For etching, a photoresist is applied, a mask pattern is transferred thereto, and the underlying film (gate material layer 8 in the example of the present invention) is processed (etched) using the resist pattern. This is done by well-known photolithography, etching, etc. Also, Gut formed in this case? Since the upper layer of the 1f pole 3 is a mechanically fragile damaged layer 9, the corners of the corners 3a, 3a are naturally shaved off when etching is performed, and the upper layer becomes rounded. It has a tinged shape.

次いで、第4図に示すようにガラス基板2上に上記ゲー
ト電極3を覆って窒化ケイ素(SiNx)などの絶縁膜
4を被覆形成し、その後この絶縁膜4上に水素化アモル
ファスシリコンなどの半導体膜5を被覆形成し、さらに
この半導体膜5上にアルミニウムなどのソース電極6お
よびドレイン電極7をそれぞれ形成して薄膜トランジス
タ1を得る。
Next, as shown in FIG. 4, an insulating film 4 such as silicon nitride (SiNx) is formed on the glass substrate 2 to cover the gate electrode 3, and then a semiconductor such as hydrogenated amorphous silicon is formed on the insulating film 4. A film 5 is formed to cover the semiconductor film 5, and a source electrode 6 and a drain electrode 7 made of aluminum or the like are respectively formed on the semiconductor film 5 to obtain the thin film transistor 1.

「発明の効果」 以上説明したように、この発明の薄膜トランジスタの製
造方法は、基板にゲート材層を形成し、次いでこのゲー
ト材層に逆スパッタリングを施してダメージ層を形成し
、その後上記ゲート材層にエツチングを施してゲート電
極を形成する乙のであるから、ゲート材層に逆スパッタ
リングを施ずことによりケート材層上層部にu的に脆弱
なダメージ層を形成することがてき、よってその後フォ
トリソグラフィー・エツチングなどのエツチングを施し
てゲート・電極を形成した際に、このゲート電極の上層
部が脆弱なダメージ層からなっているためその隅部の角
が自然に削れ、これによりその上層部か丸みを帯びた角
の無いゲート電極を形成することができ、絶縁膜のいわ
ゆるステップカバレージを向上することができる。した
がって、ゲート電極の隅部上の絶縁膜の膜厚が薄くなり
あるいは上記隅部に電界が集中するなどの不都合を防止
してこれら隅部上の絶縁膜での電流の漏れを抑制するこ
とができ、よって薄膜トランジスタの特性の向上を図り
、かつこの薄膜l・ランジスタを用いた製品の歩留りと
信頼性の向上を図ることができる。
"Effects of the Invention" As explained above, the method for manufacturing a thin film transistor of the present invention includes forming a gate material layer on a substrate, then performing reverse sputtering on this gate material layer to form a damaged layer, and then forming a damaged layer on the gate material layer. Since the gate electrode is formed by etching the gate material layer, by not performing reverse sputtering on the gate material layer, it is possible to form a fragile damaged layer on the upper layer of the gate material layer. When a gate/electrode is formed by etching such as lithography/etching, the upper layer of the gate electrode is made up of a fragile damaged layer, so the corners of the gate electrode are naturally shaved off. A gate electrode without rounded corners can be formed, and the so-called step coverage of the insulating film can be improved. Therefore, it is possible to prevent inconveniences such as thinning of the insulating film on the corners of the gate electrode or concentration of electric fields at the corners, and to suppress current leakage in the insulating film on these corners. Therefore, the characteristics of the thin film transistor can be improved, and the yield and reliability of products using this thin film transistor can be improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図ないし第4図はこの発明の薄膜トランジスタの製
造方法の一例を工程順に示す図であって、第1図はゲー
ト材層を形成した状態を示す説明図、第2図は逆スパッ
タリングを施してダメージ層を形成した状態を示す説明
図、第3図はエツチングを施した状態を示す説明図、第
4図は得られた薄膜トランジスタの該略構成図、第5図
は従来の薄膜トランジスタの該略構成図である。 l・・・・・薄膜トランジスタ、2・・・・・・ガラス
基板3・・・・・・ゲート7I¥極、3a・・・・・・
隅部、8・・・・・・ゲート材層、9・・・・・・ダメ
ージ層。
1 to 4 are diagrams showing an example of the method for manufacturing a thin film transistor of the present invention in the order of steps, in which FIG. 1 is an explanatory diagram showing a state in which a gate material layer is formed, and FIG. 3 is an explanatory diagram showing a state in which a damaged layer has been formed by etching, FIG. 4 is a schematic diagram of the structure of the obtained thin film transistor, and FIG. 5 is a schematic diagram of a conventional thin film transistor. FIG. l...Thin film transistor, 2...Glass substrate 3...Gate 7I\pole, 3a...
corner, 8... gate material layer, 9... damaged layer;

Claims (1)

【特許請求の範囲】[Claims]  基板にゲート材層を形成し、次いでこのゲート材層に
逆スパッタリングを施してダメージ層を形成し、その後
上記ゲート材層にエッチングを施してゲート電極を形成
することを特徴とする薄膜トランジスタの製造方法。
A method for manufacturing a thin film transistor, comprising forming a gate material layer on a substrate, then performing reverse sputtering on the gate material layer to form a damaged layer, and then etching the gate material layer to form a gate electrode. .
JP9274187A 1987-04-15 1987-04-15 Manufacture of thin-film transistor Pending JPS63258071A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9274187A JPS63258071A (en) 1987-04-15 1987-04-15 Manufacture of thin-film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9274187A JPS63258071A (en) 1987-04-15 1987-04-15 Manufacture of thin-film transistor

Publications (1)

Publication Number Publication Date
JPS63258071A true JPS63258071A (en) 1988-10-25

Family

ID=14062840

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9274187A Pending JPS63258071A (en) 1987-04-15 1987-04-15 Manufacture of thin-film transistor

Country Status (1)

Country Link
JP (1) JPS63258071A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012191185A (en) * 2011-02-24 2012-10-04 Semiconductor Energy Lab Co Ltd Semiconductor device and manufacturing method for semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012191185A (en) * 2011-02-24 2012-10-04 Semiconductor Energy Lab Co Ltd Semiconductor device and manufacturing method for semiconductor device

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