JPH02237161A - Thin-film transistor and its manufacture - Google Patents

Thin-film transistor and its manufacture

Info

Publication number
JPH02237161A
JPH02237161A JP5839989A JP5839989A JPH02237161A JP H02237161 A JPH02237161 A JP H02237161A JP 5839989 A JP5839989 A JP 5839989A JP 5839989 A JP5839989 A JP 5839989A JP H02237161 A JPH02237161 A JP H02237161A
Authority
JP
Japan
Prior art keywords
film
semiconductor layer
active semiconductor
gate electrode
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5839989A
Other languages
Japanese (ja)
Inventor
Tsutomu Tanaka
勉 田中
Satoru Kawai
悟 川井
Hideaki Takizawa
滝沢 英明
Norio Nagahiro
長廣 紀雄
Atsushi Inoue
淳 井上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5839989A priority Critical patent/JPH02237161A/en
Publication of JPH02237161A publication Critical patent/JPH02237161A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To control an active semiconductor layer to a desired thickness and to reduce a photocurrent by a method wherein a channel-protective film is formed of a semiconductor oxide film including an oxide film obtained by oxidizing the surface of the active semiconductor layer by means of a plasma. CONSTITUTION:A channel-protective film 5 is formed of a semiconductor oxide film formed by oxidizing a semiconductor layer by means of a plasma oxidation method. The semiconductor layer as a base material of this oxide film may be formed of only an active semiconductor layer 4 or of both the active semiconductor layer 4 and a contact layer 8 formed on it. Accordingly, an excess thickness part of the active semiconductor layer 4 can be reduced to a required minimum. Since the thickness of the active semiconductor layer 4 is made thin, a photocurrent generated when light is incident is reduced remarkably.

Description

【発明の詳細な説明】 〔概 要〕 液晶表示装置やエレクトロルミネッセンス等の駆動に用
いる薄膜トランジスタマトリクスとその製造方法に関し
、 製造工程を複雑化することなく、動作半導体層を所望の
厚さに制11rJ可能とし、もってフォトカレントを低
減することを目的とし、 動作半導体層の対向する二つの主面の一方にはゲート絶
縁膜を介してゲート電極を、他方には該ゲート電極に対
向する部位にチャネル保護膜を配設した薄膜l−ランジ
スタの構成において、前記チャネル保護膜が、前記動作
半導体層の表面をプラズマ酸化した酸化膜を含む半導体
酸化膜とした構成とする。
[Detailed Description of the Invention] [Summary] This invention relates to a thin film transistor matrix used for driving liquid crystal display devices, electroluminescence, etc., and a method for manufacturing the same, which allows controlling an active semiconductor layer to a desired thickness without complicating the manufacturing process. A gate electrode is provided on one of the two opposing main surfaces of the active semiconductor layer via a gate insulating film, and a channel is provided on the other side in a portion opposite to the gate electrode. In the structure of the thin film L-transistor provided with a protective film, the channel protective film is a semiconductor oxide film including an oxide film obtained by plasma oxidizing the surface of the active semiconductor layer.

(産業上の利用分野〕 本発明は、液晶表示装置やエレクトロルミネッセンス(
EL)等の駆動に用いる薄膜トランジスタ(TPT)マ
トリクスとその製造方法に関する。
(Industrial Application Field) The present invention is applicable to liquid crystal display devices and electroluminescence (
The present invention relates to a thin film transistor (TPT) matrix used for driving an EL device, etc., and a method for manufacturing the same.

TPTマトリクスにおいては、動作半導体層に光が入射
することによっておこるフォトカレントを最小限に抑え
ることは、素子特性を向上させる上で重要である。
In a TPT matrix, it is important to minimize the photocurrent caused by light incident on the active semiconductor layer in order to improve device characteristics.

〔従来の技術〕[Conventional technology]

動作半m 体1’Wにアモルファスシリコン(a −S
i)を用いた自己整合型のTPTマトリクスの、従来構
造とその製造工程を第4図に示す。
Motion half m Amorphous silicon (a-S
FIG. 4 shows the conventional structure and manufacturing process of a self-aligned TPT matrix using i).

まずガラス基板1の上にTi膜からなるゲート電極2を
形成する〔同図(a)参照〕。
First, a gate electrode 2 made of a Ti film is formed on a glass substrate 1 [see FIG. 3(a)].

このゲート電極2の上に、SiN膜からなるゲート絶縁
膜3、動作半導体層としてのa−St膜4、チャネル保
護膜としてのSin.膜5、密着層としてのa−Si膜
6を、プラズマ化学気相成長(P−CVD)法で連続的
に成膜する〔同図(b)参照〕。
On this gate electrode 2, a gate insulating film 3 made of a SiN film, an a-St film 4 as an active semiconductor layer, and a Sin. A film 5 and an a-Si film 6 as an adhesion layer are successively formed by plasma chemical vapor deposition (P-CVD) [see FIG. 13(b)].

次いで上記a−Si[6の上にフォトレジストを塗布形
成し、このレジスト膜にガラス基板1の裏面よりゲート
電極2をマスクとして紫外線を照射することにより、ゲ
ートと自己整合されたレジストパターン7を形成する〔
同図(C)参照〕。
Next, a photoresist is coated on the a-Si[6], and this resist film is irradiated with ultraviolet rays from the back surface of the glass substrate 1 using the gate electrode 2 as a mask, thereby forming a resist pattern 7 that is self-aligned with the gate. Form〔
See figure (C)].

次いで上記レジスト膜7をマスクとしてリアクティブイ
オンエッチング法により最上層のa−Si膜6を、その
下層のStOz膜5を弗酸系エッチング液を用いてエッ
チングし、これらの露出部を除去する〔同図(d)参照
)。
Next, using the resist film 7 as a mask, the uppermost a-Si film 6 and the lower StOz film 5 are etched using a hydrofluoric acid etching solution by reactive ion etching to remove these exposed portions. (See figure (d)).

次いでP−CVD法によりコンタクト層としてのn″a
−Si膜8を成膜し、その上に導電膜としてのTi膜9
を真空蒸着法にて積層する〔同図(e)参照〕。
Next, n″a was formed as a contact layer by P-CVD method.
- A Si film 8 is formed, and a Ti film 9 is formed thereon as a conductive film.
are laminated using a vacuum evaporation method [see figure (e)].

次いで上記マスクとして用いたレジスト膜7をアセトン
で除去して、その上のn”a−SiM8とTi膜9をリ
フトオフする〔同図(f)参照〕。
Next, the resist film 7 used as the mask is removed with acetone, and the n''a-SiM 8 and Ti film 9 thereon are lifted off [see FIG. 3(f)].

次いでソース電極S及びドレイン電極Dを形成するため
のレジストパターン(図示せず)を形成し、これをマス
クとしてプラズマエッチングを行ない、Ti膜9,n”
a−St膜8,およびa一Si膜4の不要部をエッチン
グ除去する。なお、木工程を施した後も、SiN膜3は
残留する〔同図(■参照〕。
Next, a resist pattern (not shown) for forming the source electrode S and drain electrode D is formed, and plasma etching is performed using this as a mask to form the Ti film 9,n''.
Unnecessary portions of the a-St film 8 and the a-Si film 4 are removed by etching. Note that the SiN film 3 remains even after the wood processing is performed [see figure (■)].

次いで同一ライン上のドレイン電極Dを共通に接続する
ために、Cr膜とAl膜との積層膜からなるドレインバ
ス10を形成する(同図(社)参照〕。
Next, in order to commonly connect the drain electrodes D on the same line, a drain bus 10 made of a laminated film of a Cr film and an Al film is formed (see the same figure).

なお、図示はしていないが、上記ドレインバス10とゲ
ートバスとの交差部は、ポリイミド膜で眉間を絶縁する
Although not shown, the intersection between the drain bus 10 and the gate bus is insulated between the eyebrows with a polyimide film.

次いでIT○膜からなる画素電極11を、その一端が上
記ソース電極Sの端部と重なり合うように形成するする
〔同図(i)参照〕。
Next, a pixel electrode 11 made of an IT◯ film is formed so that one end of the pixel electrode 11 overlaps the end of the source electrode S [see FIG. 12(i)].

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上記従来構造では、チャネル部上を被覆するチャネル保
護膜5と密着層6は光を透過するため、動作半導体層4
中に光が入射してフォトカレントが生起される。このフ
ォトカレントの大きさは、動作半導体層4が厚い程大き
くなる。
In the above conventional structure, since the channel protective film 5 and the adhesive layer 6 covering the channel portion transmit light, the active semiconductor layer 4
Light enters inside and a photocurrent is generated. The magnitude of this photocurrent increases as the active semiconductor layer 4 becomes thicker.

従来のTPT構造では、製造工程上の制約から動作半導
体層4の厚さを、TPTの動作に必要な厚さに比較して
必要以上に厚くせざるを得す、そのためフォトカレント
も大きくなり、TPTのOFF状態における電流値が2
〜3桁増大し、素子特性を劣化させるという問題があっ
た。
In the conventional TPT structure, due to constraints in the manufacturing process, the thickness of the active semiconductor layer 4 has to be made thicker than necessary compared to the thickness necessary for the operation of the TPT, which also increases the photocurrent. The current value in the OFF state of TPT is 2
There was a problem in that the amount increased by ~3 orders of magnitude, deteriorating the device characteristics.

本発明は、製造工程を複雑化することなく、動作半導体
層を所望の厚さに制御可能とし、もってフォトカレント
を低減することを目的とする。
An object of the present invention is to make it possible to control an active semiconductor layer to a desired thickness without complicating the manufacturing process, thereby reducing photocurrent.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の構成を第1図に示す。 The configuration of the present invention is shown in FIG.

本発明ではチャネル保護膜5を、半導体層をプラズマ酸
化法で酸化して形成した半導体酸化膜とした。なおこの
酸化膜の母材となる半導体層は、動作半導体層4のみで
もよく、動作半導体層4とその上に形成したコンタクト
層8の双方であってもよい。
In the present invention, the channel protective film 5 is a semiconductor oxide film formed by oxidizing a semiconductor layer using a plasma oxidation method. Note that the semiconductor layer serving as the base material of this oxide film may be only the active semiconductor layer 4, or may be both the active semiconductor layer 4 and the contact layer 8 formed thereon.

上記構造は、絶縁性基板1上にゲート電極2と、これを
被覆するゲート絶縁膜3,その上に少なくとも動作半導
体層4を形成し、この動作半導体層上にコンタクト層8
と導電膜9を、少なくとも導電膜9が上記ゲート電極2
直上部に開口部を有する形状に形成し、この導電膜9を
マスクとしてプラズマ酸化法を施し、上記動作半導体層
4の上記ゲート電極2直上部に半導体酸化膜からなるチ
ャネル保護膜5を形成するとともに、%該部分の動作半
導体層4を所望の厚さに制御することにより作製できる
In the above structure, a gate electrode 2 is formed on an insulating substrate 1, a gate insulating film 3 covering the gate electrode 2, at least an active semiconductor layer 4 is formed on the gate electrode 2, and a contact layer 8 is formed on the active semiconductor layer.
and a conductive film 9, at least the conductive film 9 is connected to the gate electrode 2.
A channel protection film 5 made of a semiconductor oxide film is formed on the active semiconductor layer 4 directly above the gate electrode 2 by forming a shape having an opening directly above and performing plasma oxidation using the conductive film 9 as a mask. At the same time, the semiconductor layer 4 can be manufactured by controlling the thickness of the active semiconductor layer 4 in this portion to a desired thickness.

〔作 用〕[For production]

上記構造としたことにより、動作半導体層の余分な厚さ
部分をすべて酸化してチャネル保護膜5とすることによ
り、動作半導体層4の最終厚さを必要最低限とすること
ができる。このように動作半導体層4の厚さを薄くする
ことにより、光の入射により生起されるフォトカレント
は著しく減少する。
With the above structure, the final thickness of the active semiconductor layer 4 can be reduced to the necessary minimum by oxidizing all the excess thickness of the active semiconductor layer to form the channel protection film 5. By reducing the thickness of the active semiconductor layer 4 in this way, the photocurrent generated by the incidence of light is significantly reduced.

−L記チャネル保護膜5を形成するために酸化する半導
体層を、動作半導体層4のみとした場合および動作半導
体層4とコンタクト層8の双方とした場合については、
実施例の説明の欄において詳述する。
- When the semiconductor layer to be oxidized to form the channel protective film 5 is only the active semiconductor layer 4, and when both the active semiconductor layer 4 and the contact layer 8 are used,
This will be explained in detail in the section describing the embodiments.

以上の如く本発明によれば、動作半導体層の膜厚の制御
が可能であり、TPT特性の向上が図れるばかりでなく
、半導体層の酸化は横方向にも進行するので、チャネル
保護膜5はソース・ドレイン電極の端部の下にもぐり込
む形状となる。従って、コンタクト層のサイドエッジに
働く応力の分散にもつながり、クシックの発生をなくす
ことも可能である。また従来の製造工程におけるチャネ
ル保護膜のエッチング工程が不要化され、製造工程の簡
略化が図れる。
As described above, according to the present invention, it is possible to control the film thickness of the active semiconductor layer, and not only can the TPT characteristics be improved, but also the oxidation of the semiconductor layer progresses in the lateral direction, so that the channel protective film 5 can be It has a shape that goes under the end of the source/drain electrode. Therefore, it also leads to dispersion of stress acting on the side edges of the contact layer, and it is also possible to eliminate the occurrence of cictic. Furthermore, the etching step of the channel protective film in the conventional manufacturing process is no longer necessary, and the manufacturing process can be simplified.

〔実 施 例〕〔Example〕

以下本発明の第1及び第2の実施例を図面を参照して説
明する。
First and second embodiments of the present invention will be described below with reference to the drawings.

第2図(a)〜(i)に本発明の第1の実施例を示す。A first embodiment of the present invention is shown in FIGS. 2(a) to 2(i).

本実施例では、動作半導体層としてa−SilpJ4を
用い、チャネル保護膜5はこのa−Si膜4を酸化して
形成した。
In this example, a-SilpJ4 was used as the active semiconductor layer, and the channel protection film 5 was formed by oxidizing this a-Si film 4.

ガラス基板1の上にTi膜からなるゲート電極2を形成
し(同図(a)参照〕、その上にゲート絶縁膜としての
SiN膜3と、動作半導体層としてのa−Si膜4をP
−CVD法で連続成膜する。本実施例では従来と異なり
、これの上にチャネル保護膜を成膜しない(同図(b)
参照〕。
A gate electrode 2 made of a Ti film is formed on a glass substrate 1 (see figure (a)), and a SiN film 3 as a gate insulating film and an a-Si film 4 as an active semiconductor layer are deposited thereon.
-Continuous film formation by CVD method. In this example, unlike the conventional method, a channel protective film is not formed on this (see figure (b)).
reference〕.

」一記a−St膜4の厚さは、設計上は凡そ50人程度
とすることが望ましいにもかかわらず、このように薄い
膜を均一且つ欠陥なしに成膜することはきわめて困難で
、実用上ほとんど不可能に近い。そこで本実施例では、
a=si膜4の当初厚さ約300人に成膜した。
Although it is desirable for the thickness of the a-St film 4 to be about 50 in terms of design, it is extremely difficult to form such a thin film uniformly and without defects. Practically speaking, it is almost impossible. Therefore, in this example,
A=Si film 4 was deposited to an initial thickness of about 300 mm.

次いでフォトレジストを塗布し、ガラス基板1の裏面よ
りゲート電極2をマスクとして紫外線露光を行ない、ゲ
ート電極2と自己整合しレジス1・パターン7を形成す
る〔同図(C)参照〕。
Next, a photoresist is applied and exposed to ultraviolet light from the back surface of the glass substrate 1 using the gate electrode 2 as a mask to form a resist 1/pattern 7 that is self-aligned with the gate electrode 2 [see FIG. 3(C)].

?いでP−CVD法により、コンタクト層として約50
0人の厚さのn″a−Si膜8を形成し、更にその上に
ソース・ドレイン電極の導電膜としてTi膜9を真空蒸
着法にて形成する〔同図(d)参照〕。
? Approximately 50% of the contact layer was
An n''a-Si film 8 having a thickness of 0.04 cm is formed, and a Ti film 9 is further formed thereon as a conductive film for the source/drain electrodes by vacuum evaporation [see FIG. 4(d)].

次いで、アセトンでレジスト膜7を除去して、その−F
のn″a−Si膜8とTi膜9をリフトオフし、チャネ
ル部すなわちゲート電極2直上部のa−St膜4を露出
させる〔同図(e)参照]。
Next, the resist film 7 is removed with acetone, and the -F
The n'' a-Si film 8 and Ti film 9 are lifted off to expose the channel portion, that is, the a-St film 4 directly above the gate electrode 2 [see FIG. 2(e)].

次いで、上記Ti膜9をマスクとして、例えばRFパワ
ー300W、基板温度250゜C、反応室内圧力ITo
 r r、バイアス電圧200■の条件下でプラズマ酸
化を行ない、動作半導体層4の露出部を約50人の厚さ
を残して酸化し、チャネル保護膜となるSiO■膜5を
形成する。上述の条件における酸化レートは、約100
人/時間である〔同図(e)参照〕。
Next, using the Ti film 9 as a mask, for example, the RF power is 300 W, the substrate temperature is 250°C, and the reaction chamber pressure is ITo.
Plasma oxidation is performed under the conditions of r r and a bias voltage of 200 mm to oxidize the exposed portion of the active semiconductor layer 4, leaving a thickness of approximately 50 mm, thereby forming an SiO2 film 5 that will serve as a channel protective film. The oxidation rate under the above conditions is approximately 100
person/time [see figure (e)].

本工程で形成するSiO■膜5の厚さを特に限定する必
要はないが、最終的なa−Si膜4の厚さを、上述した
ように目的とする特性を得るのに必要な最低限の厚さと
することが望ましく、a −Si膜4の厚さをこのよう
に薄くすることによって、諸特性を劣化することなくフ
ォト力レンを低減することができ、OFF電流を小さく
することが可能となる。
Although it is not necessary to specifically limit the thickness of the SiO film 5 formed in this step, the thickness of the final a-Si film 4 should be set to the minimum thickness necessary to obtain the desired characteristics as described above. By reducing the thickness of the a-Si film 4 in this way, it is possible to reduce the photo force flux without deteriorating various characteristics, and it is possible to reduce the OFF current. becomes.

このように、本実施例ではチャネル保護膜5を動作半導
体層であるa−Si膜4の表面部分をプラズマ酸化して
形成するので、a−Si膜4を成膜時には厚く形成して
おき、これの不要部をチャネル保護膜5に変換して、a
−Si[4を上述のような薄い厚さに制御することが可
能である。
As described above, in this embodiment, the channel protection film 5 is formed by plasma oxidation of the surface portion of the a-Si film 4, which is the active semiconductor layer, so the a-Si film 4 is formed thickly during film formation. The unnecessary part of this is converted into a channel protective film 5, and a
-Si[4 can be controlled to have a thin thickness as described above.

次いで、上記Ti膜9の上部に生成された酸化膜をスラ
イドエッチングし、レジスト膜(図示せず)を7スクと
してTi膜9,n”a−Si膜8,6−Si膜4の不要
部をプラズマエッチングにより除去し、ソース電極Sと
ドレイン電極Dを形成する。〔同図(粉参照〕。
Next, the oxide film formed on the top of the Ti film 9 is slide-etched, and a resist film (not shown) is used as 7 masks to remove unnecessary parts of the Ti film 9, n''a-Si film 8, 6-Si film 4. is removed by plasma etching to form a source electrode S and a drain electrode D. [See the same figure (see powder)].

この後の工程は従来と同様に進めてよい。即ち同一ライ
ン上のドレイン電極Dを共通に接続するために、Cr膜
とA2膜との積層膜からなるドレインバス10を形成す
る〔同図(h)参照〕。なお、図示はしていないが、上
記ドレインバス10とゲートバスとの交差部は、ポリイ
ミド膜で眉間を絶縁する。
The subsequent steps may proceed in the same manner as before. That is, in order to connect the drain electrodes D on the same line in common, a drain bus 10 made of a laminated film of a Cr film and an A2 film is formed [see FIG. 4(h)]. Although not shown, the intersection between the drain bus 10 and the gate bus is insulated between the eyebrows with a polyimide film.

次いでITO膜からなる画素電極1lを、その一端が.
ヒ記ソース電極Sの端部と重なり合うように形成するす
る〔同図(i)参照〕。
Next, one end of the pixel electrode 1l made of ITO film is .
It is formed so as to overlap the end of the source electrode S (see figure (i)).

以上説明した本実施例を製造するに当たっては、従来と
比較して動作半導体層を酸化するためのプラズマ酸化工
程が増加するが、チャネル保護膜のエンチング工程がな
《なるので、工程数の増減はない。しかも、動作半導体
層4の厚さを必要最低限とすることができるので、フォ
トカレントが減少する。
In manufacturing this embodiment as described above, the plasma oxidation process for oxidizing the active semiconductor layer is increased compared to the conventional method, but the etching process for the channel protective film is not required, so the increase or decrease in the number of processes is do not have. Furthermore, since the thickness of the active semiconductor layer 4 can be reduced to the necessary minimum, photocurrent is reduced.

次に本発明の第2実施例を第3図(a)〜(i)により
説明する。本実施例は、動作半導体層4およびコンタク
トN8とを母材として、チャネル保護膜5を形成する例
である。
Next, a second embodiment of the present invention will be described with reference to FIGS. 3(a) to (i). This example is an example in which the channel protective film 5 is formed using the active semiconductor layer 4 and the contact N8 as base materials.

この第2の実施例では、前述の第1の実施例と異なり、
ガラス基板1の上にTiからなるゲート電極2を形成し
〔同図(a)参照〕、これの上を被覆するSiN膜3,
a−Si膜4と、更にコンタクト層としてのn″″a−
Si膜8を、P−CVD法で連続成膜する〔同図℃)参
照〕。
In this second embodiment, unlike the first embodiment described above,
A gate electrode 2 made of Ti is formed on a glass substrate 1 [see figure (a)], and a SiN film 3 is coated thereon.
a-Si film 4 and further n″″a- as a contact layer.
A Si film 8 is continuously formed by the P-CVD method (see the same figure at 0C).

上記a−St膜4及びn”a−Si膜8の当初厚さは、
上記第1の実施例と同じく、約300人および約500
人とした。
The initial thicknesses of the a-St film 4 and n''a-Si film 8 are as follows:
As in the first embodiment, about 300 people and about 500 people
As a person.

次いでこの上にゲート電極2と自己整合したレジストパ
ターン7が形成し〔同図(C)参照〕、次いでソース・
ドレイン電掻の導電膜としてTi膜9を真空蒸着法にて
形成し〔同図(d)参照〕、次いでリフトオフ法により
レジスト膜7とともに、その上のTi膜9を除去する〔
同図(e)参照〕。
Next, a resist pattern 7 that is self-aligned with the gate electrode 2 is formed thereon [see figure (C)], and then a source pattern 7 is formed.
A Ti film 9 is formed as a conductive film for drain electrode scraping by a vacuum evaporation method [see figure (d)], and then the resist film 7 and the Ti film 9 thereon are removed by a lift-off method.
See figure (e)].

本工程終了時には、ゲート電極2直上部のn゛a−Si
膜8が露出する。そこで、上記Ti膜9をマスクとして
プラズマ酸化を行ない、上記n′″a−Si膜8をその
厚さ全部と、下層のa−Si膜4の1一層部分を酸化し
て、SiOzWi.からなるチャネル保護膜5を形成す
る〔同図げ)参照]。
At the end of this process, the na-Si directly above the gate electrode 2 is
Membrane 8 is exposed. Therefore, using the Ti film 9 as a mask, plasma oxidation is performed to oxidize the entire thickness of the n'''a-Si film 8 and the first layer of the underlying a-Si film 4, thereby forming a SiOzWi. A channel protective film 5 is formed [see the same figure].

本実施例においては、特性上望ましい最低限の厚さ.即
ち約50人の厚さのa−Si膜4が残留する程度に、上
記プラズマ酸化を行なう.従って本実施例では、約50
0人の厚さのn″a−Si膜8の全部とa−St膜4の
上から約250人をチャネル保護膜5に変換する。
In this example, the thickness is the minimum thickness that is desirable in terms of characteristics. That is, the plasma oxidation is performed to the extent that the a-Si film 4 with a thickness of approximately 50 mm remains. Therefore, in this example, approximately 50
The entirety of the n'' a-Si film 8 having a thickness of 0 and about 250 from above the a-St film 4 is converted into a channel protective film 5.

このように本実施例もa−Si膜4の最終厚さを、望ま
しい厚さの約50人ときわめて薄くするので、フォトカ
レソトは従来と比較して大幅に減少し、その効果は上記
第1の実施例と変わりはない。
As described above, in this embodiment, the final thickness of the a-Si film 4 is made extremely thin by approximately 50 mm, which is the desired thickness, so that the photovoltage is significantly reduced compared to the conventional method, and the effect is the same as the first one described above. There is no difference from the embodiment.

この後の工程は第1の実施例と同様に進めてよく、同図
(局,(ハ),(i)に示すように、レジスト膜(図示
せず)をマスクとして、Ti膜9,n” a−Si膜3
,a−Si膜4の不要部を除去し、同一ライン上のドレ
イン電極Gを共通に接続するドレインバス10を形成し
、次いで、ソース電極Sと端部が接続するITOからな
る画素電極Eを形成し7て、本実施例が完成する。
The subsequent steps may be carried out in the same manner as in the first embodiment, and as shown in FIGS. ” a-Si film 3
, remove unnecessary parts of the a-Si film 4, form a drain bus 10 that commonly connects the drain electrodes G on the same line, and then form a pixel electrode E made of ITO whose end is connected to the source electrode S. 7, this embodiment is completed.

以上説明した第2の実施例においても、第1の実施例と
同様に、製造工程数を増加させることなく、動作半導体
層の厚さを任意に制御することができるので、フォトカ
レントが減少し、TPTの素子特性が向上する。また、
チャネル保護膜5がソース・ドレイン電極の導電膜であ
るTi膜9の端部の下部に重なり合うので、ソース・ド
レイン電極のエッジに集まる応力を分散でき、クシック
の発生を防止できる。
In the second embodiment described above, as in the first embodiment, the thickness of the active semiconductor layer can be controlled arbitrarily without increasing the number of manufacturing steps, so the photocurrent is reduced. , the device characteristics of TPT are improved. Also,
Since the channel protective film 5 overlaps the lower part of the edge of the Ti film 9, which is the conductive film of the source/drain electrode, stress that gathers at the edge of the source/drain electrode can be dispersed, and the generation of oxidation can be prevented.

なお、−ト記第1および第2の実施例において、半導体
層としてa−Si膜を用いた例を説明したが、本発明は
これに限定されるものではな《、多結晶Siや単結晶S
t等、特に限定されるものではない。
In addition, in the first and second embodiments described above, an example was explained in which an a-Si film was used as the semiconductor layer, but the present invention is not limited to this. S
t, etc., are not particularly limited.

また、動作半導体層およびコンタクト層の当初厚さ、お
よび動作半導体層の最終厚さも、上記第1および第2の
実施例に限定されるものではないことは、特に説明する
までもない。
Further, it goes without saying that the initial thickness of the active semiconductor layer and the contact layer and the final thickness of the active semiconductor layer are not limited to those of the first and second embodiments.

〔発明の効果〕〔Effect of the invention〕

以上説明した如く本発明によれば、動作半導体層の膜厚
を任意に制御することが可能となり、フォトカレントを
抑制してTPTの素子特性を向上ずることができ、従っ
て製造歩留が向上し、製造コストの低減を図れる。また
ソース・ドレイン電極のエッジに集まる応力の分散が図
れ、クラックの発生を無くずことができる。
As explained above, according to the present invention, the thickness of the active semiconductor layer can be controlled arbitrarily, photocurrent can be suppressed and the device characteristics of TPT can be improved, and therefore the manufacturing yield can be improved. , it is possible to reduce manufacturing costs. Furthermore, the stress that collects at the edges of the source/drain electrodes can be dispersed, and the occurrence of cracks can be eliminated.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の構成説明図、 第2図(a)〜(i)は本発明第1の実施例説明図、第
3図(a)〜(i)は本発明第2の実施例説明図、第4
図(a)〜(i)は従来のTPTの製造工程説明図であ
る。 図において、1は絶縁性基板(ガラス基板)、2はゲー
ト電極、3はゲート絶縁膜(SiN膜)、4は動作半導
体層(a−St膜)、5はチャネル保護膜(Sing膜
)、7はレジストパターン、8はコンタクト層(n’a
−Si膜)、9は導電膜(Tt膜)、S,Dはソース電
極およ70−7ズ・・マ含表イ邑 ,V発明泥績へ′詫所謂 第1図
Fig. 1 is an explanatory diagram of the configuration of the present invention, Fig. 2 (a) to (i) is an explanatory diagram of the first embodiment of the present invention, and Fig. 3 (a) to (i) is an explanatory diagram of the second embodiment of the present invention. Explanatory diagram, 4th
Figures (a) to (i) are explanatory diagrams of conventional TPT manufacturing steps. In the figure, 1 is an insulating substrate (glass substrate), 2 is a gate electrode, 3 is a gate insulating film (SiN film), 4 is an active semiconductor layer (a-St film), 5 is a channel protection film (Sing film), 7 is a resist pattern, 8 is a contact layer (n'a
-Si film), 9 is a conductive film (Tt film), S and D are source electrodes and 70-7z...

Claims (2)

【特許請求の範囲】[Claims] (1)動作半導体層(4)の対向する二つの主面の一方
にはゲート絶縁膜(3)を介してゲート電極(2)を、
他方には該ゲート電極(2)に対向する部位にチャネル
保護膜(5)を配設した薄膜トランジスタの構成におい
て、 前記チャネル保護膜(5)が、前記動作半導体層(4)
の表面をプラズマ酸化した酸化膜を含む半導体酸化膜で
あることを特徴とする薄膜トランジスタ。
(1) A gate electrode (2) is connected to one of the two opposing main surfaces of the operational semiconductor layer (4) via a gate insulating film (3).
On the other hand, in the structure of a thin film transistor in which a channel protective film (5) is disposed at a portion facing the gate electrode (2), the channel protective film (5) is arranged on the active semiconductor layer (4).
A thin film transistor characterized in that it is a semiconductor oxide film including an oxide film whose surface is plasma oxidized.
(2)絶縁性基板(1)上にゲート電極(2)、ゲート
絶縁膜(3)、動作半導体層(4)を形成し、その上に
コンタクト層(8)と導電膜(9)を、少なくとも該導
電膜が前記ゲート電極(2)直上部に開口部を有する形
状に形成した後、該導電膜(9)をマスクとしてプラズ
マ酸化法を施し、前記動作半導体層(4)の前記ゲート
電極(2)直上部に半導体酸化膜からなるチャネル保護
膜(5)を形成するとともに、当該部分の動作半導体層
(4)を所望の厚さに制御する工程を含むことを特徴と
する薄膜トランジスタの製造方法。
(2) A gate electrode (2), a gate insulating film (3), and an active semiconductor layer (4) are formed on an insulating substrate (1), and a contact layer (8) and a conductive film (9) are formed thereon. After the conductive film is formed in a shape having at least an opening directly above the gate electrode (2), a plasma oxidation method is performed using the conductive film (9) as a mask, and the gate electrode of the active semiconductor layer (4) is (2) Manufacturing a thin film transistor characterized by including a step of forming a channel protective film (5) made of a semiconductor oxide film directly above the film and controlling the active semiconductor layer (4) in the corresponding part to a desired thickness. Method.
JP5839989A 1989-03-10 1989-03-10 Thin-film transistor and its manufacture Pending JPH02237161A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5839989A JPH02237161A (en) 1989-03-10 1989-03-10 Thin-film transistor and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5839989A JPH02237161A (en) 1989-03-10 1989-03-10 Thin-film transistor and its manufacture

Publications (1)

Publication Number Publication Date
JPH02237161A true JPH02237161A (en) 1990-09-19

Family

ID=13083279

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5839989A Pending JPH02237161A (en) 1989-03-10 1989-03-10 Thin-film transistor and its manufacture

Country Status (1)

Country Link
JP (1) JPH02237161A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007013083A (en) * 2005-06-30 2007-01-18 Lg Philips Lcd Co Ltd Thin film transistor and its manufacturing method
JP2010283326A (en) * 2009-06-03 2010-12-16 Lg Display Co Ltd Array substrate and method of manufacturing the same
JP2012209557A (en) * 2011-03-28 2012-10-25 Boe Technology Group Co Ltd Amorphous oxide thin film transistor, method for manufacturing the same, and display panel comprising the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007013083A (en) * 2005-06-30 2007-01-18 Lg Philips Lcd Co Ltd Thin film transistor and its manufacturing method
JP4578402B2 (en) * 2005-06-30 2010-11-10 エルジー ディスプレイ カンパニー リミテッド Thin film transistor substrate and manufacturing method thereof
JP2010283326A (en) * 2009-06-03 2010-12-16 Lg Display Co Ltd Array substrate and method of manufacturing the same
JP2012209557A (en) * 2011-03-28 2012-10-25 Boe Technology Group Co Ltd Amorphous oxide thin film transistor, method for manufacturing the same, and display panel comprising the same
US9608127B2 (en) 2011-03-28 2017-03-28 Boe Technology Group Co., Ltd. Amorphous oxide thin film transistor, method for manufacturing the same, and display panel

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