JPS63257837A - Check system for multi-processor system - Google Patents

Abstract

PURPOSE:To attain the check of memory content of all processors by using a bus connector and a DMA controller enabling to set an address and data word number externally by a specific data on a bus so as to use a check control program only. CONSTITUTION:In detecting a data with a specific identifier on a data bus 10 by a bus connector 21, it is written in a register 25 and a DMA controller 22 applies direct memory access with a memory 23 accordingly. When a check exclusive processor 50 reads a data of a specific processor unit 20 connected to the bus 10, since the unit 20 returns a designated data onto the bus independently of the software by sending the data representing a processor identifier, a DMA address and a word count and a data representing the direction of data to the bus 10, the data is realized and checked by displaying onto a terminal 30 connected to the processor 50.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a remote inspection system for multiprocessor systems connected via a data bus, and in particular to a remote inspection system for checking the contents of memory used by individual processor units (MPUs). Regarding inspection.

〔overview〕

The present invention provides a means for directly accessing the built-in memory of a processor unit using specific data on the bus in a testing method for a multiprocessor system consisting of a plurality of processor units each connected to one data bus. The test-dedicated processor connected to the data bus sends the specific data to the processor unit to be tested, and the data sent back from the processor unit to be tested is tested against this sent data. By doing so, the built-in memory of each processor unit can be easily inspected by remote control without requiring a special program for inspection of each processor unit.

[Conventional technology]

Conventionally, when testing a multiprocessor system of the same type, individual processor units (MPUs) are used as shown in Figure 3.
Either connect the terminals 3 directly to the terminals 3 and run some kind of test program present in each terminal 3, or, as shown in FIG. Using the dedicated processor 5, both the individual processor units and the test-dedicated processor 5 execute a communication control program for testing.

[Problem that the invention seeks to solve]

In the conventional multiprocessor system inspection method described above, in the case shown in Figure 3, a terminal for inspection is required for each individual processor unit, and as the network becomes long, it becomes impossible for one person to operate multiple terminals at the same time. There were drawbacks.

Furthermore, both Figures 3 and 4 commonly require a certain type of communication control program in all processor units for inspection, and if the processor units have different types and configurations, a different communication control program is required for each model. In order to require a large amount of software, and to allow the inspection to be performed simultaneously while the application program on each processor unit is running,
The drawback was that it required advanced software techniques.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for testing a multiprocessor system that can be easily tested by remote control by eliminating the above-mentioned drawbacks.

[Failure to solve the problem]

The present invention provides a multiprocessor system testing method for testing each processor unit in a multiprocessor system composed of a plurality of processor units each connected to one data bus. means for directly accessing the built-in memory with specific data of the processor unit, connected to the data bus, transmitting the specific data to the processor unit under test, and transmitting the specific data from the processor unit under test; The present invention is characterized by comprising a processor dedicated to testing, including means for testing the data obtained.

[For production]

Specific data with an identifier added is sent from the test-dedicated processor to the processor unit to be tested via the data bus. In the processor unit to be tested, specified data is read from the built-in memory using its direct access means and sent back to the test-dedicated processor. The test-dedicated processor displays this data on its terminal, for example, and performs the test.

Therefore, each processor unit does not need to have its own inspection program, but operates according to the program of the inspection-dedicated processor, and the contents of the built-in memory can be inspected easily and remotely.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. This embodiment includes a multiprocessor system consisting of a plurality of processor units (MPU) 20 each connected to a data bus 10, a test processor 50 that tests each processor unit 20 connected to the data bus 10, and a test processor 50 that tests each processor unit 20 connected to the data bus 10. and a terminal 30 connected to a dedicated processor 50.

FIG. 2 is a block diagram showing details of the processor unit 20 shown in FIG. 1. The processor unit 20 is connected to an internal bus 26 and performs overall control.
4, a memory 23 that is connected to the internal bus 26 and stores required data, a DMA controller 22 that is connected to the internal bus 26 and performs direct access to the memory 23, and a DMA controller 22 whose output is connected to the DMA controller 22. A register 25 including an address register and a word counter register is connected to the data bus 10, demodulates the signal input from the data bus 10, and controls the DMA controller 22 and
It includes a bus connector 21 that converts and sends a signal to the PU 24 and writes specific data to which a specific identifier is added to the register 25. Further, the test-dedicated processor 50 includes means for sending specific data to the data bus 10 and means for testing the data sent back.

The feature of the present invention is that in FIG.
0, and a processor unit 20 including a bus connector 21, a DMA controller 22 and a register 25 as means for direct access, the details of which are shown in FIG.

Next, the operation of this embodiment will be explained.

When the bus connector 51 detects data with a specific identifier on the lotus 10, it writes it into the registers (address register and word counter register) 6, and DM
The A controller 52 performs direct memory access to the memory 23 in response. A specific processor unit 20 with a test dedicated processor 50 connected to the data bus 10
When reading data from a particular processor unit 20, a particular processor unit 20 can read data from bus 10 without any software involvement by sending data indicating the processor identifier, DMA address, word count, and data direction onto bus 10.
Since the specified data is returned on the 0, the inspection can be performed by displaying the data on the terminal 30 connected to the inspection-dedicated processor 50.

C. Effects of the Invention] As explained above, the present invention provides a multiprocessor system using a data bus, in which the address and number of data words of a DMA controller can be externally set using specific data on the bus. By using a DMA controller and a DMA controller, you can control the memory contents of all processors connected to the bus by simply creating a control program for the processor dedicated to testing, without having to run a special program for testing on each multiprocessor. It has the effect of allowing inspection. Furthermore, even if the processor units are of different types, as long as the hash connector and DMA controller are designed to common specifications, there is no need to change or add software. The quantity and physical distance are not a problem as long as they are within the performance of the data bus, and there is no need to change the software of the testing processor, which has the effect of making testing easier.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a block diagram showing details of the processor unit. FIG. 3 and FIG. 4 are block configuration diagrams each showing a conventional example. 1.10...Data bus, 2.20...Processor unit (MPU), 3.30...Terminal, 4
...Test dedicated line, 5.50...Test dedicated processor, 21...Bus connector, 22...DMA?
li controller, 23... memory, 24... CPU, 2
5...Register.

Claims (1)

[Claims] (1) In a multiprocessor system inspection method in which each processor unit is tested in a multiprocessor system consisting of a plurality of processor units each connected to one data bus, each processor unit is a means for directly accessing the built-in memory with specific data; connected to the data bus; and means for transmitting the specific data to the processor unit under test; 1. A testing method for a multiprocessor system, comprising a testing-dedicated processor including means for testing data.