JPS63255937A - Chip mounting equipment - Google Patents

Chip mounting equipment

Info

Publication number
JPS63255937A
JPS63255937A JP62091281A JP9128187A JPS63255937A JP S63255937 A JPS63255937 A JP S63255937A JP 62091281 A JP62091281 A JP 62091281A JP 9128187 A JP9128187 A JP 9128187A JP S63255937 A JPS63255937 A JP S63255937A
Authority
JP
Japan
Prior art keywords
chip
push
collet
semiconductor chip
pins
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62091281A
Other languages
Japanese (ja)
Inventor
Katsunori Nishiguchi
勝規 西口
Takeshi Sekiguchi
剛 関口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP62091281A priority Critical patent/JPS63255937A/en
Publication of JPS63255937A publication Critical patent/JPS63255937A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68318Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
    • H01L2221/68322Auxiliary support including means facilitating the selective separation of some of a plurality of devices from the auxiliary support

Landscapes

  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Supply And Installment Of Electrical Components (AREA)

Abstract

PURPOSE:To prevent the cracking of a chip at the time of pick-up, by performing a control wherein a second toss member is pushed up after a first toss member is pushed up, and then the first toss member descends. CONSTITUTION:A first toss member 14 pushes up a chip 13 in the state where a shock is released, and a second toss member 15 acts to retain the chip 13 in the manner in which an expand tape 16 exfoliates from the peripheral part of the chip 13. Therefore, the expand tape 16 is easily exfoliated, and the large attractive force of a collet 11 is not necessary to be large, so that the semiconductor chip 13 is not sucked by an excessive attractive force. Thereby, the generation of crack at the time of attraction to the collet can be prevented.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体チップや、チップコンデンサ、チップ抵
抗の如き小型電子部品をパッケージにダイポンディンし
たり、ケースに分別収納するために使用されるチップ実
装装置に関、する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention is applied to chip packaging used for packaging small electronic components such as semiconductor chips, chip capacitors, and chip resistors into packages or storing them separately in cases. Regarding equipment.

〔従来の技術〕[Conventional technology]

半導体装置の製造においては、半導体ウェー八から形成
された半導体チップを1つづつパッケージにダイポンデ
ィングするため、半導体チップをピックアップすること
が行われる。この場合、半導体ウェーハはエキスパンド
テープ上でダイシングが行われて個々の半導体チップに
分別されており、半導体チップをエキスパンドテープか
ら剥離してパッケージに搬送するため、チップ実装装置
が使用される。
In the manufacture of semiconductor devices, semiconductor chips are picked up in order to die-bond the semiconductor chips formed from a semiconductor wafer one by one into a package. In this case, the semiconductor wafer is diced onto an expanded tape and separated into individual semiconductor chips, and a chip mounting device is used to separate the semiconductor chips from the expanded tape and transport them to a package.

第3図および第4図はかかるチップ実装装置の一例とし
て、半導体チップ実装装置の従来例を示す図である。こ
の装置は真空吸引手段(図示せず。)に接続されたコレ
ット1と、コレット1の下方で上下動する突上げピン2
とを備えている。
FIGS. 3 and 4 are diagrams showing a conventional example of a semiconductor chip mounting apparatus as an example of such a chip mounting apparatus. This device consists of a collet 1 connected to a vacuum suction means (not shown), and a push-up pin 2 that moves up and down below the collet 1.
It is equipped with

半導体ウェーハのダイシングによって個々に分別された
半導体チップ3は、ダイシングの際に半導体ウェーハの
下面に接着されたエキスパンドテープ4に支持された状
態で、コレット1と突上げピン2どの間に搬送される。
Semiconductor chips 3, which are individually separated by dicing the semiconductor wafer, are transported between the collet 1 and the push-up pins 2 while being supported by the expandable tape 4 adhered to the bottom surface of the semiconductor wafer during dicing. .

この搬送により半導体チップ3がコレット1の吸着口5
の下方に達すると、突上げピン2がエキスパンドテープ
4の下面を突き上げて半導体チップ3を吸着口5の方向
に押し上げる。これにより、エキスパンドチー14が上
方に湾曲すると共に、半導体チップ3がコレット1の吸
引力でコレット1の吸着口方向に吸引される。このため
、半導体チップ3の下面の周辺部からエキスパンドチー
14が徐々に剥れてエキスパンドテープ4と半導体チッ
プ3とが剥離され、半導体チップ3はコレット1の吸着
口5に吸着され、この状態でダイホンディングが行われ
る。
By this conveyance, the semiconductor chip 3 is transferred to the suction port 5 of the collet 1.
When reaching the lower part, the push-up pins 2 push up the bottom surface of the expandable tape 4 and push up the semiconductor chip 3 in the direction of the suction port 5. As a result, the expanding chip 14 curves upward, and the semiconductor chip 3 is sucked toward the suction port of the collet 1 by the suction force of the collet 1. Therefore, the expanding chip 14 is gradually peeled off from the periphery of the lower surface of the semiconductor chip 3, and the expanding tape 4 and the semiconductor chip 3 are separated, and the semiconductor chip 3 is attracted to the suction port 5 of the collet 1, and in this state. Daihonding will be held.

ところで、ガリウムヒ素(Ga As > 、ガリウム
リン(GaP)などの化合物半導体からなる半導体チッ
プは、最近では1辺が約5M以上と大型化している。こ
のため、そのピックアップにおいては、突上げ時の衝撃
による半導体チップ3の割れを防止すると共に、半導体
チップ3を確実にコレット1の方向に突き上げる必要が
あるため、第4図に示す装置が使用される。この装置は
半導体チップ3の四隅部のそれぞれに当接する4本の突
上げピン2が設けられており、4本の突上げピン2がエ
キスパンドテープ4の下面から半導体チップ3の四隅部
を同時に突き上げるようになっている。これにより、突
上げ時の半導体チップ3への負荷が局所的に作用したす
せず、ピンの突き上げとコレット1によるピックアップ
時の応力が緩和される。
By the way, semiconductor chips made of compound semiconductors such as gallium arsenide (GaAs > gallium phosphide (GaP)) have recently become larger, with each side measuring approximately 5M or more. The device shown in FIG. 4 is used because it is necessary to prevent the semiconductor chip 3 from cracking due to impact and to reliably push the semiconductor chip 3 up in the direction of the collet 1. Four push-up pins 2 are provided that abut on each of the four push-up pins 2, and the four push-up pins 2 simultaneously push up the four corners of the semiconductor chip 3 from the bottom surface of the expandable tape 4. The stress applied locally to the semiconductor chip 3 during lifting is alleviated, and the stress when the pins are pushed up and picked up by the collet 1 is alleviated.

[発明が解決しようとする問題点] しかしながら、複数の突上げピン2を備えた従来装置に
おいては、全ての突上げピン2が同時に半導体チップ3
下面に当接するため、エキスパンドテープ4が半導体チ
ップ3の下面に完全に粘着した状態でコレット1に吸着
される。従って、半導体チップ3をエキスパンドチー7
4から剥離してピックアップするためには、コレット1
の吸引力を強くする必要があり、この吸引力により半導
体チップ3がコレット1の吸着口5で割れる頻度が多く
なっている。
[Problems to be Solved by the Invention] However, in a conventional device equipped with a plurality of push-up pins 2, all push-up pins 2 simultaneously touch the semiconductor chip 3.
Since the expandable tape 4 is in contact with the lower surface of the semiconductor chip 3, it is attracted to the collet 1 while completely adhering to the lower surface of the semiconductor chip 3. Therefore, the semiconductor chip 3 is expanded into the expanded chip 7.
In order to peel and pick up from 4, use collet 1.
It is necessary to increase the suction force of the collet 1, and this suction force causes the semiconductor chip 3 to break at the suction port 5 of the collet 1 more frequently.

なお、上記の事情は半導体チップの実装に限らず、チッ
プコンデンサやチップ抵抗の如き小型電子部品において
も生じる。すなわち、チップ状の小型電子部品が大型化
したり細長い板状になったりすると、エキスパンドテー
プの粘着力とコレットの吸引力で割れが生じてしまう。
Note that the above-mentioned situation occurs not only in the mounting of semiconductor chips but also in small electronic components such as chip capacitors and chip resistors. That is, when a small electronic component in the form of a chip increases in size or becomes an elongated plate, cracks occur due to the adhesive force of the expandable tape and the suction force of the collet.

そこで本発明は、大型のチップでも吸引力を強くするこ
となく、エキスパンドテープからの剥離が可能なチップ
実装装置を提供することを目的とする。
SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a chip mounting apparatus that can peel off even a large chip from an expandable tape without increasing the suction force.

[問題点を解決するための手段] 本発明に係るチップ実装装置は、エキスパンドテープ上
に接着されたチップの下面の周辺部分を突き上げる第1
の突上げ部材と、チップの下面の中央部分を支持する第
2の突上げ部材とを協え、第1の突上げ部材による突き
上げの後、第2の突上げ部材を突き上げ、その後に第1
の突上げ部材が下降するように制御されていることを特
徴とする。
[Means for Solving the Problems] The chip mounting apparatus according to the present invention includes a first
A push-up member and a second push-up member supporting the center portion of the lower surface of the chip are used together, and after the first push-up member pushes up, the second push-up member is pushed up, and then the first push-up member is pushed up.
The thrusting member is controlled to descend.

〔作用〕[Effect]

本発明に係るチップ実装装置は以上の通りに構成される
ので、第1の突上げ部材は衝撃を緩和した状態でチップ
の突き上げを行うように作用し、第2の突上げ部材はエ
キスパンドテープがチップの周辺部から剥れるようチッ
プを支持するように作用する。
Since the chip mounting apparatus according to the present invention is configured as described above, the first push-up member acts to push up the chip while reducing the impact, and the second push-up member acts to push up the chip with the expanded tape. It acts to support the chip so that it can be peeled off from the periphery of the chip.

〔実施例〕〔Example〕

以下、添付図面を参照して本発明のいくつかの実施例を
説明する。なお、図面の説明において同一の要素には同
一符号を付し、重複する説明を省略する。
Hereinafter, some embodiments of the present invention will be described with reference to the accompanying drawings. In addition, in the description of the drawings, the same elements are given the same reference numerals, and redundant description will be omitted.

第1図は実施例に係るチップ実装装置の一例として、半
導体素子実装装置の構成および作動を示す図である。図
示の通り、下部に吸着口12を有するコレット11が上
方に配され、コレット11は吸引手段(図示せず。)に
接続されている。コレット11の下方には複数の突上げ
ピンが上下動可能に設けられている。突上げピンは第1
図に示すように半導体チップ13に対し、その下面の四
隅部に当接する4本の外側突上げピン(第1の突上げ部
材)14と、下面中央部分に当接する4本の内側突上げ
ピン(第2の突上げ部材15)とからなっている。
FIG. 1 is a diagram showing the configuration and operation of a semiconductor element mounting apparatus as an example of a chip mounting apparatus according to an embodiment. As shown in the figure, a collet 11 having a suction port 12 at the bottom is disposed above, and the collet 11 is connected to suction means (not shown). A plurality of push-up pins are provided below the collet 11 so as to be movable up and down. The push-up pin is the first
As shown in the figure, with respect to the semiconductor chip 13, there are four outer push-up pins (first push-up members) 14 that come into contact with the four corners of the bottom surface of the semiconductor chip 13, and four inner push-up pins that come into contact with the center of the bottom surface. (second push-up member 15).

各突上げピン14.15はいずれも上端部が先鋭状に成
形されており、外側突上げピン14は全てが同時に上下
動し、内側突上げピン15も全てが同時に上下動するよ
うになっており、これらの上昇によってエキスバンドチ
ー116の下面から半導体チップ13をコレット11の
方向に突き上げるように作用する。ここで、1麦述する
ように外側突上げピン14がまず上昇し、次に内側突上
げピン15が上昇し、その後、外側突上げピン14が下
降するように制御されている。
Each of the push-up pins 14 and 15 has a sharp upper end, and the outer push-up pins 14 all move up and down at the same time, and the inner push-up pins 15 all move up and down at the same time. These rises act to push up the semiconductor chip 13 from the lower surface of the expanded chip 116 toward the collet 11. Here, as described above, the control is such that the outer push-up pin 14 first rises, then the inner push-up pin 15 rises, and then the outer push-up pin 14 descends.

次に、本実施例に係る実装装置の作動を説明する。Next, the operation of the mounting apparatus according to this embodiment will be explained.

半導体ウェーハのダイシングによって半導体チップ13
は個々に分割され、エキスバンドチー116上に接着さ
れた状態でコレット11と突上げピン14.15との間
に搬送される。この搬送で半導体チップ13がコレット
11の吸着口12の下方に達すると、第1図(a>のよ
うに外側突上げピン14が上昇し、エキスパンドテープ
16の下面から半導体チップ13の下面の四隅部に同時
に当接し、半導・体チップ13をコレット11の方向に
突き上げる。この突き上げは、全ての外側突上げピン1
4が同時に半導体チップ13下面に当接することにより
なされるので、その衝撃が緩和され、突き上げによる半
導体チップ13の割れが防止される。外側突上げピン1
4の突上げにより、半導体チップ13はエキスパンドテ
ープ16が接着した状態でコレット11の吸着口13に
吸着される。
Semiconductor chips 13 are formed by dicing a semiconductor wafer.
are divided into individual parts, and are conveyed between the collet 11 and the push-up pins 14, 15 while being glued onto the expanding band chi 116. When the semiconductor chip 13 reaches below the suction port 12 of the collet 11 during this conveyance, the outer push-up pins 14 rise as shown in FIG. The semiconductor chip 13 is pushed up in the direction of the collet 11.
4 simultaneously abut against the lower surface of the semiconductor chip 13, the impact is alleviated and cracking of the semiconductor chip 13 due to pushing up is prevented. Outer push-up pin 1
4, the semiconductor chip 13 is attracted to the suction port 13 of the collet 11 with the expanded tape 16 adhered thereto.

次に゛、第1図(b)に示すように、内側突上げピン1
5が上昇し、エキスパンドテープ16の下面から半導体
チップ13の下面の中央部分に当接する。この当接まで
の間は、半導体チップ13は外側突上げピン14によっ
て支持されており、内側突上げピン15がエキスパンド
テープ16に当接すると、第1図(C)のように外側突
上げピン14は下降してエキスパンドテープ16から離
脱する。これにより、半導体チップ13は内側突上げピ
ン15によって中央部部のみが支持された状態となり、
エキバンドチー116は半導体チップ13の周辺部分か
ら中央部部に向って徐々に剥れる。そして、内側突上げ
ピン15が下降すると、すでに粘着面が減少しているの
で全体として粘着力が弱く、最終的には半導体チップ1
3下面全体から剥離する。従って、エキスバンドチー1
16が容易に剥離されるので、コレット11の吸引力を
強くする必要がなく、半導体チップ13が過度の吸引力
で吸着されることがないので、コレット11への吸着時
の割れも防止することができる。
Next, as shown in Fig. 1(b), the inner push-up pin 1
5 rises and contacts the center portion of the bottom surface of the semiconductor chip 13 from the bottom surface of the expandable tape 16. Until this contact, the semiconductor chip 13 is supported by the outer push-up pin 14, and when the inner push-up pin 15 comes into contact with the expandable tape 16, the outer push-up pin 14 descends and separates from the expanded tape 16. As a result, the semiconductor chip 13 is in a state where only the central portion is supported by the inner push-up pins 15.
The extrusion band 116 gradually peels off from the periphery of the semiconductor chip 13 toward the center. When the inner push-up pin 15 descends, the adhesive surface has already decreased, so the adhesive force as a whole is weak, and eventually the semiconductor chip 1
3 Peel off from the entire bottom surface. Therefore, extract band 1
Since the chip 16 is easily peeled off, there is no need to increase the suction force of the collet 11, and the semiconductor chip 13 is not attracted by excessive suction force, thereby preventing cracking when adsorbed to the collet 11. Can be done.

このような半導体チップのピックアップは、ガリウムヒ
素からなる化合物半導体であれば、厚さ主に対する1辺
の長さgの比率N/lが10以上の大型半導体素子に特
に有効であり、またシリコン単結晶であれば上記比率が
15以上の大型半導体チップに特に有効となっている。
This type of pickup of semiconductor chips is particularly effective for large semiconductor devices with a ratio of the length of one side g to the main thickness N/l of 10 or more for compound semiconductors made of gallium arsenide, and for compound semiconductors made of gallium arsenide. If it is a crystal, it is particularly effective for large semiconductor chips with the above ratio of 15 or more.

第2図は本発明の別の実施例の斜視図を示している。FIG. 2 shows a perspective view of another embodiment of the invention.

同図(a>の装置では、外側の円筒体17と内側の円形
軸体 18とによって突上げ部材が構成されている。また同図
(b)においては、外側の筒体19と内側の軸体20と
が矩形状に成形され、同図(C)では矩形状の外側の筒
体21に対して内側の軸体22が円形に成形されている
In the device shown in the figure (a), the push-up member is constituted by an outer cylinder 17 and an inner circular shaft 18. In addition, in the figure (b), an outer cylinder 19 and an inner circular shaft 18 constitute a thrusting member. The body 20 is formed into a rectangular shape, and in the figure (C), the inner shaft body 22 is formed into a circular shape with respect to the rectangular outer cylinder body 21.

これらの実施例においては、外側の筒体]7゜19.2
1がエキスパンドテープ16下面から半導体チップ13
の周辺部分に当接し、半導体チップ13をコレット11
方向に突き上げるものでおり、前述の実施例にあける外
側突上げピン(第1の突上げ部材)]4に相当する。ま
た、内側の軸体18,20.22は半導体チップ13の
中央部分に当接してエキスバンドチー716の剥離時の
半導体チップ13の支持を行なうものであり、前述の実
施例における内側突上げピン(第2の突上げ部材)15
に相当する。従って、このような筒体17,19.21
および軸体18,20.22の組み合わせによっても、
割れが生じることのない半導体チップのピックアップが
可能となる。
In these embodiments, the outer cylinder]7°19.2
1 is the semiconductor chip 13 from the bottom surface of the expanded tape 16
collet 11, and the semiconductor chip 13 is brought into contact with the peripheral part of the collet 11.
It pushes up in the direction, and corresponds to the outer push-up pin (first push-up member)]4 provided in the above-mentioned embodiment. Further, the inner shaft bodies 18, 20.22 are in contact with the center portion of the semiconductor chip 13 to support the semiconductor chip 13 when the expansion chip 716 is peeled off, and are similar to the inner push-up pins in the above-described embodiment. (Second push-up member) 15
corresponds to Therefore, such cylinders 17, 19, 21
And also by the combination of shaft bodies 18, 20.22,
It becomes possible to pick up semiconductor chips without causing cracks.

本発明は上記実施例に限定されるものではなく、種々の
変形が可能である。
The present invention is not limited to the above embodiments, and various modifications are possible.

例えば、半導体チップの周辺部分を突き上げる外側突上
げピンは、衝撃を緩和した状態で半導体チップをコレッ
ト方向に突き上げるものでおるから、その本数は5本以
上であってもよい。また、半導体チップの中央部分を支
持する内側突上げピンは半導体チップがコレットに吸着
されているところから、その本数は少なくてもよく、2
本、3本であってもよい。ざらに、内側の突上げピンと
筒体あるいは外側の突上げピンと軸体とを組み合わせて
もよい。
For example, the number of outer push-up pins that push up the peripheral portion of the semiconductor chip may be five or more, since the outer push-up pins push up the semiconductor chip toward the collet while reducing the impact. In addition, since the semiconductor chip is attracted to the collet, the number of inner push-up pins that support the central part of the semiconductor chip may be small;
It may be three books. Alternatively, the inner push-up pin and the cylindrical body or the outer push-up pin and the shaft body may be combined.

本発明はエキスパンドテープから半導体チップをピック
アップするもののみならず、各種のチップ状小型部品(
例えばチップコンデンサ、チップ抵抗等)のピックアッ
プにも適用できる。
The present invention is applicable not only to picking up semiconductor chips from expanded tape, but also to various small chip-shaped parts (
For example, it can also be applied to pickup of chip capacitors, chip resistors, etc.).

〔発明の効果〕〔Effect of the invention〕

以上、詳細に説明した通り、本発明に係るチップ実装装
置によれば、チップの周辺部分を突き上げる第1の突上
げ部材と、その突上げの後、チップの中央部分を支持す
る第2の突上げ部材とから構成されるので、突上げ時の
衝撃が緩和され、またエキスパンドテープが容易に剥離
されるようにする。このため、大型のチップでもコレッ
トの吸引力を強くする必要がなく、ピックアップの際の
チップの割れが防止でき、歩密りが向上する効果がある
As described above in detail, the chip mounting apparatus according to the present invention includes a first push-up member that pushes up the peripheral portion of the chip, and a second push-up member that supports the central portion of the chip after the push-up. Since it is composed of a lifting member, the impact at the time of lifting is alleviated, and the expandable tape is easily peeled off. Therefore, there is no need to increase the suction force of the collet even when the chip is large, and cracking of the chip during pickup can be prevented, which has the effect of improving the pick-up rate.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明に係る半導体素子実装装置の作動を示す
一部破断側面図、第2図は別の実施例の斜視図、第3図
および第4図は従来装置の斜視図である。 11・・・]コレット13・・・半導体素子、14・・
・外側の突上げピン(第1の突上げ部材)、15・・・
内側の突上げピン(第2の突上げ部材)、16・・・エ
キスパンドテープ、17,19,21・・・筒体(第1
の突上げ部材>、18,20.22・・・軸体(第2の
突上げ部材)。 特許出願人  住友電気工業株式会社 代理人弁理士   長谷用  芳  側径   来  
 例 第  4  図 施   例 1図
FIG. 1 is a partially cutaway side view showing the operation of a semiconductor element mounting apparatus according to the present invention, FIG. 2 is a perspective view of another embodiment, and FIGS. 3 and 4 are perspective views of a conventional apparatus. 11...] Collet 13... Semiconductor element, 14...
・Outer push-up pin (first push-up member), 15...
Inner push-up pin (second push-up member), 16... Expand tape, 17, 19, 21... Cylindrical body (first
push-up member>, 18, 20. 22... shaft body (second push-up member). Patent applicant: Sumitomo Electric Industries, Ltd. Representative Patent Attorney Yoshi Hase
Example 4 Figure 1 Example 1

Claims (1)

【特許請求の範囲】 1、エキスパンドテープ上に接着されたチップを前記エ
キスパンドテープの下面からコレツト方向に突き上げる
チップ実装装置において、前記チップの下面の周辺部分
を突き上げる第1の突上げ部材と、 前記チップの下面の中央部分を支持する第2の突上げ部
材とを備え、 前記第1の突上げ部材による突き上げの後に前記第2の
突上げ部材を突き上げ、その後に前記第1の突上げ部材
が下降するように制御されていることを特徴とするチッ
プ実装装置。 2、前記第1の突上げ部材は前記チップの四隅部を突き
上げる少なくとも4本のピンである特許請求の範囲第1
項記載のチップ実装装置。 3、前記第2の突上げ部材は前記チップの中央部を支持
する少なくとも2本のピンである特許請求の範囲第1項
記載のチップ実装装置。 4、前記第1の突上げ部材は前記チップの周辺部全体に
当接する筒体である特許請求の範囲第1項記載のチップ
実装装置。 5、前記第2の突上げ部材は前記チップの中央部に当接
する軸体である特許請求の範囲第1項記載のチップ実装
装置。
[Scope of Claims] 1. In a chip mounting apparatus that pushes up a chip bonded on an expanding tape from the lower surface of the expanding tape toward the collector, a first pushing-up member that pushes up a peripheral portion of the lower surface of the chip; a second push-up member that supports a central portion of the lower surface of the chip, the second push-up member is pushed up after the first push-up member is pushed up, and then the first push-up member is pushed up; A chip mounting device characterized in that it is controlled to descend. 2. Claim 1, wherein the first pushing-up member is at least four pins pushing up the four corners of the chip.
Chip mounting equipment as described in section. 3. The chip mounting apparatus according to claim 1, wherein the second pushing-up member is at least two pins that support the center portion of the chip. 4. The chip mounting apparatus according to claim 1, wherein the first pushing-up member is a cylindrical body that comes into contact with the entire periphery of the chip. 5. The chip mounting apparatus according to claim 1, wherein the second pushing-up member is a shaft body that comes into contact with the center portion of the chip.
JP62091281A 1987-04-14 1987-04-14 Chip mounting equipment Pending JPS63255937A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62091281A JPS63255937A (en) 1987-04-14 1987-04-14 Chip mounting equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62091281A JPS63255937A (en) 1987-04-14 1987-04-14 Chip mounting equipment

Publications (1)

Publication Number Publication Date
JPS63255937A true JPS63255937A (en) 1988-10-24

Family

ID=14022074

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62091281A Pending JPS63255937A (en) 1987-04-14 1987-04-14 Chip mounting equipment

Country Status (1)

Country Link
JP (1) JPS63255937A (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0322458A (en) * 1989-06-19 1991-01-30 Nec Kyushu Ltd Pickup device
JPH0623299U (en) * 1992-08-26 1994-03-25 株式会社カイジョー Semiconductor component supply device
JP2005117019A (en) * 2003-09-17 2005-04-28 Renesas Technology Corp Method of manufacturing semiconductor device
JP2007115934A (en) * 2005-10-21 2007-05-10 Matsushita Electric Ind Co Ltd Electronic component knocking-up device and method for feeding electronic component
JP2007158103A (en) * 2005-12-06 2007-06-21 Shibuya Kogyo Co Ltd Chip push-up device
JP2008192736A (en) * 2007-02-02 2008-08-21 Shibaura Mechatronics Corp Chip mounting apparatus, adhesive sheet for semiconductor wafer processing, and chip mounting method
JP2010092905A (en) * 2008-10-03 2010-04-22 Renesas Technology Corp Method of picking up semiconductor chip and method of manufacturing semiconductor device
JP2010135544A (en) * 2008-12-04 2010-06-17 Canon Machinery Inc Delamination equipment and delamination method
JP2010192648A (en) * 2009-02-18 2010-09-02 Canon Machinery Inc Debonding apparatus and debonding method
JP2012004393A (en) * 2010-06-17 2012-01-05 Hitachi High-Tech Instruments Co Ltd Die bonder and pickup method and pickup device
JP2012199461A (en) * 2011-03-23 2012-10-18 Hitachi High-Tech Instruments Co Ltd Die bonder
JP2013034001A (en) * 2012-10-25 2013-02-14 Hitachi High-Tech Instruments Co Ltd Die bonder, pickup method, and pickup device
JP2013065628A (en) * 2011-09-15 2013-04-11 Hitachi High-Tech Instruments Co Ltd Die bonder and die pickup device and die pickup method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57136341A (en) * 1982-01-13 1982-08-23 Hitachi Ltd Removing method for part from sheet
JPS60257537A (en) * 1984-06-04 1985-12-19 Shinkawa Ltd Die bonding apparatus
JPS6129145A (en) * 1984-07-20 1986-02-10 Hitachi Ltd Picking up method and jig therefor
JPS6144842A (en) * 1984-07-18 1986-03-04 シエリング・コ−ポレ−シヨン Inhibitor of slow reaction anaphylactic substance
JPS61267656A (en) * 1985-05-20 1986-11-27 Matsushita Electric Ind Co Ltd Pushing up and absorbing device for electron parts

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57136341A (en) * 1982-01-13 1982-08-23 Hitachi Ltd Removing method for part from sheet
JPS60257537A (en) * 1984-06-04 1985-12-19 Shinkawa Ltd Die bonding apparatus
JPS6144842A (en) * 1984-07-18 1986-03-04 シエリング・コ−ポレ−シヨン Inhibitor of slow reaction anaphylactic substance
JPS6129145A (en) * 1984-07-20 1986-02-10 Hitachi Ltd Picking up method and jig therefor
JPS61267656A (en) * 1985-05-20 1986-11-27 Matsushita Electric Ind Co Ltd Pushing up and absorbing device for electron parts

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0322458A (en) * 1989-06-19 1991-01-30 Nec Kyushu Ltd Pickup device
JPH0623299U (en) * 1992-08-26 1994-03-25 株式会社カイジョー Semiconductor component supply device
JP4574251B2 (en) * 2003-09-17 2010-11-04 ルネサスエレクトロニクス株式会社 Manufacturing method of semiconductor device
JP2005117019A (en) * 2003-09-17 2005-04-28 Renesas Technology Corp Method of manufacturing semiconductor device
JP2007115934A (en) * 2005-10-21 2007-05-10 Matsushita Electric Ind Co Ltd Electronic component knocking-up device and method for feeding electronic component
JP2007158103A (en) * 2005-12-06 2007-06-21 Shibuya Kogyo Co Ltd Chip push-up device
JP2008192736A (en) * 2007-02-02 2008-08-21 Shibaura Mechatronics Corp Chip mounting apparatus, adhesive sheet for semiconductor wafer processing, and chip mounting method
JP2010092905A (en) * 2008-10-03 2010-04-22 Renesas Technology Corp Method of picking up semiconductor chip and method of manufacturing semiconductor device
JP2010135544A (en) * 2008-12-04 2010-06-17 Canon Machinery Inc Delamination equipment and delamination method
JP2010192648A (en) * 2009-02-18 2010-09-02 Canon Machinery Inc Debonding apparatus and debonding method
JP2012004393A (en) * 2010-06-17 2012-01-05 Hitachi High-Tech Instruments Co Ltd Die bonder and pickup method and pickup device
JP2012199461A (en) * 2011-03-23 2012-10-18 Hitachi High-Tech Instruments Co Ltd Die bonder
JP2013065628A (en) * 2011-09-15 2013-04-11 Hitachi High-Tech Instruments Co Ltd Die bonder and die pickup device and die pickup method
JP2013034001A (en) * 2012-10-25 2013-02-14 Hitachi High-Tech Instruments Co Ltd Die bonder, pickup method, and pickup device

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