JP2010092905A - Method of picking up semiconductor chip and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of picking up a semiconductor chip, capable of reducing a time required for picking up the semiconductor chip. <P>SOLUTION: A dicing sheet DS having a pasting region where a semiconductor chip CP is pasted and a surrounding region for surrounding the pasting region is prepared. The semiconductor chip CP is pushed up via the pasting region while fixing the surrounding region. When the semiconductor chip CP is pushed up, peeling between the outer periphery of the semiconductor chip CP and the dicing sheet DS is detected based on the measurement for displacement of the outer periphery of the semiconductor chip CP. After the peeling is detected, the semiconductor chip CP is peeled from the dicing sheet DS. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor chip pickup method and a semiconductor device manufacturing method.

  In a manufacturing method of a semiconductor device, a process of dicing a wafer attached to an adhesive sheet into a plurality of semiconductor chips and a process of sequentially picking up each semiconductor chip from the adhesive sheet are widely performed. In this pickup process, for example, the semiconductor chip is sucked from above using an adsorption collet, and the semiconductor chip is pushed up from below using a push-up pin.

For example, in a semiconductor manufacturing apparatus according to Japanese Patent Laid-Open No. 09-036147 (Patent Document 1), a push-up means for pushing up a semiconductor chip with a push-up pin, a detection means for detecting a load applied to the push-up pin, and a load applied to the push-up pin are preset. Control means for continuing the push-up operation until the upper limit load value is reached. The semiconductor manufacturing apparatus further includes means for picking up the semiconductor chip after the load value applied to the push-up pin is reduced to a preset lower limit load value.
Japanese Unexamined Patent Publication No. 09-036147

  In the above technique, each of the upper limit load value and the lower limit load value used for process control is a preset value. This preset value needs to be given a safety margin in consideration of process variations. As a result, the semiconductor chip may be pushed up unnecessarily for a long time, so that the time required for picking up the semiconductor chip becomes long, resulting in a problem that the manufacturing efficiency of the semiconductor device is lowered.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a method of picking up a semiconductor chip that can shorten the time required for picking up the semiconductor chip. Another object of the present invention is to provide a method for manufacturing a semiconductor device having high manufacturing efficiency.

  According to one embodiment of the present invention, a method for picking up a semiconductor chip includes the following steps.

  First, a sheet having a pasting area where a semiconductor chip is pasted and a surrounding area surrounding the pasting area is prepared. The semiconductor chip is pushed up through the pasting area while fixing the surrounding area. When the semiconductor chip is pushed up, peeling between the outer peripheral portion of the semiconductor chip and the sheet is detected based on the measurement related to the displacement of the outer peripheral portion of the semiconductor chip. After the peeling is detected, the semiconductor chip is separated from the sheet.

  According to another embodiment of the present invention, a semiconductor chip pickup method includes the following steps.

  First, a sheet having a pasting area where a semiconductor chip is pasted and a surrounding area surrounding the pasting area is prepared. The semiconductor chip is pushed up through the pasting area while fixing the surrounding area. When the semiconductor chip is pushed up, peeling between the outer peripheral portion of the semiconductor chip and the sheet is detected based on the measurement related to the force pushing up the semiconductor chip. After the peeling is detected, the semiconductor chip is separated from the sheet.

  According to the one embodiment described above, the separation between the outer peripheral portion of the semiconductor chip and the sheet is detected with high accuracy based on the measurement related to the displacement of the outer peripheral portion of the semiconductor chip. Therefore, it is possible to avoid the pushing up being performed unnecessarily for a long time, so that the time required for picking up the semiconductor chip can be shortened. Thereby, the manufacturing efficiency of the semiconductor device can be increased.

  According to the other embodiment described above, the separation between the outer peripheral portion of the semiconductor chip and the sheet is detected with high accuracy based on the measurement related to the force for pushing up the semiconductor chip. Therefore, it is possible to avoid the pushing up being performed unnecessarily for a long time, so that the time required for picking up the semiconductor chip can be shortened. Thereby, the manufacturing efficiency of the semiconductor device can be increased.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
FIG. 1 is a cross-sectional view schematically showing a configuration of a semiconductor device according to the first embodiment of the present invention. Referring to FIG. 1, the semiconductor device of the present embodiment is of a lead frame type, and includes die pad DP, DAF (Die Attach Film) 81, semiconductor chip CP, wire WR, and mold resin MRa. And an external lead OL.

  FIG. 2 is a flowchart schematically showing the semiconductor device manufacturing method according to the first embodiment of the present invention. Referring to FIG. 2, in step S100, a wafer on which semiconductor chips CP are formed is prepared. A DAF 81 and a dicing sheet are attached to the wafer in order. Next, the wafer and DAF 81 are diced on a dicing sheet. In step S200, the semiconductor chip CP to which the DAF 81 is attached is picked up. In step S300, the picked-up semiconductor chip CP is bonded to the die pad DP of the lead frame via the DAF 81. Thereafter, the semiconductor chip CP and the external lead OL are electrically connected by the wire WR. In step S400, the semiconductor chip CP and the wire WR are sealed with the mold resin MRa. Thereby, the semiconductor device of the present embodiment is obtained.

  FIG. 3 is a cross-sectional view schematically showing the semiconductor chip pickup device according to the first embodiment of the present invention together with the semiconductor chip and the dicing sheet. 4 is a plan view schematically showing the positional relationship between the semiconductor chip and dicing sheet and the pickup device in FIG.

  Referring to FIGS. 3 and 4, the pickup device of the present embodiment is a device for separating semiconductor chip CP from dicing sheet DS. The dicing sheet DS is a sticking area where the semiconductor chip CP is attached via the DAF 81 (an area hidden under the semiconductor chip CP in FIG. 4) and an surrounding area surrounding the sticking area (exposed in FIG. 4). Region). The pickup device of the present embodiment includes a laser displacement meter LD, a chip position measuring device 51a, a controller 52a, first to third pieces P1 to P3, a vacuum stage 60, a vertical drive device 64, A vacuum sealing 63 and a suction head 53 are provided.

  The laser displacement meter LD is a device for measuring the displacement of the measurement target by irradiating the measurement target with the laser beam LL. The laser displacement meter LD is arranged so that the laser beam LL is irradiated on the outer peripheral portion of the semiconductor chip CP. The laser displacement meter LD is, for example, a displacement meter based on a Z-axis scanning method. The chip position measuring device 51a is a device that calculates the position of the measurement object of the laser displacement meter LD based on the signal from the laser displacement meter LD. Therefore, the displacement of the outer peripheral portion of the semiconductor chip CP can be measured by the chip position measuring device 51a.

  The controller 52a is a device for controlling the vertical drive device 64 based on the measurement result of the displacement of the outer peripheral portion of the semiconductor chip CP output from the chip position measuring device 51a. The vertical drive device 64 is a device for driving each of the first to third pieces P1 to P3 up and down.

  The inside of the vacuum stage 60 is in a low pressure state by being evacuated as indicated by an arrow 62. The vacuum stage 60 has a through hole 61 at a position facing the dicing sheet DS. With this configuration, the dicing sheet DS can be fixed to the vacuum stage 60 in the through hole 61. Thereby, the surrounding region of the dicing sheet DS located around the semiconductor chip CP to be picked up can be fixed.

  The suction head 53 has a function of fixing the semiconductor chip CP to the suction head 53 by sucking the semiconductor chip CP and a function of transporting the semiconductor chip CP by moving the suction head 53. The suction head 53 has a function of controlling the position so that the load applied to the semiconductor chip CP becomes constant when the semiconductor chip CP is pushed up from below.

  FIG. 5 is a flowchart schematically showing the semiconductor chip pickup method according to the first embodiment of the present invention. 6 to 9 are cross-sectional views schematically showing first to fourth steps of the semiconductor chip pickup method according to the first embodiment of the present invention. Referring mainly to FIGS. 5 to 9, the pickup process in step S <b> 200 (FIG. 2) includes steps S <b> 210 to S <b> 260 described below.

  In step S210, the suction head 53 moves onto the semiconductor chip CP, and the semiconductor chip CP is fixed by suction. The semiconductor chip CP (FIG. 6) placed on the vacuum stage 60 via the dicing sheet DS and the DAF 81 is pushed up by the first to third pieces P1 to P3 (FIG. 7). That is, as the positions of the first to third pieces P1 to P3 in FIG. 4 rise, the portion surrounded by the outer peripheral portion of the semiconductor chip CP is pushed up. The suction head 53 performs position control so that the load applied to the semiconductor chip CP is constant.

  In step S220, it is determined whether or not the outer periphery of the semiconductor chip CP is peeled off. In step S230, if the determination result is no peeling, step S210 is continued. On the other hand, in step S230, when the determination result is peeling, that is, when peeling between the outer peripheral portion of the semiconductor chip CP and the dicing sheet DS as shown in FIG. 7 is detected, the process proceeds to step S240. The

  In step S240, the semiconductor chip CP is pushed up by the second and third pieces P2, P3 (FIG. 8). That is, some of the portions pushed up by the first to third pieces P1 to P3 are selectively pushed up further. Next, in step S250, the semiconductor chip CP is pushed up by the third piece P3 (FIG. 9). That is, some of the portions pushed up by the second and third pieces P2 and P3 are selectively pushed up further. The suction head 53 performs position control so that the load applied to the semiconductor chip CP is always constant during steps S240 and S250.

  In step S260, the suction head 53 moves to separate the semiconductor chip CP from the dicing sheet DS.

Thus, the pick-up process in step S200 (FIG. 2) is performed.
Next, the step of determining whether or not there is peeling in step S220 (FIG. 5) in the pickup step of step S200 (FIG. 2) will be described in detail. FIG. 10 is a flowchart schematically showing a process for determining the presence or absence of peeling in the semiconductor chip pickup method according to the first embodiment of the present invention. Each of FIGS. 11 to 14 is a cross-sectional view schematically showing first to fourth steps of a peeling presence / absence determination step in the semiconductor chip pickup method according to the first embodiment of the present invention. Referring mainly to FIGS. 10 to 14, the peeling presence / absence determination step in step S <b> 220 (FIG. 5) includes steps S <b> 221 a to S <b> 224 a described below.

  In step S221a, the first piece P1 starts to rise as shown by the arrow in FIG. When the first piece P1 is raised, the second and third pieces P2, P3 are raised together with the first piece P1, as shown in FIG. As shown in FIG. 11, the laser beam LL is irradiated from the laser displacement meter LD to the outer peripheral portion of the semiconductor chip CP. Thereby, the measurement of the displacement of the outer peripheral portion of the semiconductor chip CP is started. As the first piece P1 rises, the position of the upper surface of the vacuum stage 60 becomes lower than the position of the upper surface of the first piece P1, as shown in FIG. A downward tension T1T is applied. The tension T1T has a downward tension vertical component T1V in addition to the horizontal tension component T1P along the surface of the dicing sheet DS. Due to the tension vertical component T1V, the outer peripheral portion of the semiconductor chip CP bends downward by the bend BD.

  In step S222a, it is determined whether or not the displacement of the outer peripheral portion of the semiconductor chip CP matches the displacement of the first to third pieces P1 to P3.

  As shown in FIG. 12, when the dicing sheet DS is not peeled off from the semiconductor chip CP to which the DAF 81 is attached, the displacement of the outer peripheral portion of the semiconductor chip CP is compared with the displacement of the first to third pieces P1 to P3. And it is small by the amount of the deflection BD. That is, the displacement of the outer peripheral portion of the semiconductor chip CP does not coincide with the displacement of the first to third pieces P1 to P3. Therefore, it is determined in step S223a that there is no peeling.

  On the other hand, when the peeling of the dicing sheet DS proceeds as indicated by the broken line arrow in FIG. 13, the outer peripheral portion of the semiconductor chip CP is not bent as indicated by the solid line arrow in FIG. Thereby, as shown in FIG. 14, the displacement of the outer peripheral portion of the semiconductor chip CP coincides with the displacement of the first to third pieces P1 to P3. Therefore, it is determined that there is peeling in step S224a.

The determination process of the presence or absence of peeling of step S220 (FIG. 5) is thus performed.
FIG. 15 is an example showing a temporal change in the height of the outer peripheral portion of the semiconductor chip in the semiconductor chip pick-up process. Referring mainly to FIG. 15, height Ha <b> 1 is an example showing a temporal change in the height of the outer peripheral portion of semiconductor chip CP in the present embodiment. The height Ha2 is an example showing a change in the height of the outer peripheral portion of the semiconductor chip CP when a sample once peeled off from the dicing sheet DS in the outer peripheral portion of the semiconductor chip CP is subjected again to the pick-up process. The difference DF is a value obtained by subtracting the height Ha1 from the height Ha2. In this example, a sharp increase in the height Ha1 of the outer peripheral portion of the semiconductor chip CP was clearly observed about 28 ms after the start of the process. At this moment, it is considered that the outer peripheral portion of the semiconductor chip CP as shown by the solid line arrow in FIG. 13, that is, the dicing sheet DS is peeled off from the outer peripheral portion of the semiconductor chip CP.

  Next, the peeling phenomenon of the dicing sheet DS when the thickness of the semiconductor chip CP exceeds 150 μm and when the thickness is 150 μm or less will be described below.

  Each of FIGS. 16 to 18 is a cross-sectional view schematically showing first to third steps of peeling the dicing sheet at the outer peripheral portion of the semiconductor chip having a thickness exceeding 150 μm.

  Referring to FIG. 16, length L1 is the distance between the outer edges of semiconductor chip CP and vacuum stage 60 in plan view, and length L2 is each of first piece P1 and vacuum stage 60 in plan view. The distance between the outer edges. The position z is a relative height position of the upper surface of the vacuum stage 60 with respect to the upper surface of the first piece P1. Since z = 0 in the initial state, no vertical tension acts on the dicing sheet DS.

  Referring to FIG. 17, the first piece P1 pushes up the semiconductor chip CP. As a result, the upper surface of the first piece P1 is raised, so that the position of the upper surface of the vacuum stage 60 is lower than the position of the upper surface of the first piece P1, so that the tension is directed obliquely downward with respect to the dicing sheet DS. T1T is added. The tension T1T has a downward tension vertical component T1V in addition to the horizontal tension component T1P along the surface of the dicing sheet DS. Each of the tension T1T and the tension vertical component T1V is expressed by the following equations (1) and (2), where K is the sheet elasticity (Hook) coefficient.

  Although the outer peripheral portion of the semiconductor chip CP is bent downward by the tension vertical component T1V, the bending is small when the thickness of the semiconductor chip CP exceeds 150 μm. For this reason, it is relatively difficult to reliably detect this bending by the laser displacement meter LD. The tension vertical component T1V acts as a force for peeling the dicing sheet DS from the semiconductor chip CP to which the DAF 81 is attached, that is, a peeling force at the edge of the semiconductor chip CP.

  With reference to FIG. 18, when the push-up by the first piece P <b> 1 is continued, the dicing sheet DS is peeled off at the outer periphery of the semiconductor chip CP. As a result, the tension of the dicing sheet DS changes from the tension T1T (formula (1)) to the tension T2T shown in the following formula (3).

  FIG. 19 is a diagram showing the relationship between the relative height position of the upper surface of the vacuum stage relative to the upper surface of the first piece and the peeling force. Referring to FIG. 19, as z increases, the peeling force corresponding to tension vertical component T1V also increases, and eventually reaches the sheet adhesive force. As a result, the dicing sheet DS is peeled off at the outer peripheral portion of the semiconductor chip CP, whereby the peeling force changes to a force corresponding to the tension vertical component T2V. That is, the peeling force decreases rapidly.

  20 to 22 are cross-sectional views schematically showing first to third steps of peeling the dicing sheet at the outer peripheral portion of the semiconductor chip having a thickness of 150 μm or less.

  Referring mainly to FIG. 20, in the initial state, as in the case shown in FIG. 16 above, no vertical tension acts on the dicing sheet DS.

  Referring to FIG. 21, the first piece P1 pushes up the semiconductor chip CP. As a result, the upper surface of the first piece P1 is raised, so that the position of the upper surface of the vacuum stage 60 is lower than the position of the upper surface of the first piece P1, so that the tension is directed obliquely downward with respect to the dicing sheet DS. T1T is added. Each of the tension T1T and the tension vertical component T1V is represented by the following expressions (4) and (5) instead of the above expressions (1) and (2).

  The boundary conditions in each of the equations (4) and (5) are as follows, where the coefficient determined by the beam condition is a coefficient β, the second moment of section is l, and the elastic modulus is E: It is represented by (7).

  The outer peripheral portion of the semiconductor chip CP bends downward by the bend BD due to the tension vertical component T1V shown in Expression (5). When the thickness of the semiconductor chip CP is 150 μm or less, the deflection BD is relatively large and can be easily detected by the laser displacement meter LD. The tension vertical component T1V acts as a force for peeling the dicing sheet DS from the semiconductor chip CP to which the DAF 81 is attached, that is, a peeling force at the edge of the semiconductor chip CP.

  With reference to FIG. 22, when the push-up by the first piece P <b> 1 is continued, the dicing sheet DS is peeled off at the outer periphery of the semiconductor chip CP. As a result, the tension of the dicing sheet DS changes from the tension T1T (formula (4)) to the tension T2T shown in the formula (3).

  According to the present embodiment, in the step shown in FIG. 10, the outer peripheral portion of the semiconductor chip CP and the dicing sheet are measured based on the measurement of the displacement of the outer peripheral portion of the semiconductor chip CP by the laser displacement meter LD (FIGS. 11 to 14). Separation with the DS is detected with high accuracy. Therefore, it is possible to prevent the pushing-up (FIG. 7) of step S210 (FIG. 5) from being performed for an unnecessarily long time, so that the pushing-up (FIG. 8) of step S240 (FIG. 5) can be started earlier. it can. Therefore, since the time required for the pickup in step S200 (FIG. 2) can be shortened, the manufacturing efficiency of the semiconductor device (FIG. 1) can be increased.

(Embodiment 2)
FIG. 23 is a cross sectional view schematically showing a configuration of the semiconductor device in the second embodiment of the present invention. Referring to FIG. 23, the semiconductor device of the present embodiment is a BGA (Ball Grid Array) package, and includes a resin substrate RS, DAF 81, semiconductor chip CP, wire WR, mold resin MRb, and solder ball. (External terminal) SLb. Resin substrate RS and solder ball SLb constitute a BGA substrate.

Next, a method for manufacturing the semiconductor device of the present embodiment will be described.
Referring to FIG. 2, steps S100 and S200 are performed in the same manner as in the first embodiment. In step S300, the picked-up semiconductor chip CP is bonded to the resin substrate RS via the DAF 81. Thereafter, the semiconductor chip CP and the resin substrate RS are electrically connected by the wire WR. In step S400, semiconductor chip CP and wire WR are sealed with mold resin MRb, and solder ball SLb is formed by reflow. Thereby, the semiconductor device of the present embodiment is obtained.

  Since the configuration other than the above is substantially the same as the configuration of the first embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof is not repeated. In the present embodiment, the same effect as in the first embodiment can be obtained.

(Embodiment 3)
FIG. 24 is a cross sectional view schematically showing a configuration of the semiconductor device in the third embodiment of the present invention. Referring to FIG. 24, the semiconductor device of the present embodiment is a stacked SIP (System In Package), which includes a resin substrate RS, DAF 81, solder balls SLf, SLs, semiconductor chips CPf, CPs, and wires. It has WR and mold resin MRc. The semiconductor chip CPf is, for example, a microcomputer chip (electronic component), and the semiconductor chip CPs is, for example, a memory chip.

Next, a method for manufacturing the semiconductor device of the present embodiment will be described.
First, the semiconductor chip CPf is mounted on the resin substrate RS via the solder balls SLf. Next, referring to FIG. 2, steps S100 and S200 are performed in the same manner as in the first embodiment. In step S300, the picked-up semiconductor chip CPs is bonded to the semiconductor chip CPf by the DAF 81. Thereafter, the semiconductor chip CPs and the resin substrate RS are electrically connected by the wire WR. In step S400, semiconductor chips CPf, CPs, wires WR, and solder balls SLf are sealed with mold resin MRc, and solder balls SLs are formed by reflow. Thereby, the semiconductor device of the present embodiment is obtained.

  Since the configuration other than the above is substantially the same as the configuration of the first embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof is not repeated. Also in the present embodiment, the same effect as in the first embodiment can be obtained with respect to the pickup of the semiconductor chip CPs. Therefore, the manufacturing efficiency of the semiconductor device (FIG. 24) can be increased.

(Embodiment 4)
FIG. 25 is a flowchart schematically showing a peeling presence / absence determination step in the semiconductor chip pickup method according to the fourth embodiment of the present invention. Referring mainly to FIG. 25, the step of determining whether or not peeling is performed in step S220 (FIG. 5) includes steps S221b to S224b described below.

  In step S221b, as shown by the arrow in FIG. 11, the first piece P1 starts to rise. When the first piece P1 is raised, the second and third pieces P2, P3 are raised together with the first piece P1, as shown in FIG. As shown in FIG. 11, the laser beam LL is irradiated from the laser displacement meter LD to the outer peripheral portion of the semiconductor chip CP. Thereby, the measurement of the speed of the outer peripheral part of the semiconductor chip CP is started. As the first piece P1 rises, the position of the upper surface of the vacuum stage 60 becomes lower than the position of the upper surface of the first piece P1, as shown in FIG. A downward tension T1T is applied. The tension T1T has a downward tension vertical component T1V in addition to the horizontal tension component T1P along the surface of the dicing sheet DS. Due to the tension vertical component T1V, the outer peripheral portion of the semiconductor chip CP bends downward by the bend BD.

  In step S222b, it is determined whether or not the speed of the outer peripheral portion of the semiconductor chip CP is greater than the speed of the first to third pieces P1 to P3.

  As shown in FIG. 12, when the dicing sheet DS is not peeled off, the speed of the outer peripheral portion of the semiconductor chip CP is reduced by the amount of progress of the bending BD in the outer peripheral portion of the semiconductor chip CP. That is, the speed of the outer peripheral portion of the semiconductor chip CP is smaller than the speed of the first to third pieces P1 to P3. Therefore, in step S223b, it is determined that there is no peeling.

  On the other hand, when the dicing sheet DS is peeled off as indicated by the dashed arrows in FIG. 13, the outer peripheral portion of the semiconductor chip CP is not bent. In the process of eliminating this bending, the outer peripheral portion of the semiconductor chip CP is displaced as shown by a solid line arrow (FIG. 13). As a result, the speed of the outer peripheral portion of the semiconductor chip CP is larger than the speed of the first to third pieces P1 to P3 by the amount of the displacement. Therefore, in step S224b, it is determined that there is peeling.

The determination process of the presence or absence of peeling of step S220 (FIG. 5) is thus performed.
Since the configuration other than the above is substantially the same as the configuration of the first embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof is not repeated. In the present embodiment, the same effect as in the first embodiment can be obtained.

(Embodiment 5)
FIG. 26 is a cross sectional view schematically showing a semiconductor chip pick-up device according to a fifth embodiment of the present invention together with a semiconductor chip and a dicing sheet. Referring mainly to FIG. 26, the pickup apparatus of the present embodiment is an apparatus for separating semiconductor chip CP from dicing sheet DS, as in the first embodiment. Further, the pickup device of the present embodiment includes a load cell LC, a load measuring device 51b, and a controller 52b instead of the laser displacement meter LD, the chip position measuring device 51a, and the controller 52a shown in FIG. The load cell LC is a sensor for measuring the load received by the semiconductor chip CP from the first to third pieces P1 to P3. The load measuring device 51b is a device that calculates this load based on a signal from the load cell LC. The controller 52b is a device for controlling the vertical drive device 64 based on the measurement result of the load output from the load measuring device 51b.

  Next, the step of determining whether or not there is peeling in step S220 (FIG. 5) in the pickup step of step S200 (FIG. 2) will be described in detail. FIG. 27 is a flowchart schematically showing a process for determining the presence or absence of peeling in the semiconductor chip pickup method according to the fifth embodiment of the present invention. Referring mainly to FIG. 27, the step of determining whether or not there is peeling in step S220 (FIG. 5) includes steps S221c to S224c described below.

  In step S221c, the first piece P1 (FIG. 20) starts to rise. When the first piece P1 is raised, the second and third pieces P2, P3 (not shown in FIG. 20) are raised together with the first piece P1. Also, measurement of the load received by the semiconductor chip CP from the first to third pieces P1 to P3 is started using the load cell LC (FIG. 26). As the first piece P1 rises, the position of the upper surface of the vacuum stage 60 becomes lower than the position of the upper surface of the first piece P1, as shown in FIG. A downward tension T1T is applied. The tension T1T has a downward tension vertical component T1V in addition to the horizontal tension component T1P along the surface of the dicing sheet DS. This tension vertical component T1V becomes a part of the load detected by the load cell LC.

  In step S222c, it is determined whether or not the load detected by the load cell LC has decreased as a time change.

  As shown in FIG. 21, when the dicing sheet DS is not peeled off at the outer periphery of the semiconductor chip CP, the tension vertical component T1V increases as the first piece P1 rises. For this reason, the load detected by the load cell LC increases as time changes. That is, the load detected by the load cell LC does not decrease as a time change. Therefore, in step S223c, it is determined that there is no peeling.

  Then, when the push-up by the first piece P1 is continued, the dicing sheet DS is peeled from the semiconductor chip CP to which the DAF 81 is attached at the outer peripheral portion of the semiconductor chip CP. As a result, the tension vertical component of the dicing sheet DS decreases, so the load detected by the load cell LC decreases as time changes. Therefore, in step S224c, it is determined that there is peeling.

The determination process of the presence or absence of peeling of step S220 (FIG. 5) is thus performed.
FIG. 28 shows an example of the change over time of the load in the semiconductor chip pickup process. Referring to FIG. 28, load LD1 is an example showing a load detected by load cell LC at the time of pickup. The load LD2 is an example showing a load detected by the load cell LC when a sample once peeled off from the dicing sheet DS in the outer peripheral portion of the semiconductor chip CP is subjected again to the pickup process. The height Hb1 is an example showing a temporal change in the height of the outer peripheral portion of the semiconductor chip CP in the present embodiment. The height Hb2 is an example showing a change in the height of the outer peripheral portion of the semiconductor chip CP when the sample once peeled off from the dicing sheet DS in the outer peripheral portion of the semiconductor chip CP is subjected again to the pick-up process.

  In this example, a sharp increase in the height Hb1 of the outer peripheral portion of the semiconductor chip CP was clearly observed about 61 ms after the start of the process. At this moment, it is considered that the outer peripheral portion of the semiconductor chip CP as shown by the solid line arrow in FIG. At the same time, a sharp decrease in the load LD1 was clearly observed.

  According to the present embodiment, in the step shown in FIG. 27, the separation between the outer peripheral portion of the semiconductor chip CP and the dicing sheet DS is highly accurate based on the load measurement using the load cell LC (FIG. 26). Detected. Therefore, it is possible to prevent the pushing-up (FIG. 7) of step S210 (FIG. 5) from being performed for an unnecessarily long time, so that the pushing-up (FIG. 8) of step S240 (FIG. 5) can be started earlier. it can. Therefore, since the time required for the pickup in step S200 (FIG. 2) can be shortened, the manufacturing efficiency of the semiconductor device (FIG. 1, FIG. 23, or FIG. 24) can be increased.

(Embodiment 6)
FIG. 29 is a flowchart schematically showing a process for determining the presence or absence of peeling in the semiconductor chip pickup method according to the sixth embodiment of the present invention. Referring mainly to FIG. 29, in the present embodiment, the step of determining the presence or absence of peeling in step S220 (FIG. 5) is performed as follows.

First, similarly to the fifth embodiment, steps S221c and S222c are performed.
As shown in FIG. 21, when the dicing sheet DS is not peeled off at the outer peripheral portion of the semiconductor chip CP, it is determined that there is no peeling in step S223c as in the fifth embodiment.

  And if pushing up by the 1st piece P1 is continued, peeling of the dicing sheet DS will begin to occur in the outer periphery of the semiconductor chip CP. As a result, since the tension vertical component of the dicing sheet DS is reduced, the load measured by the load cell LC is reduced as a time change. Therefore, the process proceeds to step S221d.

  In step S221d, the load is measured again by the load cell LC. If peeling is in progress as shown in FIG. 13, the load does not increase as shown in the period of about 61 to 64 ms in FIG. 28, and therefore it is determined that there is no peeling in step S223d. On the other hand, when peeling is in progress as shown in FIG. 14, the load increases as shown in the period of about 64 to 75 ms in FIG. 28, so that it is determined that peeling is present in step S <b> 224 d.

The determination process of the presence or absence of peeling of step S220 (FIG. 5) is thus performed.
Since the configuration other than the above is substantially the same as the configuration of the fifth embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof will not be repeated. In the present embodiment, the same effect as in the first embodiment can be obtained.

  According to the present embodiment, it is determined that there is peeling when the peeling of the outer peripheral portion of the semiconductor chip CP has almost progressed. Therefore, compared to the fifth embodiment, step S240 (FIG. 5) is started after the dicing sheet DS is more sufficiently peeled off from the outer peripheral portion of the semiconductor chip CP. Therefore, it is possible to prevent step S240 from being started when the dicing sheet DS is insufficiently peeled from the outer peripheral portion of the semiconductor chip CP.

  If step S240 is started when the dicing sheet DS is not sufficiently peeled off from the outer periphery of the semiconductor chip CP, the peeling of the dicing sheet DS does not progress, so that the semiconductor chip CP is not separated or the semiconductor chip CP is not separated. It may break.

(Embodiment 7)
FIG. 30 is a cross sectional view schematically showing a semiconductor chip pick-up device according to a seventh embodiment of the present invention together with a semiconductor chip and a dicing sheet. Referring to FIG. 30, the pickup device of the present embodiment has a controller 52c. The controller 52c is a device for controlling the vertical drive device 64 based on signals from each of the chip position measuring device 51a and the load measuring device 51b.

  Since the configuration other than the above is substantially the same as the configuration of the first or fifth embodiment described above, the same or corresponding elements are denoted by the same reference numerals, and description thereof will not be repeated.

According to the present embodiment, the same effect as in the first and fifth embodiments can be obtained.
In the first to seventh embodiments, DAF 81 is used for die bonding, but the present invention is not limited to this, and for example, die bonding using a paste material may be performed.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention relates to a semiconductor chip pickup method and a semiconductor device manufacturing method.

1 is a cross sectional view schematically showing a configuration of a semiconductor device in a first embodiment of the present invention. It is a flowchart which shows schematically the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is sectional drawing which shows schematically the pick-up apparatus of the semiconductor chip in Embodiment 1 of this invention with a semiconductor chip and a dicing sheet. FIG. 4 is a plan view schematically showing a positional relationship between a semiconductor chip and a dicing sheet and a pickup device in FIG. 3. It is a flowchart which shows schematically the pick-up method of the semiconductor chip in Embodiment 1 of this invention. It is sectional drawing which shows schematically the 1st process of the pick-up method of the semiconductor chip in Embodiment 1 of this invention. It is sectional drawing which shows schematically the 2nd process of the pick-up method of the semiconductor chip in Embodiment 1 of this invention. It is sectional drawing which shows schematically the 3rd process of the pick-up method of the semiconductor chip in Embodiment 1 of this invention. It is sectional drawing which shows schematically the 4th process of the pick-up method of the semiconductor chip in Embodiment 1 of this invention. It is a flowchart which shows roughly the determination process of the presence or absence of peeling in the pick-up method of the semiconductor chip in Embodiment 1 of this invention. It is sectional drawing which shows roughly the 1st process of the determination process of the presence or absence of peeling in the pick-up method of the semiconductor chip in Embodiment 1 of this invention. It is sectional drawing which shows schematically the 2nd process of the determination process of the presence or absence of peeling in the pick-up method of the semiconductor chip in Embodiment 1 of this invention. It is sectional drawing which shows roughly the 3rd process of the determination process of the presence or absence of peeling in the pick-up method of the semiconductor chip in Embodiment 1 of this invention. It is sectional drawing which shows roughly the 4th process of the determination process of the presence or absence of peeling in the pick-up method of the semiconductor chip in Embodiment 1 of this invention. It is an example which shows the time change of the height of the outer peripheral part of a semiconductor chip in the pick-up process of a semiconductor chip. It is sectional drawing which shows roughly the 1st process of peeling of the dicing sheet in the outer peripheral part of the semiconductor chip which has thickness exceeding 150 micrometers. It is sectional drawing which shows roughly the 2nd process of peeling of the dicing sheet in the outer peripheral part of the semiconductor chip which has thickness exceeding 150 micrometers. It is sectional drawing which shows roughly the 3rd process of peeling of the dicing sheet in the outer peripheral part of the semiconductor chip which has thickness exceeding 150 micrometers. It is a figure which shows the relationship between the relative height position of the upper surface of a vacuum stage with respect to the upper surface of a 1st piece, and peeling force. It is sectional drawing which shows roughly the 1st process of peeling of the dicing sheet in the outer peripheral part of the semiconductor chip which has a thickness of 150 micrometers or less. It is sectional drawing which shows roughly the 2nd process of peeling of the dicing sheet in the outer peripheral part of the semiconductor chip which has a thickness of 150 micrometers or less. It is sectional drawing which shows roughly the 3rd process of peeling of the dicing sheet in the outer peripheral part of the semiconductor chip which has a thickness of 150 micrometers or less. It is sectional drawing which shows schematically the structure of the semiconductor device in Embodiment 2 of this invention. It is sectional drawing which shows schematically the structure of the semiconductor device in Embodiment 3 of this invention. It is a flowchart which shows schematically the determination process of the presence or absence of peeling in the pick-up method of the semiconductor chip in Embodiment 4 of this invention. It is sectional drawing which shows schematically the pick-up apparatus of the semiconductor chip in Embodiment 5 of this invention with a semiconductor chip and a dicing sheet. It is a flowchart which shows schematically the determination process of the presence or absence of peeling in the pick-up method of the semiconductor chip in Embodiment 5 of this invention. It is an example which shows the time change of the load in the pick-up process of a semiconductor chip. It is a flowchart which shows schematically the determination process of the presence or absence of peeling in the pick-up method of the semiconductor chip in Embodiment 6 of this invention. It is sectional drawing which shows schematically the pick-up apparatus of the semiconductor chip in Embodiment 7 of this invention with a semiconductor chip and a dicing sheet.

Explanation of symbols

  CP semiconductor chip, DS dicing sheet, LC load cell, LD laser displacement meter, LL laser light, P1 to P3, first to third pieces, 81 DAF, 51a chip position measuring device, 51b load measuring device, 52a to 52c controller, 53 suction head, 60 vacuum stage.

Claims (12)

A step of preparing a sheet having a pasting region to which a semiconductor chip is pasted, and an surrounding region surrounding the pasting region;
A step of pushing up the semiconductor chip through the pasting area while fixing the surrounding area,
The step of pushing up includes a step of detecting separation between the outer periphery of the semiconductor chip and the sheet based on the measurement related to the displacement of the outer periphery of the semiconductor chip,
A method for picking up a semiconductor chip, further comprising a step of separating the semiconductor chip from the sheet after the step of detecting the peeling.   The method of picking up a semiconductor chip according to claim 1, wherein the step of detecting the peeling is performed by detecting coincidence between a distance at which the semiconductor chip is pushed up and a displacement amount of the outer peripheral portion.   The semiconductor chip pickup according to claim 1, wherein the step of detecting the peeling is performed by detecting that a displacement speed of the outer peripheral portion is larger than a speed at which the semiconductor chip is pushed up. Method.   The semiconductor chip pickup method according to claim 1, wherein the step of detecting the peeling includes a step of irradiating the outer peripheral portion with a laser beam.   The semiconductor chip pickup method according to claim 1, wherein the semiconductor chip has a thickness of 150 μm or less. A step of preparing a sheet having a pasting region to which a semiconductor chip is pasted, and an surrounding region surrounding the pasting region;
A step of pushing up the semiconductor chip through the pasting area while fixing the surrounding area,
The step of pushing up includes a step of detecting separation between an outer peripheral portion of the semiconductor chip and the sheet based on a measurement related to a force for pushing up the semiconductor chip,
A method for picking up a semiconductor chip, further comprising a step of separating the semiconductor chip from the sheet after the step of detecting the peeling.   The method of picking up a semiconductor chip according to claim 6, wherein the step of detecting the peeling includes a step of detecting a decrease in the force.   8. The method of picking up a semiconductor chip according to claim 7, wherein the step of detecting the peeling includes a step of detecting the increase in the force after the step of detecting the decrease in the force.   The semiconductor chip pickup method according to claim 1, wherein the pushing-up step is performed by pushing up a portion surrounded by the outer peripheral portion.   The method for picking up a semiconductor chip according to claim 9, wherein the separating step includes a step of selectively pushing up a part of the portion surrounded by the outer peripheral portion. Including a step of picking up the semiconductor chip by the method of picking up a semiconductor chip according to claim 1,
The step of preparing the sheet includes a step of attaching a wafer on which the semiconductor chip is formed on the sheet, and a step of dicing the wafer.
A method for manufacturing a semiconductor device, further comprising a step of bonding the semiconductor chip to a base material after the step of picking up.   The method of manufacturing a semiconductor device according to claim 11, wherein the base material is any one of a lead frame, a BGA substrate, and an electronic component.

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